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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2012-12-28 09:57:11 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2012-12-28 09:57:11 +0000
commitfb1b2273837207d71bdb2e676a10a934eb8fb7a7 (patch)
tree2259be0d0a81df7c7209909ad40fda6b68559131 /os/hal/platforms/STM32F3xx/adc_lld.h
parenta77c78a51ccf7a64dd5414300fe61b39c81732d2 (diff)
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4980 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32F3xx/adc_lld.h')
-rw-r--r--os/hal/platforms/STM32F3xx/adc_lld.h21
1 files changed, 19 insertions, 2 deletions
diff --git a/os/hal/platforms/STM32F3xx/adc_lld.h b/os/hal/platforms/STM32F3xx/adc_lld.h
index 8d13caf87..f5e59967c 100644
--- a/os/hal/platforms/STM32F3xx/adc_lld.h
+++ b/os/hal/platforms/STM32F3xx/adc_lld.h
@@ -126,14 +126,28 @@
/** @} */
/**
- * @name ADC clock modes
+ * @name CCR register configuration helpers
* @{
*/
+#define ADC_CCR_DUAL_MASK (31 << 0)
+#define ADC_CCR_DUAL(n) ((n) << 0)
+#define ADC_CCR_DELAY_MASK (15 << 8)
+#define ADC_CCR_DELAY(n) ((n) << 8)
+#define ADC_CCR_DMACFG_MASK (1 << 13)
+#define ADC_CCR_DMACFG_ONESHOT (0 << 13)
+#define ADC_CCR_DMACFG_CIRCULAR (1 << 13)
+#define ADC_CCR_MDMA_MASK (3 << 14)
+#define ADC_CCR_MDMA_DISABLED (0 << 14)
+#define ADC_CCR_MDMA_WORD (1 << 14)
+#define ADC_CCR_MDMA_HWORD (3 << 14)
#define ADC_CCR_CKMODE_MASK (3 << 16)
#define ADC_CCR_CKMODE_ADCCK (0 << 16)
#define ADC_CCR_CKMODE_AHB_DIV1 (1 << 16)
#define ADC_CCR_CKMODE_AHB_DIV2 (2 << 16)
#define ADC_CCR_CKMODE_AHB_DIV4 (3 << 16)
+#define ADC_CCR_VREFEN (1 << 22)
+#define ADC_CCR_TSEN (1 << 23)
+#define ADC_CCR_VBATEN (1 << 24)
/** @} */
/*===========================================================================*/
@@ -422,7 +436,10 @@ typedef struct {
* @brief Slave ADC SQRx register initialization data.
*/
uint32_t ssqr[4];
-
+ /**
+ * @brief ADC CCR register initialization data.
+ */
+ uint32_t ccr;
#endif /* STM32_ADC_DUAL_MODE */
} ADCConversionGroup;