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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-03-03 08:45:54 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-03-03 08:45:54 +0000 |
| commit | 033585af1abc8f609f3104419023457dec1cfd72 (patch) | |
| tree | 74d844a6ff770261f092b041495b9a5da59ae9b3 /os/hal/platforms/STM32F37x/hal_lld.c | |
| parent | b2a6a639f874bdf2a731995b191ad0ca65ca65ed (diff) | |
| download | ChibiOS-033585af1abc8f609f3104419023457dec1cfd72.tar.gz ChibiOS-033585af1abc8f609f3104419023457dec1cfd72.tar.bz2 ChibiOS-033585af1abc8f609f3104419023457dec1cfd72.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5345 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32F37x/hal_lld.c')
| -rw-r--r-- | os/hal/platforms/STM32F37x/hal_lld.c | 14 |
1 files changed, 5 insertions, 9 deletions
diff --git a/os/hal/platforms/STM32F37x/hal_lld.c b/os/hal/platforms/STM32F37x/hal_lld.c index 1a61bec91..d3d809662 100644 --- a/os/hal/platforms/STM32F37x/hal_lld.c +++ b/os/hal/platforms/STM32F37x/hal_lld.c @@ -136,9 +136,6 @@ void hal_lld_init(void) { /* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
-
- /* USB IRQ relocated to not conflict with CAN.*/
- SYSCFG->CFGR1 |= SYSCFG_CFGR1_USB_IT_RMP;
}
/**
@@ -182,13 +179,12 @@ void stm32_clock_init(void) { #endif
/* Clock settings.*/
- RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL |
- STM32_PLLSRC | STM32_PPRE1 | STM32_PPRE2 |
+ RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL |
+ STM32_PLLSRC | STM32_PPRE1 | STM32_PPRE2 |
STM32_HPRE;
- RCC->CFGR2 = STM32_ADC34PRES | STM32_ADC12PRES | STM32_PREDIV;
- RCC->CFGR3 = STM32_UART5SW | STM32_UART4SW | STM32_USART3SW |
- STM32_USART2SW | STM32_TIM8SW | STM32_TIM1SW |
- STM32_I2C2SW | STM32_I2C1SW | STM32_USART1SW;
+ RCC->CFGR2 = STM32_PREDIV;
+ RCC->CFGR3 = STM32_USART3SW | STM32_USART2SW | STM32_I2C2SW |
+ STM32_I2C1SW | STM32_USART1SW;
#if STM32_ACTIVATE_PLL
/* PLL activation.*/
|