diff options
author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2014-03-22 11:30:59 +0000 |
---|---|---|
committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2014-03-22 11:30:59 +0000 |
commit | dc5d7d2592a63ef533c77098b8b02425ece155b7 (patch) | |
tree | 7932e4e47fd9288f9c238e3e4096835bbf0b373a /os/hal/platforms/STM32F37x/adc_lld.c | |
parent | e12b846cda85f36535f8a88fb83e6ada3cd4bff8 (diff) | |
download | ChibiOS-dc5d7d2592a63ef533c77098b8b02425ece155b7.tar.gz ChibiOS-dc5d7d2592a63ef533c77098b8b02425ece155b7.tar.bz2 ChibiOS-dc5d7d2592a63ef533c77098b8b02425ece155b7.zip |
Fixed bug #479.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6798 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32F37x/adc_lld.c')
-rw-r--r-- | os/hal/platforms/STM32F37x/adc_lld.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/os/hal/platforms/STM32F37x/adc_lld.c b/os/hal/platforms/STM32F37x/adc_lld.c index cd8467f21..411c3a086 100644 --- a/os/hal/platforms/STM32F37x/adc_lld.c +++ b/os/hal/platforms/STM32F37x/adc_lld.c @@ -433,7 +433,7 @@ void adc_lld_start(ADCDriver *adcp) { (void *)adcp);
chDbgAssert(!b, "adc_lld_start(), #3", "stream already allocated");
dmaStreamSetPeripheral(adcp->dmastp, &SDADC2->JDATAR);
- rccEnableSDADC1(FALSE);
+ rccEnableSDADC2(FALSE);
PWR->CR |= PWR_CR_SDADC2EN;
adcp->sdadc->CR2 = 0;
adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) &
@@ -450,7 +450,7 @@ void adc_lld_start(ADCDriver *adcp) { (void *)adcp);
chDbgAssert(!b, "adc_lld_start(), #4", "stream already allocated");
dmaStreamSetPeripheral(adcp->dmastp, &SDADC3->JDATAR);
- rccEnableSDADC1(FALSE);
+ rccEnableSDADC3(FALSE);
PWR->CR |= PWR_CR_SDADC3EN;
adcp->sdadc->CR2 = 0;
adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) &
@@ -589,11 +589,16 @@ void adc_lld_start_conversion(ADCDriver *adcp) { adcp->sdadc->CONFCHR1 = grpp->u.sdadc.confchr[0];
adcp->sdadc->CONFCHR2 = grpp->u.sdadc.confchr[1];
+ /* SDADC trigger modes, this write must be performed when
+ SDADC_CR1_INIT=1.*/
+ adcp->sdadc->CR2 = cr2;
+
/* Leaving initialization mode.*/
adcp->sdadc->CR1 &= ~SDADC_CR1_INIT;
- /* SDADC conversion start, the start is performed using the method
- specified in the CR2 configuration, usually SDADC_CR2_JSWSTART.*/
+ /* Special case, if SDADC_CR2_JSWSTART is specified it has to be
+ written after SDADC_CR1_INIT has been set to zero. Just a write is
+ performed, any other bit is ingore if not in initialization mode.*/
adcp->sdadc->CR2 = cr2;
}
#endif /* STM32_ADC_USE_SDADC */
|