diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2010-03-22 12:29:20 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2010-03-22 12:29:20 +0000 |
| commit | 167f5bc8781dd66539cd5db5a48f465457d9a8bb (patch) | |
| tree | 109075fca4b5ebf8d5f7418e5bb5280564adc7f4 /os/hal/platforms/STM32/pwm_lld.h | |
| parent | 51d47eb0795fb2acf0b374c0e348384654d84b17 (diff) | |
| download | ChibiOS-167f5bc8781dd66539cd5db5a48f465457d9a8bb.tar.gz ChibiOS-167f5bc8781dd66539cd5db5a48f465457d9a8bb.tar.bz2 ChibiOS-167f5bc8781dd66539cd5db5a48f465457d9a8bb.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1769 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32/pwm_lld.h')
| -rw-r--r-- | os/hal/platforms/STM32/pwm_lld.h | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/os/hal/platforms/STM32/pwm_lld.h b/os/hal/platforms/STM32/pwm_lld.h index 3a772d023..9e7cbd080 100644 --- a/os/hal/platforms/STM32/pwm_lld.h +++ b/os/hal/platforms/STM32/pwm_lld.h @@ -80,34 +80,38 @@ /**
* @brief PWM1 interrupt priority level setting.
- * @note @p BASEPRI_KERNEL >= @p STM32_PWM1_IRQ_PRIORITY > @p PRIORITY_PENDSV.
+ * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_PWM1_IRQ_PRIORITY >
+ * @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_PWM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_PWM1_IRQ_PRIORITY 0x70
+#define STM32_PWM1_IRQ_PRIORITY CORTEX_PRIORITY(7)
#endif
/**
* @brief PWM2 interrupt priority level setting.
- * @note @p BASEPRI_KERNEL >= @p STM32_PWM2_IRQ_PRIORITY > @p PRIORITY_PENDSV.
+ * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_PWM2_IRQ_PRIORITY >
+ * @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_PWM2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_PWM2_IRQ_PRIORITY 0x70
+#define STM32_PWM2_IRQ_PRIORITY CORTEX_PRIORITY(7)
#endif
/**
* @brief PWM3 interrupt priority level setting.
- * @note @p BASEPRI_KERNEL >= @p STM32_PWM3_IRQ_PRIORITY > @p PRIORITY_PENDSV.
+ * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_PWM3_IRQ_PRIORITY >
+ * @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_PWM3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_PWM3_IRQ_PRIORITY 0x70
+#define STM32_PWM3_IRQ_PRIORITY CORTEX_PRIORITY(7)
#endif
/**
* @brief PWM4 interrupt priority level setting.
- * @note @p BASEPRI_KERNEL >= @p STM32_PWM4_IRQ_PRIORITY > @p PRIORITY_PENDSV.
+ * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_PWM4_IRQ_PRIORITY >
+ * @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_PWM4_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_PWM4_IRQ_PRIORITY 0x80
+#define STM32_PWM4_IRQ_PRIORITY CORTEX_PRIORITY(7)
#endif
/*===========================================================================*/
|