diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-09-02 09:48:38 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-09-02 09:48:38 +0000 |
| commit | 74b860fee65ca8feb2a796144976ff6c44e64bcc (patch) | |
| tree | 3ef638c9e13287040805ebcef40f84b57436c5d3 /os/hal/platforms/STM32/OTGv1 | |
| parent | 2b7a306c13738545059f7b67d5ee8b92ec399687 (diff) | |
| download | ChibiOS-74b860fee65ca8feb2a796144976ff6c44e64bcc.tar.gz ChibiOS-74b860fee65ca8feb2a796144976ff6c44e64bcc.tar.bz2 ChibiOS-74b860fee65ca8feb2a796144976ff6c44e64bcc.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6242 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32/OTGv1')
| -rw-r--r-- | os/hal/platforms/STM32/OTGv1/stm32_otg.h | 916 | ||||
| -rw-r--r-- | os/hal/platforms/STM32/OTGv1/usb_lld.c | 1300 | ||||
| -rw-r--r-- | os/hal/platforms/STM32/OTGv1/usb_lld.h | 534 |
3 files changed, 0 insertions, 2750 deletions
diff --git a/os/hal/platforms/STM32/OTGv1/stm32_otg.h b/os/hal/platforms/STM32/OTGv1/stm32_otg.h deleted file mode 100644 index a78ba57e4..000000000 --- a/os/hal/platforms/STM32/OTGv1/stm32_otg.h +++ /dev/null @@ -1,916 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file stm32_otg.h
- * @brief STM32 OTG registers layout header.
- *
- * @addtogroup USB
- * @{
- */
-
-#ifndef _STM32_OTG_H_
-#define _STM32_OTG_H_
-
-/**
- * @brief Number of the implemented endpoints in OTG_FS.
- * @details This value does not include the endpoint 0 that is always present.
- */
-#define STM32_OTG1_ENDOPOINTS_NUMBER 3
-
-/**
- * @brief Number of the implemented endpoints in OTG_HS.
- * @details This value does not include the endpoint 0 that is always present.
- */
-#define STM32_OTG2_ENDOPOINTS_NUMBER 5
-
-/**
- * @brief OTG_FS FIFO memory size in words.
- */
-#define STM32_OTG1_FIFO_MEM_SIZE 384
-
-/**
- * @brief OTG_HS FIFO memory size in words.
- */
-#define STM32_OTG2_FIFO_MEM_SIZE 1024
-
-/**
- * @brief Host channel registers group.
- */
-typedef struct {
- volatile uint32_t HCCHAR; /**< @brief Host channel characteristics
- register. */
- volatile uint32_t resvd8;
- volatile uint32_t HCINT; /**< @brief Host channel interrupt register.*/
- volatile uint32_t HCINTMSK; /**< @brief Host channel interrupt mask
- register. */
- volatile uint32_t HCTSIZ; /**< @brief Host channel transfer size
- register. */
- volatile uint32_t resvd14;
- volatile uint32_t resvd18;
- volatile uint32_t resvd1c;
-} stm32_otg_host_chn_t;
-
-/**
- * @brief Device input endpoint registers group.
- */
-typedef struct {
- volatile uint32_t DIEPCTL; /**< @brief Device control IN endpoint
- control register. */
- volatile uint32_t resvd4;
- volatile uint32_t DIEPINT; /**< @brief Device IN endpoint interrupt
- register. */
- volatile uint32_t resvdC;
- volatile uint32_t DIEPTSIZ; /**< @brief Device IN endpoint transfer size
- register. */
- volatile uint32_t resvd14;
- volatile uint32_t DTXFSTS; /**< @brief Device IN endpoint transmit FIFO
- status register. */
- volatile uint32_t resvd1C;
-} stm32_otg_in_ep_t;
-
-/**
- * @brief Device output endpoint registers group.
- */
-typedef struct {
- volatile uint32_t DOEPCTL; /**< @brief Device control OUT endpoint
- control register. */
- volatile uint32_t resvd4;
- volatile uint32_t DOEPINT; /**< @brief Device OUT endpoint interrupt
- register. */
- volatile uint32_t resvdC;
- volatile uint32_t DOEPTSIZ; /**< @brief Device OUT endpoint transfer
- size register. */
- volatile uint32_t resvd14;
- volatile uint32_t resvd18;
- volatile uint32_t resvd1C;
-} stm32_otg_out_ep_t;
-
-/**
- * @brief USB registers memory map.
- */
-typedef struct {
- volatile uint32_t GOTGCTL; /**< @brief OTG control and status register.*/
- volatile uint32_t GOTGINT; /**< @brief OTG interrupt register. */
- volatile uint32_t GAHBCFG; /**< @brief AHB configuration register. */
- volatile uint32_t GUSBCFG; /**< @brief USB configuration register. */
- volatile uint32_t GRSTCTL; /**< @brief Reset register size. */
- volatile uint32_t GINTSTS; /**< @brief Interrupt register. */
- volatile uint32_t GINTMSK; /**< @brief Interrupt mask register. */
- volatile uint32_t GRXSTSR; /**< @brief Receive status debug read
- register. */
- volatile uint32_t GRXSTSP; /**< @brief Receive status read/pop
- register. */
- volatile uint32_t GRXFSIZ; /**< @brief Receive FIFO size register. */
- volatile uint32_t DIEPTXF0; /**< @brief Endpoint 0 transmit FIFO size
- register. */
- volatile uint32_t HNPTXSTS; /**< @brief Non-periodic transmit FIFO/queue
- status register. */
- volatile uint32_t resvd30;
- volatile uint32_t resvd34;
- volatile uint32_t GCCFG; /**< @brief General core configuration. */
- volatile uint32_t CID; /**< @brief Core ID register. */
- volatile uint32_t resvd58[48];
- volatile uint32_t HPTXFSIZ; /**< @brief Host periodic transmit FIFO size
- register. */
- volatile uint32_t DIEPTXF[15];/**< @brief Device IN endpoint transmit FIFO
- size registers. */
- volatile uint32_t resvd140[176];
- volatile uint32_t HCFG; /**< @brief Host configuration register. */
- volatile uint32_t HFIR; /**< @brief Host frame interval register. */
- volatile uint32_t HFNUM; /**< @brief Host frame number/frame time
- Remaining register. */
- volatile uint32_t resvd40C;
- volatile uint32_t HPTXSTS; /**< @brief Host periodic transmit FIFO/queue
- status register. */
- volatile uint32_t HAINT; /**< @brief Host all channels interrupt
- register. */
- volatile uint32_t HAINTMSK; /**< @brief Host all channels interrupt mask
- register. */
- volatile uint32_t resvd41C[9];
- volatile uint32_t HPRT; /**< @brief Host port control and status
- register. */
- volatile uint32_t resvd444[47];
- stm32_otg_host_chn_t hc[16]; /**< @brief Host channels array. */
- volatile uint32_t resvd700[64];
- volatile uint32_t DCFG; /**< @brief Device configuration register. */
- volatile uint32_t DCTL; /**< @brief Device control register. */
- volatile uint32_t DSTS; /**< @brief Device status register. */
- volatile uint32_t resvd80C;
- volatile uint32_t DIEPMSK; /**< @brief Device IN endpoint common
- interrupt mask register. */
- volatile uint32_t DOEPMSK; /**< @brief Device OUT endpoint common
- interrupt mask register. */
- volatile uint32_t DAINT; /**< @brief Device all endpoints interrupt
- register. */
- volatile uint32_t DAINTMSK; /**< @brief Device all endpoints interrupt
- mask register. */
- volatile uint32_t resvd820;
- volatile uint32_t resvd824;
- volatile uint32_t DVBUSDIS; /**< @brief Device VBUS discharge time
- register. */
- volatile uint32_t DVBUSPULSE; /**< @brief Device VBUS pulsing time
- register. */
- volatile uint32_t resvd830;
- volatile uint32_t DIEPEMPMSK; /**< @brief Device IN endpoint FIFO empty
- interrupt mask register. */
- volatile uint32_t resvd838;
- volatile uint32_t resvd83C;
- volatile uint32_t resvd840[16];
- volatile uint32_t resvd880[16];
- volatile uint32_t resvd8C0[16];
- stm32_otg_in_ep_t ie[16]; /**< @brief Input endpoints. */
- stm32_otg_out_ep_t oe[16]; /**< @brief Output endpoints. */
- volatile uint32_t resvdD00[64];
- volatile uint32_t PCGCCTL; /**< @brief Power and clock gating control
- register. */
- volatile uint32_t resvdE04[127];
- volatile uint32_t FIFO[16][1024];
-} stm32_otg_t;
-
-/**
- * @name GOTGCTL register bit definitions
- * @{
- */
-#define GOTGCTL_BSVLD (1U<<19) /**< B-Session Valid. */
-#define GOTGCTL_ASVLD (1U<<18) /**< A-Session Valid. */
-#define GOTGCTL_DBCT (1U<<17) /**< Long/Short debounce time. */
-#define GOTGCTL_CIDSTS (1U<<16) /**< Connector ID status. */
-#define GOTGCTL_DHNPEN (1U<<11) /**< Device HNP enabled. */
-#define GOTGCTL_HSHNPEN (1U<<10) /**< Host Set HNP enable. */
-#define GOTGCTL_HNPRQ (1U<<9) /**< HNP request. */
-#define GOTGCTL_HNGSCS (1U<<8) /**< Host negotiation success. */
-#define GOTGCTL_SRQ (1U<<1) /**< Session request. */
-#define GOTGCTL_SRQSCS (1U<<0) /**< Session request success. */
-/** @} */
-
-/**
- * @name GOTGINT register bit definitions
- * @{
- */
-#define GOTGINT_DBCDNE (1U<<19) /**< Debounce done. */
-#define GOTGINT_ADTOCHG (1U<<18) /**< A-Device timeout change. */
-#define GOTGINT_HNGDET (1U<<17) /**< Host negotiation detected. */
-#define GOTGINT_HNSSCHG (1U<<9) /**< Host negotiation success
- status change. */
-#define GOTGINT_SRSSCHG (1U<<8) /**< Session request success
- status change. */
-#define GOTGINT_SEDET (1U<<2) /**< Session end detected. */
-/** @} */
-
-/**
- * @name GAHBCFG register bit definitions
- * @{
- */
-#define GAHBCFG_PTXFELVL (1U<<8) /**< Periodic TxFIFO empty
- level. */
-#define GAHBCFG_TXFELVL (1U<<7) /**< Non-periodic TxFIFO empty
- level. */
-#define GAHBCFG_DMAEN (1U<<5) /**< DMA enable (HS only). */
-#define GAHBCFG_HBSTLEN_MASK (15U<<1) /**< Burst length/type mask (HS
- only). */
-#define GAHBCFG_HBSTLEN(n) ((n)<<1) /**< Burst length/type (HS
- only). */
-#define GAHBCFG_GINTMSK (1U<<0) /**< Global interrupt mask. */
-/** @} */
-
-/**
- * @name GUSBCFG register bit definitions
- * @{
- */
-#define GUSBCFG_CTXPKT (1U<<31) /**< Corrupt Tx packet. */
-#define GUSBCFG_FDMOD (1U<<30) /**< Force Device Mode. */
-#define GUSBCFG_FHMOD (1U<<29) /**< Force Host Mode. */
-#define GUSBCFG_TRDT_MASK (15U<<10) /**< USB Turnaround time field
- mask. */
-#define GUSBCFG_TRDT(n) ((n)<<10) /**< USB Turnaround time field
- value. */
-#define GUSBCFG_HNPCAP (1U<<9) /**< HNP-Capable. */
-#define GUSBCFG_SRPCAP (1U<<8) /**< SRP-Capable. */
-#define GUSBCFG_PHYSEL (1U<<6) /**< USB 2.0 High-Speed PHY or
- USB 1.1 Full-Speed serial
- transceiver Select. */
-#define GUSBCFG_TOCAL_MASK (7U<<0) /**< HS/FS timeout calibration
- field mask. */
-#define GUSBCFG_TOCAL(n) ((n)<<0) /**< HS/FS timeout calibration
- field value. */
-/** @} */
-
-/**
- * @name GRSTCTL register bit definitions
- * @{
- */
-#define GRSTCTL_AHBIDL (1U<<31) /**< AHB Master Idle. */
-#define GRSTCTL_TXFNUM_MASK (31U<<6) /**< TxFIFO number field mask. */
-#define GRSTCTL_TXFNUM(n) ((n)<<6) /**< TxFIFO number field value. */
-#define GRSTCTL_TXFFLSH (1U<<5) /**< TxFIFO flush. */
-#define GRSTCTL_RXFFLSH (1U<<4) /**< RxFIFO flush. */
-#define GRSTCTL_FCRST (1U<<2) /**< Host frame counter reset. */
-#define GRSTCTL_HSRST (1U<<1) /**< HClk soft reset. */
-#define GRSTCTL_CSRST (1U<<0) /**< Core soft reset. */
-/** @} */
-
-/**
- * @name GINTSTS register bit definitions
- * @{
- */
-#define GINTSTS_WKUPINT (1U<<31) /**< Resume/Remote wakeup
- detected interrupt. */
-#define GINTSTS_SRQINT (1U<<30) /**< Session request/New session
- detected interrupt. */
-#define GINTSTS_DISCINT (1U<<29) /**< Disconnect detected
- interrupt. */
-#define GINTSTS_CIDSCHG (1U<<28) /**< Connector ID status change.*/
-#define GINTSTS_PTXFE (1U<<26) /**< Periodic TxFIFO empty. */
-#define GINTSTS_HCINT (1U<<25) /**< Host channels interrupt. */
-#define GINTSTS_HPRTINT (1U<<24) /**< Host port interrupt. */
-#define GINTSTS_IPXFR (1U<<21) /**< Incomplete periodic
- transfer. */
-#define GINTSTS_IISOOXFR (1U<<21) /**< Incomplete isochronous OUT
- transfer. */
-#define GINTSTS_IISOIXFR (1U<<20) /**< Incomplete isochronous IN
- transfer. */
-#define GINTSTS_OEPINT (1U<<19) /**< OUT endpoints interrupt. */
-#define GINTSTS_IEPINT (1U<<18) /**< IN endpoints interrupt. */
-#define GINTSTS_EOPF (1U<<15) /**< End of periodic frame
- interrupt. */
-#define GINTSTS_ISOODRP (1U<<14) /**< Isochronous OUT packet
- dropped interrupt. */
-#define GINTSTS_ENUMDNE (1U<<13) /**< Enumeration done. */
-#define GINTSTS_USBRST (1U<<12) /**< USB reset. */
-#define GINTSTS_USBSUSP (1U<<11) /**< USB suspend. */
-#define GINTSTS_ESUSP (1U<<10) /**< Early suspend. */
-#define GINTSTS_GONAKEFF (1U<<7) /**< Global OUT NAK effective. */
-#define GINTSTS_GINAKEFF (1U<<6) /**< Global IN non-periodic NAK
- effective. */
-#define GINTSTS_NPTXFE (1U<<5) /**< Non-periodic TxFIFO empty. */
-#define GINTSTS_RXFLVL (1U<<4) /**< RxFIFO non-empty. */
-#define GINTSTS_SOF (1U<<3) /**< Start of frame. */
-#define GINTSTS_OTGINT (1U<<2) /**< OTG interrupt. */
-#define GINTSTS_MMIS (1U<<1) /**< Mode Mismatch interrupt. */
-#define GINTSTS_CMOD (1U<<0) /**< Current mode of operation. */
-/** @} */
-
-/**
- * @name GINTMSK register bit definitions
- * @{
- */
-#define GINTMSK_WKUM (1U<<31) /**< Resume/remote wakeup
- detected interrupt mask. */
-#define GINTMSK_SRQM (1U<<30) /**< Session request/New session
- detected interrupt mask. */
-#define GINTMSK_DISCM (1U<<29) /**< Disconnect detected
- interrupt mask. */
-#define GINTMSK_CIDSCHGM (1U<<28) /**< Connector ID status change
- mask. */
-#define GINTMSK_PTXFEM (1U<<26) /**< Periodic TxFIFO empty mask.*/
-#define GINTMSK_HCM (1U<<25) /**< Host channels interrupt
- mask. */
-#define GINTMSK_HPRTM (1U<<24) /**< Host port interrupt mask. */
-#define GINTMSK_IPXFRM (1U<<21) /**< Incomplete periodic
- transfer mask. */
-#define GINTMSK_IISOOXFRM (1U<<21) /**< Incomplete isochronous OUT
- transfer mask. */
-#define GINTMSK_IISOIXFRM (1U<<20) /**< Incomplete isochronous IN
- transfer mask. */
-#define GINTMSK_OEPM (1U<<19) /**< OUT endpoints interrupt
- mask. */
-#define GINTMSK_IEPM (1U<<18) /**< IN endpoints interrupt
- mask. */
-#define GINTMSK_EOPFM (1U<<15) /**< End of periodic frame
- interrupt mask. */
-#define GINTMSK_ISOODRPM (1U<<14) /**< Isochronous OUT packet
- dropped interrupt mask. */
-#define GINTMSK_ENUMDNEM (1U<<13) /**< Enumeration done mask. */
-#define GINTMSK_USBRSTM (1U<<12) /**< USB reset mask. */
-#define GINTMSK_USBSUSPM (1U<<11) /**< USB suspend mask. */
-#define GINTMSK_ESUSPM (1U<<10) /**< Early suspend mask. */
-#define GINTMSK_GONAKEFFM (1U<<7) /**< Global OUT NAK effective
- mask. */
-#define GINTMSK_GINAKEFFM (1U<<6) /**< Global non-periodic IN NAK
- effective mask. */
-#define GINTMSK_NPTXFEM (1U<<5) /**< Non-periodic TxFIFO empty
- mask. */
-#define GINTMSK_RXFLVLM (1U<<4) /**< Receive FIFO non-empty
- mask. */
-#define GINTMSK_SOFM (1U<<3) /**< Start of (micro)frame mask.*/
-#define GINTMSK_OTGM (1U<<2) /**< OTG interrupt mask. */
-#define GINTMSK_MMISM (1U<<1) /**< Mode Mismatch interrupt
- mask. */
-/** @} */
-
-/**
- * @name GRXSTSR register bit definitions
- * @{
- */
-#define GRXSTSR_PKTSTS_MASK (15U<<17) /**< Packet status mask. */
-#define GRXSTSR_PKTSTS(n) ((n)<<17) /**< Packet status value. */
-#define GRXSTSR_OUT_GLOBAL_NAK GRXSTSR_PKTSTS(1)
-#define GRXSTSR_OUT_DATA GRXSTSR_PKTSTS(2)
-#define GRXSTSR_OUT_COMP GRXSTSR_PKTSTS(3)
-#define GRXSTSR_SETUP_COMP GRXSTSR_PKTSTS(4)
-#define GRXSTSR_SETUP_DATA GRXSTSR_PKTSTS(6)
-#define GRXSTSR_DPID_MASK (3U<<15) /**< Data PID mask. */
-#define GRXSTSR_DPID(n) ((n)<<15) /**< Data PID value. */
-#define GRXSTSR_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */
-#define GRXSTSR_BCNT(n) ((n)<<4) /**< Byte count value. */
-#define GRXSTSR_CHNUM_MASK (15U<<0) /**< Channel number mask. */
-#define GRXSTSR_CHNUM(n) ((n)<<0) /**< Channel number value. */
-#define GRXSTSR_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */
-#define GRXSTSR_EPNUM(n) ((n)<<0) /**< Endpoint number value. */
-/** @} */
-
-/**
- * @name GRXSTSP register bit definitions
- * @{
- */
-#define GRXSTSP_PKTSTS_MASK (15<<17) /**< Packet status mask. */
-#define GRXSTSP_PKTSTS(n) ((n)<<17) /**< Packet status value. */
-#define GRXSTSP_OUT_GLOBAL_NAK GRXSTSP_PKTSTS(1)
-#define GRXSTSP_OUT_DATA GRXSTSP_PKTSTS(2)
-#define GRXSTSP_OUT_COMP GRXSTSP_PKTSTS(3)
-#define GRXSTSP_SETUP_COMP GRXSTSP_PKTSTS(4)
-#define GRXSTSP_SETUP_DATA GRXSTSP_PKTSTS(6)
-#define GRXSTSP_DPID_MASK (3U<<15) /**< Data PID mask. */
-#define GRXSTSP_DPID(n) ((n)<<15) /**< Data PID value. */
-#define GRXSTSP_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */
-#define GRXSTSP_BCNT_OFF 4 /**< Byte count offset. */
-#define GRXSTSP_BCNT(n) ((n)<<4) /**< Byte count value. */
-#define GRXSTSP_CHNUM_MASK (15U<<0) /**< Channel number mask. */
-#define GRXSTSP_CHNUM(n) ((n)<<0) /**< Channel number value. */
-#define GRXSTSP_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */
-#define GRXSTSP_EPNUM_OFF 0 /**< Endpoint number offset. */
-#define GRXSTSP_EPNUM(n) ((n)<<0) /**< Endpoint number value. */
-/** @} */
-
-/**
- * @name GRXFSIZ register bit definitions
- * @{
- */
-#define GRXFSIZ_RXFD_MASK (0xFFFF<<0) /**< RxFIFO depth mask. */
-#define GRXFSIZ_RXFD(n) ((n)<<0) /**< RxFIFO depth value. */
-/** @} */
-
-/**
- * @name DIEPTXFx register bit definitions
- * @{
- */
-#define DIEPTXF_INEPTXFD_MASK (0xFFFFU<<16)/**< IN endpoint TxFIFO depth
- mask. */
-#define DIEPTXF_INEPTXFD(n) ((n)<<16) /**< IN endpoint TxFIFO depth
- value. */
-#define DIEPTXF_INEPTXSA_MASK (0xFFFF<<0) /**< IN endpoint FIFOx transmit
- RAM start address mask. */
-#define DIEPTXF_INEPTXSA(n) ((n)<<0) /**< IN endpoint FIFOx transmit
- RAM start address value. */
-/** @} */
-
-/**
- * @name GCCFG register bit definitions
- * @{
- */
-#define GCCFG_NOVBUSSENS (1U<<21) /**< VBUS sensing disable. */
-#define GCCFG_SOFOUTEN (1U<<20) /**< SOF output enable. */
-#define GCCFG_VBUSBSEN (1U<<19) /**< Enable the VBUS sensing "B"
- device. */
-#define GCCFG_VBUSASEN (1U<<18) /**< Enable the VBUS sensing "A"
- device. */
-#define GCCFG_PWRDWN (1U<<16) /**< Power down. */
-/** @} */
-
-/**
- * @name HPTXFSIZ register bit definitions
- * @{
- */
-#define HPTXFSIZ_PTXFD_MASK (0xFFFFU<<16)/**< Host periodic TxFIFO
- depth mask. */
-#define HPTXFSIZ_PTXFD(n) ((n)<<16) /**< Host periodic TxFIFO
- depth value. */
-#define HPTXFSIZ_PTXSA_MASK (0xFFFFU<<0)/**< Host periodic TxFIFO
- Start address mask. */
-#define HPTXFSIZ_PTXSA(n) ((n)<<0) /**< Host periodic TxFIFO
- start address value. */
-/** @} */
-
-/**
- * @name HCFG register bit definitions
- * @{
- */
-#define HCFG_FSLSS (1U<<2) /**< FS- and LS-only support. */
-#define HCFG_FSLSPCS_MASK (3U<<0) /**< FS/LS PHY clock select
- mask. */
-#define HCFG_FSLSPCS_48 (1U<<0) /**< PHY clock is running at
- 48 MHz. */
-#define HCFG_FSLSPCS_6 (2U<<0) /**< PHY clock is running at
- 6 MHz. */
-/** @} */
-
-/**
- * @name HFIR register bit definitions
- * @{
- */
-#define HFIR_FRIVL_MASK (0xFFFFU<<0)/**< Frame interval mask. */
-#define HFIR_FRIVL(n) ((n)<<0) /**< Frame interval value. */
-/** @} */
-
-/**
- * @name HFNUM register bit definitions
- * @{
- */
-#define HFNUM_FTREM_MASK (0xFFFFU<<16)/**< Frame time Remaining mask.*/
-#define HFNUM_FTREM(n) ((n)<<16) /**< Frame time Remaining value.*/
-#define HFNUM_FRNUM_MASK (0xFFFFU<<0)/**< Frame number mask. */
-#define HFNUM_FRNUM(n) ((n)<<0) /**< Frame number value. */
-/** @} */
-
-/**
- * @name HPTXSTS register bit definitions
- * @{
- */
-#define HPTXSTS_PTXQTOP_MASK (0xFFU<<24) /**< Top of the periodic
- transmit request queue
- mask. */
-#define HPTXSTS_PTXQTOP(n) ((n)<<24) /**< Top of the periodic
- transmit request queue
- value. */
-#define HPTXSTS_PTXQSAV_MASK (0xFF<<16) /**< Periodic transmit request
- queue Space Available
- mask. */
-#define HPTXSTS_PTXQSAV(n) ((n)<<16) /**< Periodic transmit request
- queue Space Available
- value. */
-#define HPTXSTS_PTXFSAVL_MASK (0xFFFF<<0) /**< Periodic transmit Data
- FIFO Space Available
- mask. */
-#define HPTXSTS_PTXFSAVL(n) ((n)<<0) /**< Periodic transmit Data
- FIFO Space Available
- value. */
-/** @} */
-
-/**
- * @name HAINT register bit definitions
- * @{
- */
-#define HAINT_HAINT_MASK (0xFFFFU<<0)/**< Channel interrupts mask. */
-#define HAINT_HAINT(n) ((n)<<0) /**< Channel interrupts value. */
-/** @} */
-
-/**
- * @name HAINTMSK register bit definitions
- * @{
- */
-#define HAINTMSK_HAINTM_MASK (0xFFFFU<<0)/**< Channel interrupt mask
- mask. */
-#define HAINTMSK_HAINTM(n) ((n)<<0) /**< Channel interrupt mask
- value. */
-/** @} */
-
-/**
- * @name HPRT register bit definitions
- * @{
- */
-#define HPRT_PSPD_MASK (3U<<17) /**< Port speed mask. */
-#define HPRT_PSPD_FS (1U<<17) /**< Full speed value. */
-#define HPRT_PSPD_LS (2U<<17) /**< Low speed value. */
-#define HPRT_PTCTL_MASK (15<<13) /**< Port Test control mask. */
-#define HPRT_PTCTL(n) ((n)<<13) /**< Port Test control value. */
-#define HPRT_PPWR (1U<<12) /**< Port power. */
-#define HPRT_PLSTS_MASK (3U<<11) /**< Port Line status mask. */
-#define HPRT_PLSTS_DM (1U<<11) /**< Logic level of D-. */
-#define HPRT_PLSTS_DP (1U<<10) /**< Logic level of D+. */
-#define HPRT_PRST (1U<<8) /**< Port reset. */
-#define HPRT_PSUSP (1U<<7) /**< Port suspend. */
-#define HPRT_PRES (1U<<6) /**< Port Resume. */
-#define HPRT_POCCHNG (1U<<5) /**< Port overcurrent change. */
-#define HPRT_POCA (1U<<4) /**< Port overcurrent active. */
-#define HPRT_PENCHNG (1U<<3) /**< Port enable/disable change.*/
-#define HPRT_PENA (1U<<2) /**< Port enable. */
-#define HPRT_PCDET (1U<<1) /**< Port Connect detected. */
-#define HPRT_PCSTS (1U<<0) /**< Port connect status. */
-/** @} */
-
-/**
- * @name HCCHAR register bit definitions
- * @{
- */
-#define HCCHAR_CHENA (1U<<31) /**< Channel enable. */
-#define HCCHAR_CHDIS (1U<<30) /**< Channel Disable. */
-#define HCCHAR_ODDFRM (1U<<29) /**< Odd frame. */
-#define HCCHAR_DAD_MASK (0x7FU<<22) /**< Device Address mask. */
-#define HCCHAR_DAD(n) ((n)<<22) /**< Device Address value. */
-#define HCCHAR_MCNT_MASK (3U<<20) /**< Multicount mask. */
-#define HCCHAR_MCNT(n) ((n)<<20) /**< Multicount value. */
-#define HCCHAR_EPTYP_MASK (3U<<18) /**< Endpoint type mask. */
-#define HCCHAR_EPTYP(n) ((n)<<18) /**< Endpoint type value. */
-#define HCCHAR_EPTYP_CTL (0U<<18) /**< Control endpoint value. */
-#define HCCHAR_EPTYP_ISO (1U<<18) /**< Isochronous endpoint value.*/
-#define HCCHAR_EPTYP_BULK (2U<<18) /**< Bulk endpoint value. */
-#define HCCHAR_EPTYP_INTR (3U<<18) /**< Interrupt endpoint value. */
-#define HCCHAR_LSDEV (1U<<17) /**< Low-Speed device. */
-#define HCCHAR_EPDIR (1U<<15) /**< Endpoint direction. */
-#define HCCHAR_EPNUM_MASK (15U<<11) /**< Endpoint number mask. */
-#define HCCHAR_EPNUM(n) ((n)<<11) /**< Endpoint number value. */
-#define HCCHAR_MPS_MASK (11U<<0) /**< Maximum packet size mask. */
-#define HCCHAR_MPS(n) (11U<<0) /**< Maximum packet size value. */
-/** @} */
-
-/**
- * @name HCINT register bit definitions
- * @{
- */
-#define HCINT_DTERR (1U<<10) /**< Data toggle error. */
-#define HCINT_FRMOR (1U<<9) /**< Frame overrun. */
-#define HCINT_BBERR (1U<<8) /**< Babble error. */
-#define HCINT_TRERR (1U<<7) /**< Transaction Error. */
-#define HCINT_ACK (1U<<5) /**< ACK response
- received/transmitted
- interrupt. */
-#define HCINT_NAK (1U<<4) /**< NAK response received
- interrupt. */
-#define HCINT_STALL (1U<<3) /**< STALL response received
- interrupt. */
-#define HCINT_CHH (1U<<1) /**< Channel halted. */
-#define HCINT_XFRC (1U<<0) /**< Transfer completed. */
-/** @} */
-
-/**
- * @name HCINTMSK register bit definitions
- * @{
- */
-#define HCINTMSK_DTERRM (1U<<10) /**< Data toggle error mask. */
-#define HCINTMSK_FRMORM (1U<<9) /**< Frame overrun mask. */
-#define HCINTMSK_BBERRM (1U<<8) /**< Babble error mask. */
-#define HCINTMSK_TRERRM (1U<<7) /**< Transaction error mask. */
-#define HCINTMSK_NYET (1U<<6) /**< NYET response received
- interrupt mask. */
-#define HCINTMSK_ACKM (1U<<5) /**< ACK Response
- received/transmitted
- interrupt mask. */
-#define HCINTMSK_NAKM (1U<<4) /**< NAK response received
- interrupt mask. */
-#define HCINTMSK_STALLM (1U<<3) /**< STALL response received
- interrupt mask. */
-#define HCINTMSK_CHHM (1U<<1) /**< Channel halted mask. */
-#define HCINTMSK_XFRCM (1U<<0) /**< Transfer completed mask. */
-/** @} */
-
-/**
- * @name HCTSIZ register bit definitions
- * @{
- */
-#define HCTSIZ_DPID_MASK (3U<<29) /**< PID mask. */
-#define HCTSIZ_DPID_DATA0 (0U<<29) /**< DATA0. */
-#define HCTSIZ_DPID_DATA2 (1U<<29) /**< DATA2. */
-#define HCTSIZ_DPID_DATA1 (2U<<29) /**< DATA1. */
-#define HCTSIZ_DPID_MDATA (3U<<29) /**< MDATA. */
-#define HCTSIZ_PKTCNT_MASK (0x3FFU<<19)/**< Packet count mask. */
-#define HCTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */
-#define HCTSIZ_XFRSIZ_MASK (0x7FFFF<<0)/**< Transfer size mask. */
-#define HCTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */
-/** @} */
-
-/**
- * @name DCFG register bit definitions
- * @{
- */
-#define DCFG_PFIVL_MASK (3U<<11) /**< Periodic frame interval
- mask. */
-#define DCFG_PFIVL(n) ((n)<<11) /**< Periodic frame interval
- value. */
-#define DCFG_DAD_MASK (0x7FU<<4) /**< Device address mask. */
-#define DCFG_DAD(n) ((n)<<4) /**< Device address value. */
-#define DCFG_NZLSOHSK (1U<<2) /**< Non-Zero-Length status
- OUT handshake. */
-#define DCFG_DSPD_MASK (3U<<0) /**< Device speed mask. */
-#define DCFG_DSPD_HS (0U<<0) /**< High speed (USB 2.0). */
-#define DCFG_DSPD_HS_FS (1U<<0) /**< High speed (USB 2.0) in FS
- mode. */
-#define DCFG_DSPD_FS11 (3U<<0) /**< Full speed (USB 1.1
- transceiver clock is 48
- MHz). */
-/** @} */
-
-/**
- * @name DCTL register bit definitions
- * @{
- */
-#define DCTL_POPRGDNE (1U<<11) /**< Power-on programming done. */
-#define DCTL_CGONAK (1U<<10) /**< Clear global OUT NAK. */
-#define DCTL_SGONAK (1U<<9) /**< Set global OUT NAK. */
-#define DCTL_CGINAK (1U<<8) /**< Clear global non-periodic
- IN NAK. */
-#define DCTL_SGINAK (1U<<7) /**< Set global non-periodic
- IN NAK. */
-#define DCTL_TCTL_MASK (7U<<4) /**< Test control mask. */
-#define DCTL_TCTL(n) ((n)<<4 /**< Test control value. */
-#define DCTL_GONSTS (1U<<3) /**< Global OUT NAK status. */
-#define DCTL_GINSTS (1U<<2) /**< Global non-periodic IN
- NAK status. */
-#define DCTL_SDIS (1U<<1) /**< Soft disconnect. */
-#define DCTL_RWUSIG (1U<<0) /**< Remote wakeup signaling. */
-/** @} */
-
-/**
- * @name DSTS register bit definitions
- * @{
- */
-#define DSTS_FNSOF_MASK (0x3FFU<<8) /**< Frame number of the received
- SOF mask. */
-#define DSTS_FNSOF(n) ((n)<<8) /**< Frame number of the received
- SOF value. */
-#define DSTS_EERR (1U<<3) /**< Erratic error. */
-#define DSTS_ENUMSPD_MASK (3U<<1) /**< Enumerated speed mask. */
-#define DSTS_ENUMSPD_FS_48 (3U<<1) /**< Full speed (PHY clock is
- running at 48 MHz). */
-#define DSTS_SUSPSTS (1U<<0) /**< Suspend status. */
-/** @} */
-
-/**
- * @name DIEPMSK register bit definitions
- * @{
- */
-#define DIEPMSK_TXFEM (1U<<6) /**< Transmit FIFO empty mask. */
-#define DIEPMSK_INEPNEM (1U<<6) /**< IN endpoint NAK effective
- mask. */
-#define DIEPMSK_ITTXFEMSK (1U<<4) /**< IN token received when
- TxFIFO empty mask. */
-#define DIEPMSK_TOCM (1U<<3) /**< Timeout condition mask. */
-#define DIEPMSK_EPDM (1U<<1) /**< Endpoint disabled
- interrupt mask. */
-#define DIEPMSK_XFRCM (1U<<0) /**< Transfer completed
- interrupt mask. */
-/** @} */
-
-/**
- * @name DOEPMSK register bit definitions
- * @{
- */
-#define DOEPMSK_OTEPDM (1U<<4) /**< OUT token received when
- endpoint disabled mask. */
-#define DOEPMSK_STUPM (1U<<3) /**< SETUP phase done mask. */
-#define DOEPMSK_EPDM (1U<<1) /**< Endpoint disabled
- interrupt mask. */
-#define DOEPMSK_XFRCM (1U<<0) /**< Transfer completed
- interrupt mask. */
-/** @} */
-
-/**
- * @name DAINT register bit definitions
- * @{
- */
-#define DAINT_OEPINT_MASK (0xFFFFU<<16)/**< OUT endpoint interrupt
- bits mask. */
-#define DAINT_OEPINT(n) ((n)<<16) /**< OUT endpoint interrupt
- bits value. */
-#define DAINT_IEPINT_MASK (0xFFFFU<<0)/**< IN endpoint interrupt
- bits mask. */
-#define DAINT_IEPINT(n) ((n)<<0) /**< IN endpoint interrupt
- bits value. */
-/** @} */
-
-/**
- * @name DAINTMSK register bit definitions
- * @{
- */
-#define DAINTMSK_OEPM_MASK (0xFFFFU<<16)/**< OUT EP interrupt mask
- bits mask. */
-#define DAINTMSK_OEPM(n) (1U<<(16+(n)))/**< OUT EP interrupt mask
- bits value. */
-#define DAINTMSK_IEPM_MASK (0xFFFFU<<0)/**< IN EP interrupt mask
- bits mask. */
-#define DAINTMSK_IEPM(n) (1U<<(n)) /**< IN EP interrupt mask
- bits value. */
-/** @} */
-
-/**
- * @name DVBUSDIS register bit definitions
- * @{
- */
-#define DVBUSDIS_VBUSDT_MASK (0xFFFFU<<0)/**< Device VBUS discharge
- time mask. */
-#define DVBUSDIS_VBUSDT(n) ((n)<<0) /**< Device VBUS discharge
- time value. */
-/** @} */
-
-/**
- * @name DVBUSPULSE register bit definitions
- * @{
- */
-#define DVBUSPULSE_DVBUSP_MASK (0xFFFU<<0) /**< Device VBUSpulsing time
- mask. */
-#define DVBUSPULSE_DVBUSP(n) ((n)<<0) /**< Device VBUS pulsing time
- value. */
-/** @} */
-
-/**
- * @name DIEPEMPMSK register bit definitions
- * @{
- */
-#define DIEPEMPMSK_INEPTXFEM(n) (1U<<(n)) /**< IN EP Tx FIFO empty
- interrupt mask bit. */
-/** @} */
-
-/**
- * @name DIEPCTL register bit definitions
- * @{
- */
-#define DIEPCTL_EPENA (1U<<31) /**< Endpoint enable. */
-#define DIEPCTL_EPDIS (1U<<30) /**< Endpoint disable. */
-#define DIEPCTL_SD1PID (1U<<29) /**< Set DATA1 PID. */
-#define DIEPCTL_SODDFRM (1U<<29) /**< Set odd frame. */
-#define DIEPCTL_SD0PID (1U<<28) /**< Set DATA0 PID. */
-#define DIEPCTL_SEVNFRM (1U<<28) /**< Set even frame. */
-#define DIEPCTL_SNAK (1U<<27) /**< Set NAK. */
-#define DIEPCTL_CNAK (1U<<26) /**< Clear NAK. */
-#define DIEPCTL_TXFNUM_MASK (15U<<22) /**< TxFIFO number mask. */
-#define DIEPCTL_TXFNUM(n) ((n)<<22) /**< TxFIFO number value. */
-#define DIEPCTL_STALL (1U<<21) /**< STALL handshake. */
-#define DIEPCTL_SNPM (1U<<20) /**< Snoop mode. */
-#define DIEPCTL_EPTYP_MASK (3<<18) /**< Endpoint type mask. */
-#define DIEPCTL_EPTYP_CTRL (0U<<18) /**< Control. */
-#define DIEPCTL_EPTYP_ISO (1U<<18) /**< Isochronous. */
-#define DIEPCTL_EPTYP_BULK (2U<<18) /**< Bulk. */
-#define DIEPCTL_EPTYP_INTR (3U<<18) /**< Interrupt. */
-#define DIEPCTL_NAKSTS (1U<<17) /**< NAK status. */
-#define DIEPCTL_EONUM (1U<<16) /**< Even/odd frame. */
-#define DIEPCTL_DPID (1U<<16) /**< Endpoint data PID. */
-#define DIEPCTL_USBAEP (1U<<15) /**< USB active endpoint. */
-#define DIEPCTL_MPSIZ_MASK (0x3FFU<<0) /**< Maximum Packet size mask. */
-#define DIEPCTL_MPSIZ(n) ((n)<<0) /**< Maximum Packet size value. */
-/** @} */
-
-/**
- * @name DIEPINT register bit definitions
- * @{
- */
-#define DIEPINT_TXFE (1U<<7) /**< Transmit FIFO empty. */
-#define DIEPINT_INEPNE (1U<<6) /**< IN endpoint NAK effective. */
-#define DIEPINT_ITTXFE (1U<<4) /**< IN Token received when
- TxFIFO is empty. */
-#define DIEPINT_TOC (1U<<3) /**< Timeout condition. */
-#define DIEPINT_EPDISD (1U<<1) /**< Endpoint disabled
- interrupt. */
-#define DIEPINT_XFRC (1U<<0) /**< Transfer completed. */
-/** @} */
-
-/**
- * @name DIEPTSIZ register bit definitions
- * @{
- */
-#define DIEPTSIZ_MCNT_MASK (3U<<29) /**< Multi count mask. */
-#define DIEPTSIZ_MCNT(n) ((n)<<29) /**< Multi count value. */
-#define DIEPTSIZ_PKTCNT_MASK (0x3FF<<19) /**< Packet count mask. */
-#define DIEPTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */
-#define DIEPTSIZ_XFRSIZ_MASK (0x7FFFFU<<0)/**< Transfer size mask. */
-#define DIEPTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */
-/** @} */
-
-/**
- * @name DTXFSTS register bit definitions.
- * @{
- */
-#define DTXFSTS_INEPTFSAV_MASK (0xFFFF<<0) /**< IN endpoint TxFIFO space
- available. */
-/** @} */
-
-/**
- * @name DOEPCTL register bit definitions.
- * @{
- */
-#define DOEPCTL_EPENA (1U<<31) /**< Endpoint enable. */
-#define DOEPCTL_EPDIS (1U<<30) /**< Endpoint disable. */
-#define DOEPCTL_SD1PID (1U<<29) /**< Set DATA1 PID. */
-#define DOEPCTL_SODDFRM (1U<<29) /**< Set odd frame. */
-#define DOEPCTL_SD0PID (1U<<28) /**< Set DATA0 PID. */
-#define DOEPCTL_SEVNFRM (1U<<28) /**< Set even frame. */
-#define DOEPCTL_SNAK (1U<<27) /**< Set NAK. */
-#define DOEPCTL_CNAK (1U<<26) /**< Clear NAK. */
-#define DOEPCTL_STALL (1U<<21) /**< STALL handshake. */
-#define DOEPCTL_SNPM (1U<<20) /**< Snoop mode. */
-#define DOEPCTL_EPTYP_MASK (3U<<18) /**< Endpoint type mask. */
-#define DOEPCTL_EPTYP_CTRL (0U<<18) /**< Control. */
-#define DOEPCTL_EPTYP_ISO (1U<<18) /**< Isochronous. */
-#define DOEPCTL_EPTYP_BULK (2U<<18) /**< Bulk. */
-#define DOEPCTL_EPTYP_INTR (3U<<18) /**< Interrupt. */
-#define DOEPCTL_NAKSTS (1U<<17) /**< NAK status. */
-#define DOEPCTL_EONUM (1U<<16) /**< Even/odd frame. */
-#define DOEPCTL_DPID (1U<<16) /**< Endpoint data PID. */
-#define DOEPCTL_USBAEP (1U<<15) /**< USB active endpoint. */
-#define DOEPCTL_MPSIZ_MASK (0x3FFU<<0) /**< Maximum Packet size mask. */
-#define DOEPCTL_MPSIZ(n) ((n)<<0) /**< Maximum Packet size value. */
-/** @} */
-
-/**
- * @name DOEPINT register bit definitions
- * @{
- */
-#define DOEPINT_B2BSTUP (1U<<6) /**< Back-to-back SETUP packets
- received. */
-#define DOEPINT_OTEPDIS (1U<<4) /**< OUT token received when
- endpoint disabled. */
-#define DOEPINT_STUP (1U<<3) /**< SETUP phase done. */
-#define DOEPINT_EPDISD (1U<<1) /**< Endpoint disabled
- interrupt. */
-#define DOEPINT_XFRC (1U<<0) /**< Transfer completed
- interrupt. */
-/** @} */
-
-/**
- * @name DOEPTSIZ register bit definitions
- * @{
- */
-#define DOEPTSIZ_RXDPID_MASK (3U<<29) /**< Received data PID mask. */
-#define DOEPTSIZ_RXDPID(n) ((n)<<29) /**< Received data PID value. */
-#define DOEPTSIZ_STUPCNT_MASK (3U<<29) /**< SETUP packet count mask. */
-#define DOEPTSIZ_STUPCNT(n) ((n)<<29) /**< SETUP packet count value. */
-#define DOEPTSIZ_PKTCNT_MASK (0x3FFU<<19)/**< Packet count mask. */
-#define DOEPTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */
-#define DOEPTSIZ_XFRSIZ_MASK (0x7FFFFU<<0)/**< Transfer size mask. */
-#define DOEPTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */
-/** @} */
-
-/**
- * @name PCGCCTL register bit definitions
- * @{
- */
-#define PCGCCTL_PHYSUSP (1U<<4) /**< PHY Suspended. */
-#define PCGCCTL_GATEHCLK (1U<<1) /**< Gate HCLK. */
-#define PCGCCTL_STPPCLK (1U<<0) /**< Stop PCLK. */
-/** @} */
-
-/**
- * @brief OTG_FS registers block memory address.
- */
-#define OTG_FS_ADDR 0x50000000
-
-/**
- * @brief OTG_HS registers block memory address.
- */
-#define OTG_HS_ADDR 0x40040000
-
-/**
- * @brief Accesses to the OTG_FS registers block.
- */
-#define OTG_FS ((stm32_otg_t *)OTG_FS_ADDR)
-
-/**
- * @brief Accesses to the OTG_HS registers block.
- */
-#define OTG_HS ((stm32_otg_t *)OTG_HS_ADDR)
-
-#endif /* _STM32_OTG_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/OTGv1/usb_lld.c b/os/hal/platforms/STM32/OTGv1/usb_lld.c deleted file mode 100644 index f6287a49c..000000000 --- a/os/hal/platforms/STM32/OTGv1/usb_lld.c +++ /dev/null @@ -1,1300 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file STM32/OTGv1/usb_lld.c
- * @brief STM32 USB subsystem low level driver source.
- *
- * @addtogroup USB
- * @{
- */
-
-#include <string.h>
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_USB || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-#define TRDT_VALUE 5
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/** @brief OTG_FS driver identifier.*/
-#if STM32_USB_USE_OTG1 || defined(__DOXYGEN__)
-USBDriver USBD1;
-#endif
-
-/** @brief OTG_HS driver identifier.*/
-#if STM32_USB_USE_OTG2 || defined(__DOXYGEN__)
-USBDriver USBD2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief EP0 state.
- * @note It is an union because IN and OUT endpoints are never used at the
- * same time for EP0.
- */
-static union {
- /**
- * @brief IN EP0 state.
- */
- USBInEndpointState in;
- /**
- * @brief OUT EP0 state.
- */
- USBOutEndpointState out;
-} ep0_state;
-
-/**
- * @brief Buffer for the EP0 setup packets.
- */
-static uint8_t ep0setup_buffer[8];
-
-/**
- * @brief EP0 initialization structure.
- */
-static const USBEndpointConfig ep0config = {
- USB_EP_MODE_TYPE_CTRL,
- _usb_ep0setup,
- _usb_ep0in,
- _usb_ep0out,
- 0x40,
- 0x40,
- &ep0_state.in,
- &ep0_state.out,
- 1,
- ep0setup_buffer
-};
-
-#if STM32_USB_USE_OTG1
-static const stm32_otg_params_t fsparams = {
- STM32_USB_OTG1_RX_FIFO_SIZE / 4,
- STM32_OTG1_FIFO_MEM_SIZE,
- STM32_OTG1_ENDOPOINTS_NUMBER
-};
-#endif
-
-#if STM32_USB_USE_OTG2
-static const stm32_otg_params_t hsparams = {
- STM32_USB_OTG2_RX_FIFO_SIZE / 4,
- STM32_OTG2_FIFO_MEM_SIZE,
- STM32_OTG2_ENDOPOINTS_NUMBER
-};
-#endif
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Wakes up the pump thread.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- *
- * @notapi
- */
-static void usb_lld_wakeup_pump(USBDriver *usbp) {
-
- if (usbp->thd_wait != NULL) {
- chThdResumeI(usbp->thd_wait);
- usbp->thd_wait = NULL;
- }
-}
-
-static void otg_core_reset(USBDriver *usbp) {
- stm32_otg_t *otgp = usbp->otg;
-
- /* Core reset and delay of at least 3 PHY cycles.*/
- otgp->GRSTCTL = GRSTCTL_CSRST;
- while ((otgp->GRSTCTL & GRSTCTL_CSRST) != 0)
- ;
- halPolledDelay(12);
- /* Wait AHB idle condition.*/
- while ((otgp->GRSTCTL & GRSTCTL_AHBIDL) == 0)
- ;
-}
-
-static void otg_disable_ep(USBDriver *usbp) {
- stm32_otg_t *otgp = usbp->otg;
- unsigned i;
-
- for (i = 0; i <= usbp->otgparams->num_endpoints; i++) {
- /* Disable only if enabled because this sentence in the manual:
- "The application must set this bit only if Endpoint Enable is
- already set for this endpoint".*/
- if ((otgp->ie[i].DIEPCTL & DIEPCTL_EPENA) != 0) {
- otgp->ie[i].DIEPCTL = DIEPCTL_EPDIS;
- /* Wait for endpoint disable.*/
- while (!(otgp->ie[i].DIEPINT & DIEPINT_EPDISD))
- ;
- }
- else
- otgp->ie[i].DIEPCTL = 0;
- otgp->ie[i].DIEPTSIZ = 0;
- otgp->ie[i].DIEPINT = 0xFFFFFFFF;
- /* Disable only if enabled because this sentence in the manual:
- "The application must set this bit only if Endpoint Enable is
- already set for this endpoint".
- Note that the attempt to disable the OUT EP0 is ignored by the
- hardware but the code is simpler this way.*/
- if ((otgp->oe[i].DOEPCTL & DOEPCTL_EPENA) != 0) {
- otgp->oe[i].DOEPCTL = DOEPCTL_EPDIS;
- /* Wait for endpoint disable.*/
- while (!(otgp->oe[i].DOEPINT & DOEPINT_OTEPDIS))
- ;
- }
- else
- otgp->oe[i].DOEPCTL = 0;
- otgp->oe[i].DOEPTSIZ = 0;
- otgp->oe[i].DOEPINT = 0xFFFFFFFF;
- }
- otgp->DAINTMSK = DAINTMSK_OEPM(0) | DAINTMSK_IEPM(0);
-}
-
-static void otg_rxfifo_flush(USBDriver *usbp) {
- stm32_otg_t *otgp = usbp->otg;
-
- otgp->GRSTCTL = GRSTCTL_RXFFLSH;
- while ((otgp->GRSTCTL & GRSTCTL_RXFFLSH) != 0)
- ;
- /* Wait for 3 PHY Clocks.*/
- halPolledDelay(12);
-}
-
-static void otg_txfifo_flush(USBDriver *usbp, uint32_t fifo) {
- stm32_otg_t *otgp = usbp->otg;
-
- otgp->GRSTCTL = GRSTCTL_TXFNUM(fifo) | GRSTCTL_TXFFLSH;
- while ((otgp->GRSTCTL & GRSTCTL_TXFFLSH) != 0)
- ;
- /* Wait for 3 PHY Clocks.*/
- halPolledDelay(12);
-}
-
-/**
- * @brief Resets the FIFO RAM memory allocator.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- *
- * @notapi
- */
-static void otg_ram_reset(USBDriver *usbp) {
-
- usbp->pmnext = usbp->otgparams->rx_fifo_size;
-}
-
-/**
- * @brief Allocates a block from the FIFO RAM memory.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] size size of the packet buffer to allocate in words
- *
- * @notapi
- */
-static uint32_t otg_ram_alloc(USBDriver *usbp, size_t size) {
- uint32_t next;
-
- next = usbp->pmnext;
- usbp->pmnext += size;
- chDbgAssert(usbp->pmnext <= usbp->otgparams->otg_ram_size,
- "otg_fifo_alloc(), #1", "OTG FIFO memory overflow");
- return next;
-}
-
-/**
- * @brief Pushes a series of words into a FIFO.
- *
- * @param[in] fifop pointer to the FIFO register
- * @param[in] buf pointer to the words buffer, not necessarily word
- * aligned
- * @param[in] n number of words to push
- *
- * @return A pointer after the last word pushed.
- *
- * @notapi
- */
-static uint8_t *otg_do_push(volatile uint32_t *fifop, uint8_t *buf, size_t n) {
-
- while (n > 0) {
- /* Note, this line relies on the Cortex-M3/M4 ability to perform
- unaligned word accesses and on the LSB-first memory organization.*/
- *fifop = *((uint32_t *)buf);
- buf += 4;
- n--;
- }
- return buf;
-}
-
-/**
- * @brief Writes to a TX FIFO.
- *
- * @param[in] fifop pointer to the FIFO register
- * @param[in] buf buffer where to copy the endpoint data
- * @param[in] n maximum number of bytes to copy
- *
- * @notapi
- */
-static void otg_fifo_write_from_buffer(volatile uint32_t *fifop,
- const uint8_t *buf,
- size_t n) {
-
- otg_do_push(fifop, (uint8_t *)buf, (n + 3) / 4);
-}
-
-/**
- * @brief Writes to a TX FIFO fetching data from a queue.
- *
- * @param[in] fifop pointer to the FIFO register
- * @param[in] oqp pointer to an @p OutputQueue object
- * @param[in] n maximum number of bytes to copy
- *
- * @notapi
- */
-static void otg_fifo_write_from_queue(volatile uint32_t *fifop,
- OutputQueue *oqp,
- size_t n) {
- size_t ntogo;
-
- ntogo = n;
- while (ntogo > 0) {
- uint32_t w, i;
- size_t nw = ntogo / 4;
-
- if (nw > 0) {
- size_t streak;
- uint32_t nw2end = (oqp->q_top - oqp->q_rdptr) / 4;
-
- ntogo -= (streak = nw <= nw2end ? nw : nw2end) * 4;
- oqp->q_rdptr = otg_do_push(fifop, oqp->q_rdptr, streak);
- if (oqp->q_rdptr >= oqp->q_top) {
- oqp->q_rdptr = oqp->q_buffer;
- continue;
- }
- }
-
- /* If this condition is not satisfied then there is a word lying across
- queue circular buffer boundary or there are some remaining bytes.*/
- if (ntogo <= 0)
- break;
-
- /* One byte at time.*/
- w = 0;
- i = 0;
- while ((ntogo > 0) && (i < 4)) {
- w |= (uint32_t)*oqp->q_rdptr++ << (i * 8);
- if (oqp->q_rdptr >= oqp->q_top)
- oqp->q_rdptr = oqp->q_buffer;
- ntogo--;
- i++;
- }
- *fifop = w;
- }
-
- /* Updating queue.*/
- chSysLock();
- oqp->q_counter += n;
- while (notempty(&oqp->q_waiting))
- chSchReadyI(fifo_remove(&oqp->q_waiting))->p_u.rdymsg = Q_OK;
- chSchRescheduleS();
- chSysUnlock();
-}
-
-/**
- * @brief Pops a series of words from a FIFO.
- *
- * @param[in] fifop pointer to the FIFO register
- * @param[in] buf pointer to the words buffer, not necessarily word
- * aligned
- * @param[in] n number of words to push
- *
- * @return A pointer after the last word pushed.
- *
- * @notapi
- */
-static uint8_t *otg_do_pop(volatile uint32_t *fifop, uint8_t *buf, size_t n) {
-
- while (n > 0) {
- uint32_t w = *fifop;
- /* Note, this line relies on the Cortex-M3/M4 ability to perform
- unaligned word accesses and on the LSB-first memory organization.*/
- *((uint32_t *)buf) = w;
- buf += 4;
- n--;
- }
- return buf;
-}
-
-/**
- * @brief Reads a packet from the RXFIFO.
- *
- * @param[in] fifop pointer to the FIFO register
- * @param[out] buf buffer where to copy the endpoint data
- * @param[in] n number of bytes to pull from the FIFO
- * @param[in] max number of bytes to copy into the buffer
- *
- * @notapi
- */
-static void otg_fifo_read_to_buffer(volatile uint32_t *fifop,
- uint8_t *buf,
- size_t n,
- size_t max) {
-
- n = (n + 3) / 4;
- max = (max + 3) / 4;
- while (n) {
- uint32_t w = *fifop;
- if (max) {
- /* Note, this line relies on the Cortex-M3/M4 ability to perform
- unaligned word accesses and on the LSB-first memory organization.*/
- *((uint32_t *)buf) = w;
- buf += 4;
- max--;
- }
- n--;
- }
-}
-
-/**
- * @brief Reads a packet from the RXFIFO.
- *
- * @param[in] fifop pointer to the FIFO register
- * @param[in] iqp pointer to an @p InputQueue object
- * @param[in] n number of bytes to pull from the FIFO
- *
- * @notapi
- */
-static void otg_fifo_read_to_queue(volatile uint32_t *fifop,
- InputQueue *iqp,
- size_t n) {
- size_t ntogo;
-
- ntogo = n;
- while (ntogo > 0) {
- uint32_t w, i;
- size_t nw = ntogo / 4;
-
- if (nw > 0) {
- size_t streak;
- uint32_t nw2end = (iqp->q_wrptr - iqp->q_wrptr) / 4;
-
- ntogo -= (streak = nw <= nw2end ? nw : nw2end) * 4;
- iqp->q_wrptr = otg_do_pop(fifop, iqp->q_wrptr, streak);
- if (iqp->q_wrptr >= iqp->q_top) {
- iqp->q_wrptr = iqp->q_buffer;
- continue;
- }
- }
-
- /* If this condition is not satisfied then there is a word lying across
- queue circular buffer boundary or there are some remaining bytes.*/
- if (ntogo <= 0)
- break;
-
- /* One byte at time.*/
- w = *fifop;
- i = 0;
- while ((ntogo > 0) && (i < 4)) {
- *iqp->q_wrptr++ = (uint8_t)(w >> (i * 8));
- if (iqp->q_wrptr >= iqp->q_top)
- iqp->q_wrptr = iqp->q_buffer;
- ntogo--;
- i++;
- }
- }
-
- /* Updating queue.*/
- chSysLock();
- iqp->q_counter += n;
- while (notempty(&iqp->q_waiting))
- chSchReadyI(fifo_remove(&iqp->q_waiting))->p_u.rdymsg = Q_OK;
- chSchRescheduleS();
- chSysUnlock();
-}
-
-/**
- * @brief Incoming packets handler.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- *
- * @notapi
- */
-static void otg_rxfifo_handler(USBDriver *usbp) {
- uint32_t sts, cnt, ep;
-
- sts = usbp->otg->GRXSTSP;
- switch (sts & GRXSTSP_PKTSTS_MASK) {
- case GRXSTSP_SETUP_COMP:
- break;
- case GRXSTSP_SETUP_DATA:
- cnt = (sts & GRXSTSP_BCNT_MASK) >> GRXSTSP_BCNT_OFF;
- ep = (sts & GRXSTSP_EPNUM_MASK) >> GRXSTSP_EPNUM_OFF;
- otg_fifo_read_to_buffer(usbp->otg->FIFO[0], usbp->epc[ep]->setup_buf,
- cnt, 8);
- break;
- case GRXSTSP_OUT_DATA:
- cnt = (sts & GRXSTSP_BCNT_MASK) >> GRXSTSP_BCNT_OFF;
- ep = (sts & GRXSTSP_EPNUM_MASK) >> GRXSTSP_EPNUM_OFF;
- if (usbp->epc[ep]->out_state->rxqueued) {
- /* Queue associated.*/
- otg_fifo_read_to_queue(usbp->otg->FIFO[0],
- usbp->epc[ep]->out_state->mode.queue.rxqueue,
- cnt);
- }
- else {
- otg_fifo_read_to_buffer(usbp->otg->FIFO[0],
- usbp->epc[ep]->out_state->mode.linear.rxbuf,
- cnt,
- usbp->epc[ep]->out_state->rxsize -
- usbp->epc[ep]->out_state->rxcnt);
- usbp->epc[ep]->out_state->mode.linear.rxbuf += cnt;
- }
- usbp->epc[ep]->out_state->rxcnt += cnt;
- break;
- case GRXSTSP_OUT_GLOBAL_NAK:
- case GRXSTSP_OUT_COMP:
- default:
- ;
- }
-}
-
-/**
- * @brief Outgoing packets handler.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @notapi
- */
-static bool_t otg_txfifo_handler(USBDriver *usbp, usbep_t ep) {
-
- /* The TXFIFO is filled until there is space and data to be transmitted.*/
- while (TRUE) {
- uint32_t n;
-
- /* Transaction end condition.*/
- if (usbp->epc[ep]->in_state->txcnt >= usbp->epc[ep]->in_state->txsize)
- return TRUE;
-
- /* Number of bytes remaining in current transaction.*/
- n = usbp->epc[ep]->in_state->txsize - usbp->epc[ep]->in_state->txcnt;
- if (n > usbp->epc[ep]->in_maxsize)
- n = usbp->epc[ep]->in_maxsize;
-
- /* Checks if in the TXFIFO there is enough space to accommodate the
- next packet.*/
- if (((usbp->otg->ie[ep].DTXFSTS & DTXFSTS_INEPTFSAV_MASK) * 4) < n)
- return FALSE;
-
-#if STM32_USB_OTGFIFO_FILL_BASEPRI
- __set_BASEPRI(CORTEX_PRIORITY_MASK(STM32_USB_OTGFIFO_FILL_BASEPRI));
-#endif
- /* Handles the two cases: linear buffer or queue.*/
- if (usbp->epc[ep]->in_state->txqueued) {
- /* Queue associated.*/
- otg_fifo_write_from_queue(usbp->otg->FIFO[ep],
- usbp->epc[ep]->in_state->mode.queue.txqueue,
- n);
- }
- else {
- /* Linear buffer associated.*/
- otg_fifo_write_from_buffer(usbp->otg->FIFO[ep],
- usbp->epc[ep]->in_state->mode.linear.txbuf,
- n);
- usbp->epc[ep]->in_state->mode.linear.txbuf += n;
- }
- usbp->epc[ep]->in_state->txcnt += n;
- }
-#if STM32_USB_OTGFIFO_FILL_BASEPRI
- __set_BASEPRI(0);
-#endif
-}
-
-/**
- * @brief Generic endpoint IN handler.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @notapi
- */
-static void otg_epin_handler(USBDriver *usbp, usbep_t ep) {
- stm32_otg_t *otgp = usbp->otg;
- uint32_t epint = otgp->ie[ep].DIEPINT;
-
- otgp->ie[ep].DIEPINT = 0xFFFFFFFF;
-
- if (epint & DIEPINT_TOC) {
- /* Timeouts not handled yet, not sure how to handle.*/
- }
- if ((epint & DIEPINT_XFRC) && (otgp->DIEPMSK & DIEPMSK_XFRCM)) {
- /* Transmit transfer complete.*/
- _usb_isr_invoke_in_cb(usbp, ep);
- }
- if ((epint & DIEPINT_TXFE) &&
- (otgp->DIEPEMPMSK & DIEPEMPMSK_INEPTXFEM(ep))) {
- /* The thread is made ready, it will be scheduled on ISR exit.*/
- chSysLockFromIsr();
- usbp->txpending |= (1 << ep);
- otgp->DIEPEMPMSK &= ~(1 << ep);
- usb_lld_wakeup_pump(usbp);
- chSysUnlockFromIsr();
- }
-}
-
-/**
- * @brief Generic endpoint OUT handler.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @notapi
- */
-static void otg_epout_handler(USBDriver *usbp, usbep_t ep) {
- stm32_otg_t *otgp = usbp->otg;
- uint32_t epint = otgp->oe[ep].DOEPINT;
-
- /* Resets all EP IRQ sources.*/
- otgp->oe[ep].DOEPINT = 0xFFFFFFFF;
-
- if ((epint & DOEPINT_STUP) && (otgp->DOEPMSK & DOEPMSK_STUPM)) {
- /* Setup packets handling, setup packets are handled using a
- specific callback.*/
- _usb_isr_invoke_setup_cb(usbp, ep);
-
- }
- if ((epint & DOEPINT_XFRC) && (otgp->DOEPMSK & DOEPMSK_XFRCM)) {
- /* Receive transfer complete.*/
- _usb_isr_invoke_out_cb(usbp, ep);
- }
-}
-
-/**
- * @brief OTG shared ISR.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- *
- * @notapi
- */
-static void usb_lld_serve_interrupt(USBDriver *usbp) {
- stm32_otg_t *otgp = usbp->otg;
- uint32_t sts, src;
-
- sts = otgp->GINTSTS & otgp->GINTMSK;
- otgp->GINTSTS = sts;
-
- /* Reset interrupt handling.*/
- if (sts & GINTSTS_USBRST) {
- _usb_reset(usbp);
- _usb_isr_invoke_event_cb(usbp, USB_EVENT_RESET);
- }
-
- /* Enumeration done.*/
- if (sts & GINTSTS_ENUMDNE) {
- (void)otgp->DSTS;
- }
-
- /* SOF interrupt handling.*/
- if (sts & GINTSTS_SOF) {
- _usb_isr_invoke_sof_cb(usbp);
- }
-
- /* RX FIFO not empty handling.*/
- if (sts & GINTSTS_RXFLVL) {
- /* The interrupt is masked while the thread has control or it would
- be triggered again.*/
- chSysLockFromIsr();
- otgp->GINTMSK &= ~GINTMSK_RXFLVLM;
- usb_lld_wakeup_pump(usbp);
- chSysUnlockFromIsr();
- }
-
- /* IN/OUT endpoints event handling.*/
- src = otgp->DAINT;
- if (sts & GINTSTS_IEPINT) {
- if (src & (1 << 0))
- otg_epin_handler(usbp, 0);
- if (src & (1 << 1))
- otg_epin_handler(usbp, 1);
- if (src & (1 << 2))
- otg_epin_handler(usbp, 2);
- if (src & (1 << 3))
- otg_epin_handler(usbp, 3);
-#if STM32_USB_USE_OTG2
- if (src & (1 << 4))
- otg_epin_handler(usbp, 4);
- if (src & (1 << 5))
- otg_epin_handler(usbp, 5);
-#endif
- }
- if (sts & GINTSTS_OEPINT) {
- if (src & (1 << 16))
- otg_epout_handler(usbp, 0);
- if (src & (1 << 17))
- otg_epout_handler(usbp, 1);
- if (src & (1 << 18))
- otg_epout_handler(usbp, 2);
- if (src & (1 << 19))
- otg_epout_handler(usbp, 3);
-#if STM32_USB_USE_OTG2
- if (src & (1 << 20))
- otg_epout_handler(usbp, 4);
- if (src & (1 << 21))
- otg_epout_handler(usbp, 5);
-#endif
- }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers and threads. */
-/*===========================================================================*/
-
-static msg_t usb_lld_pump(void *p) {
- USBDriver *usbp = (USBDriver *)p;
- stm32_otg_t *otgp = usbp->otg;
-
- chRegSetThreadName("usb_lld_pump");
- chSysLock();
- while (TRUE) {
- usbep_t ep;
- uint32_t epmask;
-
- /* Nothing to do, going to sleep.*/
- if ((usbp->state == USB_STOP) ||
- ((usbp->txpending == 0) && !(otgp->GINTSTS & GINTSTS_RXFLVL))) {
- otgp->GINTMSK |= GINTMSK_RXFLVLM;
- usbp->thd_wait = chThdSelf();
- chSchGoSleepS(THD_STATE_SUSPENDED);
- }
- chSysUnlock();
-
- /* Checks if there are TXFIFOs to be filled.*/
- for (ep = 0; ep <= usbp->otgparams->num_endpoints; ep++) {
-
- /* Empties the RX FIFO.*/
- while (otgp->GINTSTS & GINTSTS_RXFLVL) {
- otg_rxfifo_handler(usbp);
- }
-
- epmask = (1 << ep);
- if (usbp->txpending & epmask) {
- bool_t done;
-
- chSysLock();
- /* USB interrupts are globally *suspended* because the peripheral
- does not allow any interference during the TX FIFO filling
- operation.
- Synopsys document: DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG)
- "The application has to finish writing one complete packet before
- switching to a different channel/endpoint FIFO. Violating this
- rule results in an error.".*/
- otgp->GAHBCFG &= ~GAHBCFG_GINTMSK;
- usbp->txpending &= ~epmask;
- chSysUnlock();
-
- done = otg_txfifo_handler(usbp, ep);
-
- chSysLock();
- otgp->GAHBCFG |= GAHBCFG_GINTMSK;
- if (!done)
- otgp->DIEPEMPMSK |= epmask;
- chSysUnlock();
- }
- }
- chSysLock();
- }
- chSysUnlock();
- return 0;
-}
-
-#if STM32_USB_USE_OTG1 || defined(__DOXYGEN__)
-#if !defined(STM32_OTG1_HANDLER)
-#error "STM32_OTG1_HANDLER not defined"
-#endif
-/**
- * @brief OTG1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_OTG1_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- usb_lld_serve_interrupt(&USBD1);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if STM32_USB_USE_OTG2 || defined(__DOXYGEN__)
-#if !defined(STM32_OTG2_HANDLER)
-#error "STM32_OTG2_HANDLER not defined"
-#endif
-/**
- * @brief OTG2 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_OTG2_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- usb_lld_serve_interrupt(&USBD2);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level USB driver initialization.
- *
- * @notapi
- */
-void usb_lld_init(void) {
-
- /* Driver initialization.*/
-#if STM32_USB_USE_OTG1
- usbObjectInit(&USBD1);
- USBD1.thd_ptr = NULL;
- USBD1.thd_wait = NULL;
- USBD1.otg = OTG_FS;
- USBD1.otgparams = &fsparams;
-
- /* Filling the thread working area here because the function
- @p chThdCreateI() does not do it.*/
-#if CH_DBG_FILL_THREADS
- {
- void *wsp = USBD1.wa_pump;
- _thread_memfill((uint8_t *)wsp,
- (uint8_t *)wsp + sizeof(Thread),
- CH_THREAD_FILL_VALUE);
- _thread_memfill((uint8_t *)wsp + sizeof(Thread),
- (uint8_t *)wsp + sizeof(USBD1.wa_pump) - sizeof(Thread),
- CH_STACK_FILL_VALUE);
- }
-#endif
-#endif
-
-#if STM32_USB_USE_OTG2
- usbObjectInit(&USBD2);
- USBD2.thd_ptr = NULL;
- USBD2.thd_wait = NULL;
- USBD2.otg = OTG_HS;
- USBD2.otgparams = &hsparams;
-
- /* Filling the thread working area here because the function
- @p chThdCreateI() does not do it.*/
-#if CH_DBG_FILL_THREADS
- {
- void *wsp = USBD2.wa_pump;
- _thread_memfill((uint8_t *)wsp,
- (uint8_t *)wsp + sizeof(Thread),
- CH_THREAD_FILL_VALUE);
- _thread_memfill((uint8_t *)wsp + sizeof(Thread),
- (uint8_t *)wsp + sizeof(USBD2.wa_pump) - sizeof(Thread),
- CH_STACK_FILL_VALUE);
- }
-#endif
-#endif
-}
-
-/**
- * @brief Configures and activates the USB peripheral.
- * @note Starting the OTG cell can be a slow operation carried out with
- * interrupts disabled, perform it before starting time-critical
- * operations.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_start(USBDriver *usbp) {
- stm32_otg_t *otgp = usbp->otg;
-
- if (usbp->state == USB_STOP) {
- /* Clock activation.*/
-#if STM32_USB_USE_OTG1
- if (&USBD1 == usbp) {
- /* OTG FS clock enable and reset.*/
- rccEnableOTG_FS(FALSE);
- rccResetOTG_FS();
-
- /* Enables IRQ vector.*/
- nvicEnableVector(STM32_OTG1_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_USB_OTG1_IRQ_PRIORITY));
- }
-#endif
-#if STM32_USB_USE_OTG2
- if (&USBD2 == usbp) {
- /* OTG HS clock enable and reset.*/
- rccEnableOTG_HS(FALSE);
- rccResetOTG_HS();
-
- /* Enables IRQ vector.*/
- nvicEnableVector(STM32_OTG2_NUMBER,
- CORTEX_PRIORITY_MASK(STM32_USB_OTG2_IRQ_PRIORITY));
- }
-#endif
-
- /* Creates the data pump threads in a suspended state. Note, it is
- created only once, the first time @p usbStart() is invoked.*/
- usbp->txpending = 0;
- if (usbp->thd_ptr == NULL)
- usbp->thd_ptr = usbp->thd_wait = chThdCreateI(usbp->wa_pump,
- sizeof usbp->wa_pump,
- STM32_USB_OTG_THREAD_PRIO,
- usb_lld_pump,
- usbp);
-
- /* - Forced device mode.
- - USB turn-around time = TRDT_VALUE.
- - Full Speed 1.1 PHY.*/
- otgp->GUSBCFG = GUSBCFG_FDMOD | GUSBCFG_TRDT(TRDT_VALUE) | GUSBCFG_PHYSEL;
-
- /* 48MHz 1.1 PHY.*/
- otgp->DCFG = 0x02200000 | DCFG_DSPD_FS11;
-
- /* PHY enabled.*/
- otgp->PCGCCTL = 0;
-
- /* Internal FS PHY activation.*/
- otgp->GCCFG = GCCFG_VBUSASEN | GCCFG_VBUSBSEN | GCCFG_PWRDWN;
-
- /* Soft core reset.*/
- otg_core_reset(usbp);
-
- /* Interrupts on TXFIFOs half empty.*/
- otgp->GAHBCFG = 0;
-
- /* Endpoints re-initialization.*/
- otg_disable_ep(usbp);
-
- /* Clear all pending Device Interrupts, only the USB Reset interrupt
- is required initially.*/
- otgp->DIEPMSK = 0;
- otgp->DOEPMSK = 0;
- otgp->DAINTMSK = 0;
- if (usbp->config->sof_cb == NULL)
- otgp->GINTMSK = GINTMSK_ENUMDNEM | GINTMSK_USBRSTM /*| GINTMSK_USBSUSPM |
- GINTMSK_ESUSPM |*/;
- else
- otgp->GINTMSK = GINTMSK_ENUMDNEM | GINTMSK_USBRSTM /*| GINTMSK_USBSUSPM |
- GINTMSK_ESUSPM */ | GINTMSK_SOFM;
- otgp->GINTSTS = 0xFFFFFFFF; /* Clears all pending IRQs, if any. */
-
- /* Global interrupts enable.*/
- otgp->GAHBCFG |= GAHBCFG_GINTMSK;
- }
-}
-
-/**
- * @brief Deactivates the USB peripheral.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_stop(USBDriver *usbp) {
- stm32_otg_t *otgp = usbp->otg;
-
- /* If in ready state then disables the USB clock.*/
- if (usbp->state != USB_STOP) {
-
- /* Disabling all endpoints in case the driver has been stopped while
- active.*/
- otg_disable_ep(usbp);
-
- usbp->txpending = 0;
-
- otgp->DAINTMSK = 0;
- otgp->GAHBCFG = 0;
- otgp->GCCFG = 0;
-
-#if STM32_USB_USE_USB1
- if (&USBD1 == usbp) {
- nvicDisableVector(STM32_OTG1_NUMBER);
- rccDisableOTG1(FALSE);
- }
-#endif
-
-#if STM32_USB_USE_USB2
- if (&USBD2 == usbp) {
- nvicDisableVector(STM32_OTG2_NUMBER);
- rccDisableOTG2(FALSE);
- }
-#endif
- }
-}
-
-/**
- * @brief USB low level reset routine.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_reset(USBDriver *usbp) {
- unsigned i;
- stm32_otg_t *otgp = usbp->otg;
-
- /* Flush the Tx FIFO.*/
- otg_txfifo_flush(usbp, 0);
-
- /* All endpoints in NAK mode, interrupts cleared.*/
- for (i = 0; i <= usbp->otgparams->num_endpoints; i++) {
- otgp->ie[i].DIEPCTL = DIEPCTL_SNAK;
- otgp->oe[i].DOEPCTL = DOEPCTL_SNAK;
- otgp->ie[i].DIEPINT = 0xFF;
- otgp->oe[i].DOEPINT = 0xFF;
- }
-
- /* Endpoint interrupts all disabled and cleared.*/
- otgp->DAINT = 0xFFFFFFFF;
- otgp->DAINTMSK = DAINTMSK_OEPM(0) | DAINTMSK_IEPM(0);
-
- /* Resets the FIFO memory allocator.*/
- otg_ram_reset(usbp);
-
- /* Receive FIFO size initialization, the address is always zero.*/
- otgp->GRXFSIZ = usbp->otgparams->rx_fifo_size;
- otg_rxfifo_flush(usbp);
-
- /* Resets the device address to zero.*/
- otgp->DCFG = (otgp->DCFG & ~DCFG_DAD_MASK) | DCFG_DAD(0);
-
- /* Enables also EP-related interrupt sources.*/
- otgp->GINTMSK |= GINTMSK_RXFLVLM | GINTMSK_OEPM | GINTMSK_IEPM;
- otgp->DIEPMSK = DIEPMSK_TOCM | DIEPMSK_XFRCM;
- otgp->DOEPMSK = DOEPMSK_STUPM | DOEPMSK_XFRCM;
-
- /* EP0 initialization, it is a special case.*/
- usbp->epc[0] = &ep0config;
- otgp->oe[0].DOEPTSIZ = 0;
- otgp->oe[0].DOEPCTL = DOEPCTL_SD0PID | DOEPCTL_USBAEP | DOEPCTL_EPTYP_CTRL |
- DOEPCTL_MPSIZ(ep0config.out_maxsize);
- otgp->ie[0].DIEPTSIZ = 0;
- otgp->ie[0].DIEPCTL = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_CTRL |
- DIEPCTL_TXFNUM(0) | DIEPCTL_MPSIZ(ep0config.in_maxsize);
- otgp->DIEPTXF0 = DIEPTXF_INEPTXFD(ep0config.in_maxsize / 4) |
- DIEPTXF_INEPTXSA(otg_ram_alloc(usbp,
- ep0config.in_maxsize / 4));
-}
-
-/**
- * @brief Sets the USB address.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_set_address(USBDriver *usbp) {
- stm32_otg_t *otgp = usbp->otg;
-
- otgp->DCFG = (otgp->DCFG & ~DCFG_DAD_MASK) | DCFG_DAD(usbp->address);
-}
-
-/**
- * @brief Enables an endpoint.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @notapi
- */
-void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) {
- uint32_t ctl, fsize;
- stm32_otg_t *otgp = usbp->otg;
-
- /* IN and OUT common parameters.*/
- switch (usbp->epc[ep]->ep_mode & USB_EP_MODE_TYPE) {
- case USB_EP_MODE_TYPE_CTRL:
- ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_CTRL;
- break;
- case USB_EP_MODE_TYPE_ISOC:
- ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_ISO;
- break;
- case USB_EP_MODE_TYPE_BULK:
- ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_BULK;
- break;
- case USB_EP_MODE_TYPE_INTR:
- ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_INTR;
- break;
- default:
- return;
- }
-
- /* OUT endpoint activation or deactivation.*/
- otgp->oe[ep].DOEPTSIZ = 0;
- if (usbp->epc[ep]->out_cb != NULL) {
- otgp->oe[ep].DOEPCTL = ctl | DOEPCTL_MPSIZ(usbp->epc[ep]->out_maxsize);
- otgp->DAINTMSK |= DAINTMSK_OEPM(ep);
- }
- else {
- otgp->oe[ep].DOEPCTL &= ~DOEPCTL_USBAEP;
- otgp->DAINTMSK &= ~DAINTMSK_OEPM(ep);
- }
-
- /* IN endpoint activation or deactivation.*/
- otgp->ie[ep].DIEPTSIZ = 0;
- if (usbp->epc[ep]->in_cb != NULL) {
- /* FIFO allocation for the IN endpoint.*/
- fsize = usbp->epc[ep]->in_maxsize / 4;
- if (usbp->epc[ep]->in_multiplier > 1)
- fsize *= usbp->epc[ep]->in_multiplier;
- otgp->DIEPTXF[ep - 1] = DIEPTXF_INEPTXFD(fsize) |
- DIEPTXF_INEPTXSA(otg_ram_alloc(usbp, fsize));
- otg_txfifo_flush(usbp, ep);
-
- otgp->ie[ep].DIEPCTL = ctl |
- DIEPCTL_TXFNUM(ep) |
- DIEPCTL_MPSIZ(usbp->epc[ep]->in_maxsize);
- otgp->DAINTMSK |= DAINTMSK_IEPM(ep);
- }
- else {
- otgp->DIEPTXF[ep - 1] = 0x02000400; /* Reset value.*/
- otg_txfifo_flush(usbp, ep);
- otgp->ie[ep].DIEPCTL &= ~DIEPCTL_USBAEP;
- otgp->DAINTMSK &= ~DAINTMSK_IEPM(ep);
- }
-}
-
-/**
- * @brief Disables all the active endpoints except the endpoint zero.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_disable_endpoints(USBDriver *usbp) {
-
- /* Resets the FIFO memory allocator.*/
- otg_ram_reset(usbp);
-
- /* Disabling all endpoints.*/
- otg_disable_ep(usbp);
-}
-
-/**
- * @brief Returns the status of an OUT endpoint.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- * @return The endpoint status.
- * @retval EP_STATUS_DISABLED The endpoint is not active.
- * @retval EP_STATUS_STALLED The endpoint is stalled.
- * @retval EP_STATUS_ACTIVE The endpoint is active.
- *
- * @notapi
- */
-usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) {
- uint32_t ctl;
-
- (void)usbp;
-
- ctl = usbp->otg->oe[ep].DOEPCTL;
- if (!(ctl & DOEPCTL_USBAEP))
- return EP_STATUS_DISABLED;
- if (ctl & DOEPCTL_STALL)
- return EP_STATUS_STALLED;
- return EP_STATUS_ACTIVE;
-}
-
-/**
- * @brief Returns the status of an IN endpoint.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- * @return The endpoint status.
- * @retval EP_STATUS_DISABLED The endpoint is not active.
- * @retval EP_STATUS_STALLED The endpoint is stalled.
- * @retval EP_STATUS_ACTIVE The endpoint is active.
- *
- * @notapi
- */
-usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) {
- uint32_t ctl;
-
- (void)usbp;
-
- ctl = usbp->otg->ie[ep].DIEPCTL;
- if (!(ctl & DIEPCTL_USBAEP))
- return EP_STATUS_DISABLED;
- if (ctl & DIEPCTL_STALL)
- return EP_STATUS_STALLED;
- return EP_STATUS_ACTIVE;
-}
-
-/**
- * @brief Reads a setup packet from the dedicated packet buffer.
- * @details This function must be invoked in the context of the @p setup_cb
- * callback in order to read the received setup packet.
- * @pre In order to use this function the endpoint must have been
- * initialized as a control endpoint.
- * @post The endpoint is ready to accept another packet.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- * @param[out] buf buffer where to copy the packet data
- *
- * @notapi
- */
-void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) {
-
- memcpy(buf, usbp->epc[ep]->setup_buf, 8);
-}
-
-/**
- * @brief Prepares for a receive operation.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @notapi
- */
-void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep) {
- uint32_t pcnt;
- USBOutEndpointState *osp = usbp->epc[ep]->out_state;
-
- /* Transfer initialization.*/
- pcnt = (osp->rxsize + usbp->epc[ep]->out_maxsize - 1) /
- usbp->epc[ep]->out_maxsize;
- usbp->otg->oe[ep].DOEPTSIZ = DOEPTSIZ_STUPCNT(3) | DOEPTSIZ_PKTCNT(pcnt) |
- DOEPTSIZ_XFRSIZ(usbp->epc[ep]->out_maxsize);
-
-}
-
-/**
- * @brief Prepares for a transmit operation.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @notapi
- */
-void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep) {
- USBInEndpointState *isp = usbp->epc[ep]->in_state;
-
- /* Transfer initialization.*/
- if (isp->txsize == 0) {
- /* Special case, sending zero size packet.*/
- usbp->otg->ie[ep].DIEPTSIZ = DIEPTSIZ_PKTCNT(1) | DIEPTSIZ_XFRSIZ(0);
- }
- else {
- /* Normal case.*/
- uint32_t pcnt = (isp->txsize + usbp->epc[ep]->in_maxsize - 1) /
- usbp->epc[ep]->in_maxsize;
- usbp->otg->ie[ep].DIEPTSIZ = DIEPTSIZ_PKTCNT(pcnt) |
- DIEPTSIZ_XFRSIZ(usbp->epc[ep]->in_state->txsize);
- }
-
-}
-
-/**
- * @brief Starts a receive operation on an OUT endpoint.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @notapi
- */
-void usb_lld_start_out(USBDriver *usbp, usbep_t ep) {
-
- usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_CNAK;
-}
-
-/**
- * @brief Starts a transmit operation on an IN endpoint.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @notapi
- */
-void usb_lld_start_in(USBDriver *usbp, usbep_t ep) {
-
- usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_EPENA | DIEPCTL_CNAK;
- usbp->otg->DIEPEMPMSK |= DIEPEMPMSK_INEPTXFEM(ep);
-}
-
-/**
- * @brief Brings an OUT endpoint in the stalled state.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @notapi
- */
-void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) {
-
- usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_STALL;
-}
-
-/**
- * @brief Brings an IN endpoint in the stalled state.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @notapi
- */
-void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) {
-
- usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_STALL;
-}
-
-/**
- * @brief Brings an OUT endpoint in the active state.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @notapi
- */
-void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) {
-
- usbp->otg->oe[ep].DOEPCTL &= ~DOEPCTL_STALL;
-}
-
-/**
- * @brief Brings an IN endpoint in the active state.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @notapi
- */
-void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) {
-
- usbp->otg->ie[ep].DIEPCTL &= ~DIEPCTL_STALL;
-}
-
-#endif /* HAL_USE_USB */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/OTGv1/usb_lld.h b/os/hal/platforms/STM32/OTGv1/usb_lld.h deleted file mode 100644 index 570309750..000000000 --- a/os/hal/platforms/STM32/OTGv1/usb_lld.h +++ /dev/null @@ -1,534 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file STM32/OTGv1/usb_lld.h
- * @brief STM32 USB subsystem low level driver header.
- *
- * @addtogroup USB
- * @{
- */
-
-#ifndef _USB_LLD_H_
-#define _USB_LLD_H_
-
-#if HAL_USE_USB || defined(__DOXYGEN__)
-
-#include "stm32_otg.h"
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief Maximum endpoint address.
- */
-#if !STM32_USB_USE_OTG2 || defined(__DOXYGEN__)
-#define USB_MAX_ENDPOINTS 3
-#else
-#define USB_MAX_ENDPOINTS 5
-#endif
-
-/**
- * @brief The address can be changed immediately upon packet reception.
- */
-#define USB_SET_ADDRESS_MODE USB_EARLY_SET_ADDRESS
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @brief OTG1 driver enable switch.
- * @details If set to @p TRUE the support for OTG_FS is included.
- * @note The default is @p TRUE.
- */
-#if !defined(STM32_USB_USE_OTG1) || defined(__DOXYGEN__)
-#define STM32_USB_USE_OTG1 FALSE
-#endif
-
-/**
- * @brief OTG2 driver enable switch.
- * @details If set to @p TRUE the support for OTG_HS is included.
- * @note The default is @p TRUE.
- */
-#if !defined(STM32_USB_USE_OTG2) || defined(__DOXYGEN__)
-#define STM32_USB_USE_OTG2 FALSE
-#endif
-
-/**
- * @brief OTG1 interrupt priority level setting.
- */
-#if !defined(STM32_USB_OTG1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_USB_OTG1_IRQ_PRIORITY 14
-#endif
-
-/**
- * @brief OTG2 interrupt priority level setting.
- */
-#if !defined(STM32_USB_OTG2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_USB_OTG2_IRQ_PRIORITY 14
-#endif
-
-/**
- * @brief OTG1 RX shared FIFO size.
- * @note Must be a multiple of 4.
- */
-#if !defined(STM32_USB_OTG1_RX_FIFO_SIZE) || defined(__DOXYGEN__)
-#define STM32_USB_OTG1_RX_FIFO_SIZE 512
-#endif
-
-/**
- * @brief OTG2 RX shared FIFO size.
- * @note Must be a multiple of 4.
- */
-#if !defined(STM32_USB_OTG2_RX_FIFO_SIZE) || defined(__DOXYGEN__)
-#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
-#endif
-
-/**
- * @brief Dedicated data pump threads priority.
- */
-#if !defined(STM32_USB_OTG_THREAD_PRIO) || defined(__DOXYGEN__)
-#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
-#endif
-
-/**
- * @brief Dedicated data pump threads stack size.
- */
-#if !defined(STM32_USB_OTG_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
-#define STM32_USB_OTG_THREAD_STACK_SIZE 128
-#endif
-
-/**
- * @brief Exception priority level during TXFIFOs operations.
- * @note Because an undocumented silicon behavior the operation of
- * copying a packet into a TXFIFO must not be interrupted by
- * any other operation on the OTG peripheral.
- * This parameter represents the priority mask during copy
- * operations. The default value only allows to call USB
- * functions from callbacks invoked from USB ISR handlers.
- * If you need to invoke USB functions from other handlers
- * then raise this priority mast to the same level of the
- * handler you need to use.
- * @note The value zero means disabled, when disabled calling USB
- * functions is only safe from thread level or from USB
- * callbacks.
- */
-#if !defined(STM32_USB_OTGFIFO_FILL_BASEPRI) || defined(__DOXYGEN__)
-#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if STM32_USB_USE_OTG1 && !STM32_HAS_OTG1
-#error "OTG1 not present in the selected device"
-#endif
-
-#if STM32_USB_USE_OTG2 && !STM32_HAS_OTG2
-#error "OTG2 not present in the selected device"
-#endif
-
-#if !STM32_USB_USE_OTG1 && !STM32_USB_USE_OTG2
-#error "USB driver activated but no USB peripheral assigned"
-#endif
-
-#if STM32_USB_USE_OTG1 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_USB_OTG1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to OTG1"
-#endif
-
-#if STM32_USB_USE_OTG2 && \
- !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_USB_OTG2_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to OTG2"
-#endif
-
-#if (STM32_USB_OTG1_RX_FIFO_SIZE & 3) != 0
-#error "OTG1 RX FIFO size must be a multiple of 4"
-#endif
-
-#if (STM32_USB_OTG2_RX_FIFO_SIZE & 3) != 0
-#error "OTG2 RX FIFO size must be a multiple of 4"
-#endif
-
-#if defined(STM32F4XX) || defined(STM32F2XX)
-#define STM32_USBCLK STM32_PLL48CLK
-#elif defined(STM32F10X_CL)
-#define STM32_USBCLK STM32_OTGFSCLK
-#else
-#error "unsupported STM32 platform for OTG functionality"
-#endif
-
-#if STM32_USBCLK != 48000000
-#error "the USB OTG driver requires a 48MHz clock"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Peripheral-specific parameters block.
- */
-typedef struct {
- uint32_t rx_fifo_size;
- uint32_t otg_ram_size;
- uint32_t num_endpoints;
-} stm32_otg_params_t;
-
-/**
- * @brief Type of an IN endpoint state structure.
- */
-typedef struct {
- /**
- * @brief Buffer mode, queue or linear.
- */
- bool_t txqueued;
- /**
- * @brief Requested transmit transfer size.
- */
- size_t txsize;
- /**
- * @brief Transmitted bytes so far.
- */
- size_t txcnt;
- union {
- struct {
- /**
- * @brief Pointer to the transmission linear buffer.
- */
- const uint8_t *txbuf;
- } linear;
- struct {
- /**
- * @brief Pointer to the output queue.
- */
- OutputQueue *txqueue;
- } queue;
- } mode;
-} USBInEndpointState;
-
-/**
- * @brief Type of an OUT endpoint state structure.
- */
-typedef struct {
- /**
- * @brief Buffer mode, queue or linear.
- */
- bool_t rxqueued;
- /**
- * @brief Requested receive transfer size.
- */
- size_t rxsize;
- /**
- * @brief Received bytes so far.
- */
- size_t rxcnt;
- union {
- struct {
- /**
- * @brief Pointer to the receive linear buffer.
- */
- uint8_t *rxbuf;
- } linear;
- struct {
- /**
- * @brief Pointer to the input queue.
- */
- InputQueue *rxqueue;
- } queue;
- } mode;
-} USBOutEndpointState;
-
-/**
- * @brief Type of an USB endpoint configuration structure.
- * @note Platform specific restrictions may apply to endpoints.
- */
-typedef struct {
- /**
- * @brief Type and mode of the endpoint.
- */
- uint32_t ep_mode;
- /**
- * @brief Setup packet notification callback.
- * @details This callback is invoked when a setup packet has been
- * received.
- * @post The application must immediately call @p usbReadPacket() in
- * order to access the received packet.
- * @note This field is only valid for @p USB_EP_MODE_TYPE_CTRL
- * endpoints, it should be set to @p NULL for other endpoint
- * types.
- */
- usbepcallback_t setup_cb;
- /**
- * @brief IN endpoint notification callback.
- * @details This field must be set to @p NULL if the IN endpoint is not
- * used.
- */
- usbepcallback_t in_cb;
- /**
- * @brief OUT endpoint notification callback.
- * @details This field must be set to @p NULL if the OUT endpoint is not
- * used.
- */
- usbepcallback_t out_cb;
- /**
- * @brief IN endpoint maximum packet size.
- * @details This field must be set to zero if the IN endpoint is not
- * used.
- */
- uint16_t in_maxsize;
- /**
- * @brief OUT endpoint maximum packet size.
- * @details This field must be set to zero if the OUT endpoint is not
- * used.
- */
- uint16_t out_maxsize;
- /**
- * @brief @p USBEndpointState associated to the IN endpoint.
- * @details This structure maintains the state of the IN endpoint.
- */
- USBInEndpointState *in_state;
- /**
- * @brief @p USBEndpointState associated to the OUT endpoint.
- * @details This structure maintains the state of the OUT endpoint.
- */
- USBOutEndpointState *out_state;
- /* End of the mandatory fields.*/
- /**
- * @brief Determines the space allocated for the TXFIFO as multiples of
- * the packet size (@p in_maxsize). Note that zero is interpreted
- * as one for simplicity and robustness.
- */
- uint16_t in_multiplier;
- /**
- * @brief Pointer to a buffer for setup packets.
- * @details Setup packets require a dedicated 8-bytes buffer, set this
- * field to @p NULL for non-control endpoints.
- */
- uint8_t *setup_buf;
-} USBEndpointConfig;
-
-/**
- * @brief Type of an USB driver configuration structure.
- */
-typedef struct {
- /**
- * @brief USB events callback.
- * @details This callback is invoked when an USB driver event is registered.
- */
- usbeventcb_t event_cb;
- /**
- * @brief Device GET_DESCRIPTOR request callback.
- * @note This callback is mandatory and cannot be set to @p NULL.
- */
- usbgetdescriptor_t get_descriptor_cb;
- /**
- * @brief Requests hook callback.
- * @details This hook allows to be notified of standard requests or to
- * handle non standard requests.
- */
- usbreqhandler_t requests_hook_cb;
- /**
- * @brief Start Of Frame callback.
- */
- usbcallback_t sof_cb;
- /* End of the mandatory fields.*/
-} USBConfig;
-
-/**
- * @brief Structure representing an USB driver.
- */
-struct USBDriver {
- /**
- * @brief Driver state.
- */
- usbstate_t state;
- /**
- * @brief Current configuration data.
- */
- const USBConfig *config;
- /**
- * @brief Bit map of the transmitting IN endpoints.
- */
- uint16_t transmitting;
- /**
- * @brief Bit map of the receiving OUT endpoints.
- */
- uint16_t receiving;
- /**
- * @brief Active endpoints configurations.
- */
- const USBEndpointConfig *epc[USB_MAX_ENDPOINTS + 1];
- /**
- * @brief Fields available to user, it can be used to associate an
- * application-defined handler to an IN endpoint.
- * @note The base index is one, the endpoint zero does not have a
- * reserved element in this array.
- */
- void *in_params[USB_MAX_ENDPOINTS];
- /**
- * @brief Fields available to user, it can be used to associate an
- * application-defined handler to an OUT endpoint.
- * @note The base index is one, the endpoint zero does not have a
- * reserved element in this array.
- */
- void *out_params[USB_MAX_ENDPOINTS];
- /**
- * @brief Endpoint 0 state.
- */
- usbep0state_t ep0state;
- /**
- * @brief Next position in the buffer to be transferred through endpoint 0.
- */
- uint8_t *ep0next;
- /**
- * @brief Number of bytes yet to be transferred through endpoint 0.
- */
- size_t ep0n;
- /**
- * @brief Endpoint 0 end transaction callback.
- */
- usbcallback_t ep0endcb;
- /**
- * @brief Setup packet buffer.
- */
- uint8_t setup[8];
- /**
- * @brief Current USB device status.
- */
- uint16_t status;
- /**
- * @brief Assigned USB address.
- */
- uint8_t address;
- /**
- * @brief Current USB device configuration.
- */
- uint8_t configuration;
-#if defined(USB_DRIVER_EXT_FIELDS)
- USB_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the OTG peripheral associated to this driver.
- */
- stm32_otg_t *otg;
- /**
- * @brief Peripheral-specific parameters.
- */
- const stm32_otg_params_t *otgparams;
- /**
- * @brief Pointer to the next address in the packet memory.
- */
- uint32_t pmnext;
- /**
- * @brief Mask of TXFIFOs to be filled by the pump thread.
- */
- uint32_t txpending;
- /**
- * @brief Pointer to the thread.
- */
- Thread *thd_ptr;
- /**
- * @brief Pointer to the thread when it is sleeping or @p NULL.
- */
- Thread *thd_wait;
- /**
- * @brief Working area for the dedicated data pump thread;
- */
- WORKING_AREA(wa_pump, STM32_USB_OTG_THREAD_STACK_SIZE);
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @brief Returns the exact size of a receive transaction.
- * @details The received size can be different from the size specified in
- * @p usbStartReceiveI() because the last packet could have a size
- * different from the expected one.
- * @pre The OUT endpoint must have been configured in transaction mode
- * in order to use this function.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- * @return Received data size.
- *
- * @notapi
- */
-#define usb_lld_get_transaction_size(usbp, ep) \
- ((usbp)->epc[ep]->out_state->rxcnt)
-
-/**
- * @brief Connects the USB device.
- *
- * @api
- */
-#define usb_lld_connect_bus(usbp) ((usbp)->otg->GCCFG |= GCCFG_VBUSBSEN)
-
-/**
- * @brief Disconnect the USB device.
- *
- * @api
- */
-#define usb_lld_disconnect_bus(usbp) ((usbp)->otg->GCCFG &= ~GCCFG_VBUSBSEN)
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if STM32_USB_USE_OTG1 && !defined(__DOXYGEN__)
-extern USBDriver USBD1;
-#endif
-
-#if STM32_USB_USE_OTG2 && !defined(__DOXYGEN__)
-extern USBDriver USBD2;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void usb_lld_init(void);
- void usb_lld_start(USBDriver *usbp);
- void usb_lld_stop(USBDriver *usbp);
- void usb_lld_reset(USBDriver *usbp);
- void usb_lld_set_address(USBDriver *usbp);
- void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep);
- void usb_lld_disable_endpoints(USBDriver *usbp);
- usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep);
- usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep);
- void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf);
- void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep);
- void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep);
- void usb_lld_start_out(USBDriver *usbp, usbep_t ep);
- void usb_lld_start_in(USBDriver *usbp, usbep_t ep);
- void usb_lld_stall_out(USBDriver *usbp, usbep_t ep);
- void usb_lld_stall_in(USBDriver *usbp, usbep_t ep);
- void usb_lld_clear_out(USBDriver *usbp, usbep_t ep);
- void usb_lld_clear_in(USBDriver *usbp, usbep_t ep);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_USB */
-
-#endif /* _USB_LLD_H_ */
-
-/** @} */
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