Reintegrate sama5d2_dev branch

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10878 35acf78f-673a-0410-8e92-d51de3d6d3f4

3 files changed, 123 insertions, 26 deletions

diff --git a/os/common/startup/ARM/devices/SAMA5D2/armparams.h b/os/common/startup/ARM/devices/SAMA5D2/armparams.h
index 9e0ba1210..29e6613fe 100755
--- a/os/common/startup/ARM/devices/SAMA5D2/armparams.h
+++ b/os/common/startup/ARM/devices/SAMA5D2/armparams.h
@@ -34,6 +34,11 @@
 #define ARM_CORE                ARM_CORE_CORTEX_A5

 

 /**

+ * @brief   Cortex core model.

+ */

+#define CORTEX_MODEL            5

+

+/**

  * @brief   Thumb-capable.

  */

 #define ARM_SUPPORTS_THUMB      1

@@ -44,17 +49,43 @@
 #define ARM_SUPPORTS_THUMB2     1

 

 /**

+ * @brief   VFPv4-D16 FPU.

+ */

+#define TARGET_FEATURE_EXTENSION_REGISTER_COUNT    16

+

+/**

  * @brief   Implementation of the wait-for-interrupt state enter.

  */

 #define ARM_WFI_IMPL            asm volatile ("wfi")

 

 #if !defined(_FROM_ASM_) || defined(__DOXYGEN__)

+/* If the device type is not externally defined, for example from the Makefile,

+   then a file named board.h is included. This file must contain a device

+   definition compatible with the vendor include file.*/

+#if !defined (SAMA5D21) && !defined (SAMA5D22) &&  !defined (SAMA5D23) &&   \

+    !defined (SAMA5D24) && !defined (SAMA5D25) &&  !defined (SAMA5D26) &&   \

+    !defined (SAMA5D27) && !defined (SAMA5D28)

+#include "board.h"

+#endif

+

+/* Including the device CMSIS header. Note, we are not using the definitions

+   from this header because we need this file to be usable also from

+   assembler source files. We verify that the info matches instead.*/

+#include "sama5d2x.h"

+

+/*lint -save -e9029 [10.4] Signedness comes from external files, it is

+  unpredictable but gives no problems.*/

+#if CORTEX_MODEL != __CORTEX_A

+#error "CMSIS __CORTEX_A mismatch"

+#endif

+

 /**

  * @brief   Address of the IRQ vector register in the interrupt controller.

  */

 #define ARM_IRQ_VECTOR_REG      0xF803C010U

 #else

 #define ARM_IRQ_VECTOR_REG      0xF803C010

+

 #endif

 #endif /* ARMPARAMS_H */

 

diff --git a/os/common/startup/ARM/devices/SAMA5D2/boot.S b/os/common/startup/ARM/devices/SAMA5D2/boot.S
index d507ea8b4..2de5be0f2 100644
--- a/os/common/startup/ARM/devices/SAMA5D2/boot.S
+++ b/os/common/startup/ARM/devices/SAMA5D2/boot.S
@@ -23,9 +23,11 @@
  */
 #if !defined(__DOXYGEN__)
 
-                .set    AIC_REDIR_KEY, 0x5B6C0E26 << 1
-                .set    SFR_SN1, 	   0xF8030050
-                .set	SFR_AICREDIR,  0xF8030054
+                .set    AIC_REDIR_KEY,  0x5B6C0E26 << 1
+                .set    SFR_SN1, 	    0xF8030050
+                .set	SFR_AICREDIR,   0xF8030054
+                .set    SFR_L2CC_HRAMC, 0xF8030058
+                .set    L2CC_CR,        0x00A00100
 
                 .section .boot
                 .code   32
@@ -35,22 +37,45 @@
  */
 				.global Boot_Handler
 Boot_Handler:
-				/*
-				 * Set VBAR to system vectors table
-				 */
-                ldr		r0, =_start
-                mcr 	p15, 0, r0, c12, c0, 0
+                /*
+                 * Set VBAR to system vectors table
+                 */
+                ldr     r0, =_start
+                mcr     p15, 0, r0, c12, c0, 0
                 /*
                  * Do not redirect secure interrupts to AIC
                  */
-				ldr		r0, =AIC_REDIR_KEY
+				ldr     r0, =AIC_REDIR_KEY
 				ldr     r1, =SFR_SN1
-				ldr		r1, [r1]
-				eor		r0, r0, r1
-				bic		r0, r0, #0x1
-				ldr		r1, =SFR_AICREDIR
-				str		r0, [r1]
-				b       Reset_Handler
+				ldr     r1, [r1]
+				eor     r0, r0, r1
+				bic     r0, r0, #0x1
+				ldr     r1, =SFR_AICREDIR
+				str     r0, [r1]
+                /*
+                 * Reset SCTLR Settings
+                 */
+                mrc     p15, 0, r0, c1, c0, 0       // Read CP15 System Control register
+                bic     r0, r0, #(0x1 << 12)        // Clear I bit 12 to disable I Cache
+                bic     r0, r0, #(0x1 <<  2)        // Clear C bit  2 to disable D Cache
+                bic     r0, r0, #0x1                // Clear M bit  0 to disable MMU
+                bic     r0, r0, #(0x1 << 11)        // Clear Z bit 11 to disable branch prediction
+                bic     r0, r0, #(0x1 << 13)        // Clear V bit 13 to disable hivecs
+                mcr     p15, 0, r0, c1, c0, 0       // Write value back to CP15 System Control register
+                isb
+                /*
+                 * Turn off L2Cache
+                 */
+                bic     r0, r0, #0x1
+                ldr     r1, =L2CC_CR
+                str     r0, [r1]
+                /*
+                 * Configure the L2 cache to be used as an internal SRAM
+                 */
+                bic     r0, r0, #0x1
+                ldr     r1, =SFR_L2CC_HRAMC
+                str     r0, [r1]
+                b       Reset_Handler
 #endif /* !defined(__DOXYGEN__) */
 
 /** @} */
diff --git a/os/common/startup/ARM/devices/SAMA5D2/sama5d2x.h b/os/common/startup/ARM/devices/SAMA5D2/sama5d2x.h
index c00f6b8fd..86123a031 100644
--- a/os/common/startup/ARM/devices/SAMA5D2/sama5d2x.h
+++ b/os/common/startup/ARM/devices/SAMA5D2/sama5d2x.h
@@ -32,16 +32,7 @@
 #include <stddef.h>
 #include <stdint.h>
 #include <stdbool.h>
-
-#ifdef __cplusplus
-#define  __I  volatile         /**< Defines 'read-only'  permissions */
-#else
-#define  __I  volatile const   /**< Defines 'read-only'  permissions */
-#endif
-
-#define  __O  volatile         /**< Defines 'write-only' permissions */
-#define  __IO volatile         /**< Defines 'read/write' permissions */
- 
+#include "ARMCA5.h"
 /**
   * @brief SAMA5D2 Family
   */
@@ -70,6 +61,7 @@
 #else
  #error "Please select first the target SAMA5D2x device used in your application (in sama5d2x.h file)"
 #endif
+
 /**@} */
 
 /**
@@ -317,7 +309,56 @@
 #define ID_RXLP_MSK           (1 << (ID_RXLP & 0x1F))
 #define ID_CHIPID_MSK         (1 << (ID_CHIPID & 0x1F))
 
-/**@} */
+/* MASTER MATRIX ID DEFINITION FOR SAMA5D2x */
+
+#define H64MX_MASTER_BRIDGE_FROM_AXI  0
+#define H64MX_MASTER_XDMAC0_0         1
+#define H64MX_MASTER_XDMAC0_1         2
+#define H64MX_MASTER_XDMAC1_0         3
+#define H64MX_MASTER_XDMAC1_1         4
+#define H64MX_MASTER_LCDC_DMA_0       5
+#define H64MX_MASTER_LCDC_DMA_1       6
+#define H64MX_MASTER_SDMMC0           7
+#define H64MX_MASTER_SDMMC1           8
+#define H64MX_MASTER_ISC_DMA          9
+#define H64MX_MASTER_AESB            10
+#define H64MX_MASTER_BRIDGE_H64MX    11
+
+#define H32MX_MASTER_BRIDGE_H32MX     0
+#define H32MX_MASTER_ICM              1
+#define H32MX_MASTER_UHPHS_EHCI_DMA   2
+#define H32MX_MASTER_UHPHS_OHCI_DMA   3
+#define H32MX_MASTER_UDPHS_DMA        4
+#define H32MX_MASTER_GMAC_DMA         5
+#define H32MX_MASTER_CAN0_DMA         6
+#define H32MX_MASTER_CAN1_DMA         7
+
+ /* SLAVE MATRIX ID DEFINITIONS FOR SAMA5D2x */
+
+ #define H64MX_SLAVE_BRIDGE_H32MX     0
+ #define H64MX_SLAVE_APB              1
+ #define H64MX_SLAVE_SDMMC            1
+ #define H64MX_SLAVE_DDR_PORT0        2
+ #define H64MX_SLAVE_DDR_PORT1        3
+ #define H64MX_SLAVE_DDR_PORT2        4
+ #define H64MX_SLAVE_DDR_PORT3        5
+ #define H64MX_SLAVE_DDR_PORT4        6
+ #define H64MX_SLAVE_DDR_PORT5        7
+ #define H64MX_SLAVE_DDR_PORT6        8
+ #define H64MX_SLAVE_DDR_PORT7        9
+ #define H64MX_SLAVE_SRAM            10
+ #define H64MX_SLAVE_L2C_SRAM        11
+ #define H64MX_SLAVE_QSPI0           12
+ #define H64MX_SLAVE_QSPI1           13
+ #define H64MX_SLAVE_AESB            14
+
+ #define H32MX_SLAVE_BRIDGE_H64MX     0
+ #define H32MX_SLAVE_APB0             1
+ #define H32MX_SLAVE_APB1             2
+ #define H32MX_SLAVE_EBI              3
+ #define H32MX_SLAVE_NFC_CMD          3
+ #define H32MX_SLAVE_NFC_SRAM         4
+ #define H32MX_SLAVE_USB              5
 
 #ifdef __cplusplus
 }