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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-09-15 11:30:02 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-09-15 11:30:02 +0000 |
| commit | c89f1992ef2d66f9f4417bc0f5b9f29dc42e630e (patch) | |
| tree | a27eb5fca0bfdde0f84372e2439c9ada235580b9 /demos | |
| parent | a538caa615c12e7e2ab3f6bccfc1d81af749b64b (diff) | |
| download | ChibiOS-c89f1992ef2d66f9f4417bc0f5b9f29dc42e630e.tar.gz ChibiOS-c89f1992ef2d66f9f4417bc0f5b9f29dc42e630e.tar.bz2 ChibiOS-c89f1992ef2d66f9f4417bc0f5b9f29dc42e630e.zip | |
Reintegrated timer-related drivers in L4+ HAL.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12262 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'demos')
| -rw-r--r-- | demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h index 0e56a339c..29baa0361 100644 --- a/demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h @@ -136,6 +136,22 @@ /*
* GPT driver system settings.
*/
+#define STM32_GPT_USE_TIM1 FALSE
+#define STM32_GPT_USE_TIM2 FALSE
+#define STM32_GPT_USE_TIM3 FALSE
+#define STM32_GPT_USE_TIM4 FALSE
+#define STM32_GPT_USE_TIM5 FALSE
+#define STM32_GPT_USE_TIM6 FALSE
+#define STM32_GPT_USE_TIM7 FALSE
+#define STM32_GPT_USE_TIM8 FALSE
+#define STM32_GPT_TIM1_IRQ_PRIORITY 7
+#define STM32_GPT_TIM2_IRQ_PRIORITY 7
+#define STM32_GPT_TIM3_IRQ_PRIORITY 7
+#define STM32_GPT_TIM4_IRQ_PRIORITY 7
+#define STM32_GPT_TIM5_IRQ_PRIORITY 7
+#define STM32_GPT_TIM6_IRQ_PRIORITY 7
+#define STM32_GPT_TIM7_IRQ_PRIORITY 7
+#define STM32_GPT_TIM8_IRQ_PRIORITY 7
/*
* I2C driver system settings.
@@ -144,10 +160,35 @@ /*
* ICU driver system settings.
*/
+#define STM32_ICU_USE_TIM1 FALSE
+#define STM32_ICU_USE_TIM2 FALSE
+#define STM32_ICU_USE_TIM3 FALSE
+#define STM32_ICU_USE_TIM4 FALSE
+#define STM32_ICU_USE_TIM5 FALSE
+#define STM32_ICU_USE_TIM8 FALSE
+#define STM32_ICU_TIM1_IRQ_PRIORITY 7
+#define STM32_ICU_TIM2_IRQ_PRIORITY 7
+#define STM32_ICU_TIM3_IRQ_PRIORITY 7
+#define STM32_ICU_TIM4_IRQ_PRIORITY 7
+#define STM32_ICU_TIM5_IRQ_PRIORITY 7
+#define STM32_ICU_TIM8_IRQ_PRIORITY 7
/*
* PWM driver system settings.
*/
+#define STM32_PWM_USE_ADVANCED FALSE
+#define STM32_PWM_USE_TIM1 FALSE
+#define STM32_PWM_USE_TIM2 FALSE
+#define STM32_PWM_USE_TIM3 FALSE
+#define STM32_PWM_USE_TIM4 FALSE
+#define STM32_PWM_USE_TIM5 FALSE
+#define STM32_PWM_USE_TIM8 FALSE
+#define STM32_PWM_TIM1_IRQ_PRIORITY 7
+#define STM32_PWM_TIM2_IRQ_PRIORITY 7
+#define STM32_PWM_TIM3_IRQ_PRIORITY 7
+#define STM32_PWM_TIM4_IRQ_PRIORITY 7
+#define STM32_PWM_TIM5_IRQ_PRIORITY 7
+#define STM32_PWM_TIM8_IRQ_PRIORITY 7
/*
* SDC driver system settings.
|