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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-06-14 12:34:59 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-06-14 12:34:59 +0000 |
| commit | 126943984c591c952bd0b9f6b2d36d97be823de3 (patch) | |
| tree | ba80c46171dcc1e34bbd0110edb0cca645bd50ed /demos/PPC-SPC560D-GCC/mcuconf.h | |
| parent | f0e62eb4b588d8b2fbf858efb7b41226a2424d81 (diff) | |
| download | ChibiOS-126943984c591c952bd0b9f6b2d36d97be823de3.tar.gz ChibiOS-126943984c591c952bd0b9f6b2d36d97be823de3.tar.bz2 ChibiOS-126943984c591c952bd0b9f6b2d36d97be823de3.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5848 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'demos/PPC-SPC560D-GCC/mcuconf.h')
| -rw-r--r-- | demos/PPC-SPC560D-GCC/mcuconf.h | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/demos/PPC-SPC560D-GCC/mcuconf.h b/demos/PPC-SPC560D-GCC/mcuconf.h index dd1deb91e..a62a73496 100644 --- a/demos/PPC-SPC560D-GCC/mcuconf.h +++ b/demos/PPC-SPC560D-GCC/mcuconf.h @@ -23,6 +23,8 @@ *
* IRQ priorities:
* 1...15 Lowest...Highest.
+ * DMA priorities:
+ * 0...15 Highest...Lowest.
*/
#define SPC560Dxx_MCUCONF
@@ -162,6 +164,15 @@ #define SPC5_CLOCK_FAILURE_HOOK() chSysHalt()
/*
+ * EDMA driver settings.
+ */
+#define SPC5_EDMA_CR_SETTING 0
+#define SPC5_EDMA_GROUP0_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_ERROR_IRQ_PRIO 2
+#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
+
+/*
* SERIAL driver system settings.
*/
#define SPC5_SERIAL_USE_LINFLEX0 TRUE
@@ -182,3 +193,38 @@ SPC5_ME_PCTL_LP(2))
#define SPC5_SERIAL_LINFLEX2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
SPC5_ME_PCTL_LP(0))
+
+/*
+ * SPI driver system settings.
+ */
+#define SPC5_SPI_USE_DSPI0 FALSE
+#define SPC5_SPI_USE_DSPI1 FALSE
+#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
+#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
+#define SPC5_SPI_DSPI0_IRQ_PRIO 10
+#define SPC5_SPI_DSPI1_IRQ_PRIO 10
+#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
+#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
|