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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2012-04-28 16:09:07 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2012-04-28 16:09:07 +0000
commitc670c00668799feea3ec8f6c637b730b1c559e6e (patch)
tree6deaaedde682cacc3c8476a0016dcc85f4238566 /boards
parentdc4a2a16809ee83a4bd37ea971475fd5be441d50 (diff)
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Fixed wrong USART3 IO mapping.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4145 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'boards')
-rw-r--r--boards/OLIMEX_STM32_P407/board.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/boards/OLIMEX_STM32_P407/board.h b/boards/OLIMEX_STM32_P407/board.h
index 9caafed6d..35e16582b 100644
--- a/boards/OLIMEX_STM32_P407/board.h
+++ b/boards/OLIMEX_STM32_P407/board.h
@@ -405,10 +405,10 @@
PIN_PUDR_PULLUP(GPIOD_USELESS15))
#define VAL_GPIOD_ODR 0xFFFFFFFF
#define VAL_GPIOD_AFRL 0x00000000
-#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_USART3_TX, 8) | \
- PIN_AFIO_AF(GPIOD_USART3_RX, 8) | \
- PIN_AFIO_AF(GPIOD_USART3_CTS, 8) | \
- PIN_AFIO_AF(GPIOD_USART3_RTS, 8))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_USART3_TX, 7) | \
+ PIN_AFIO_AF(GPIOD_USART3_RX, 7) | \
+ PIN_AFIO_AF(GPIOD_USART3_CTS, 7) | \
+ PIN_AFIO_AF(GPIOD_USART3_RTS, 7))
/*
* Port E setup.