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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2011-01-08 13:40:44 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2011-01-08 13:40:44 +0000
commite01b1f1f1eeff80a2670e0c7d52619e7dd5a85e2 (patch)
tree94a0a5f68e38513ec4a38d986ae40b8e511443b7
parentf1c970760f8cf9e5346a6dd02f0a6fbef88c0a6b (diff)
downloadChibiOS-e01b1f1f1eeff80a2670e0c7d52619e7dd5a85e2.tar.gz
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2617 35acf78f-673a-0410-8e92-d51de3d6d3f4
-rw-r--r--demos/ARMCM0-LPC1114-LPCXPRESSO/keil/ch.uvopt1904
-rw-r--r--demos/ARMCM0-LPC1114-LPCXPRESSO/keil/ch.uvproj1010
-rw-r--r--os/ports/IAR/ARMCMx/chcore_v6m.h4
-rw-r--r--os/ports/IAR/ARMCMx/chcoreasm_v6m.s4
-rw-r--r--os/ports/RVCT/ARMCMx/chcore_v6m.c56
-rw-r--r--os/ports/RVCT/ARMCMx/chcore_v6m.h250
-rw-r--r--os/ports/RVCT/ARMCMx/chcoreasm_v6m.s130
-rw-r--r--os/ports/RVCT/ARMCMx/cstartup.s3
8 files changed, 3354 insertions, 7 deletions
diff --git a/demos/ARMCM0-LPC1114-LPCXPRESSO/keil/ch.uvopt b/demos/ARMCM0-LPC1114-LPCXPRESSO/keil/ch.uvopt
new file mode 100644
index 000000000..ad6bc133e
--- /dev/null
+++ b/demos/ARMCM0-LPC1114-LPCXPRESSO/keil/ch.uvopt
@@ -0,0 +1,1904 @@
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+ <FilenameWithoutPath>main.c</FilenameWithoutPath>
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+ <PathWithFileName>..\chconf.h</PathWithFileName>
+ <FilenameWithoutPath>chconf.h</FilenameWithoutPath>
+ </File>
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+ <PathWithFileName>..\halconf.h</PathWithFileName>
+ <FilenameWithoutPath>halconf.h</FilenameWithoutPath>
+ </File>
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+ <GroupNumber>7</GroupNumber>
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+ <PathWithFileName>..\mcuconf.h</PathWithFileName>
+ <FilenameWithoutPath>mcuconf.h</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <MDIGroups>
+ <Orientation>1</Orientation>
+ <ActiveMDIGroup>0</ActiveMDIGroup>
+ <MDIGroup>
+ <Size>100</Size>
+ <ActiveTab>0</ActiveTab>
+ <Documents>
+ <Doc>
+ <Name>..\main.c</Name>
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+ </MDIGroup>
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+</ProjectOpt>
diff --git a/demos/ARMCM0-LPC1114-LPCXPRESSO/keil/ch.uvproj b/demos/ARMCM0-LPC1114-LPCXPRESSO/keil/ch.uvproj
new file mode 100644
index 000000000..e69135a04
--- /dev/null
+++ b/demos/ARMCM0-LPC1114-LPCXPRESSO/keil/ch.uvproj
@@ -0,0 +1,1010 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>Demo</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>LPC1114x302</Device>
+ <Vendor>NXP (founded by Philips)</Vendor>
+ <Cpu>IRAM(0x10000000-0x10001FFF) IROM(0-0x7FFF) CLOCK(12000000) CPUTYPE("Cortex-M0")</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile>"STARTUP\NXP\LPC11xx\startup_LPC11xx.s" ("NXP LPC11xx Startup Code")</StartupFile>
+ <FlashDriverDll>UL2CM3(-UV1742AOE -O463 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10000000 -FC800 -FN1 -FF0LPC1xxx_32 -FS00 -FL08000)</FlashDriverDll>
+ <DeviceId>5376</DeviceId>
+ <RegisterFile>LPC11xx.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile></SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath>NXP\LPC11xx\</RegisterFilePath>
+ <DBRegisterFilePath>NXP\LPC11xx\</DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\obj\</OutputDirectory>
+ <OutputName>ch</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\lst\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll>DARMP1.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pLPC1114</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TARMP1.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pLPC1114</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
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+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>0</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>1</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>8</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>STLink\ST-LINKIII-KEIL.dll</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>4100</DriverSelection>
+ </Flash1>
+ <Flash2>STLink\ST-LINKIII-KEIL.dll</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
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+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M0"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>0</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
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+ <Ra1Chk>0</Ra1Chk>
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+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>1</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
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+ <Size>0x0</Size>
+ </Ocm2>
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+ </Ocm3>
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+ </Ocm4>
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+ <StartAddress>0x0</StartAddress>
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+ </Ocm5>
+ <Ocm6>
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+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
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+ <StartAddress>0x10000000</StartAddress>
+ <Size>0x2000</Size>
+ </IRAM>
+ <IROM>
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+ <StartAddress>0x0</StartAddress>
+ <Size>0x8000</Size>
+ </IROM>
+ <XRAM>
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+ <StartAddress>0x0</StartAddress>
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+ </XRAM>
+ <OCR_RVCT1>
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+ </OCR_RVCT1>
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+ <Size>0x1</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
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+ <Define>__heap_base__=Image$$RW_IRAM1$$ZI$$Limit __heap_end__=Image$$RW_IRAM2$$Base</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\;..\..\..\os\kernel\include;..\..\..\os\ports\RVCT\ARMCMx;..\..\..\os\ports\RVCT\ARMCMx\LPC11xx;..\..\..\os\hal\include;..\..\..\os\hal\platforms\LPC11xx;..\..\..\boards\EA_LPCXPRESSO_BB_1114;..\..\..\test</IncludePath>
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+ <FileType>1</FileType>
+ <FilePath>..\..\..\os\kernel\src\chvt.c</FilePath>
+ </File>
+ <File>
+ <FileName>ch.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\kernel\include\ch.h</FilePath>
+ </File>
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+ <FileName>chbsem.h</FileName>
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+ <FilePath>..\..\..\os\kernel\include\chbsem.h</FilePath>
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+ <FilePath>..\..\..\os\kernel\include\chcond.h</FilePath>
+ </File>
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+ <FileName>chdebug.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\kernel\include\chdebug.h</FilePath>
+ </File>
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+ <FileName>chdynamic.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\kernel\include\chdynamic.h</FilePath>
+ </File>
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+ <FileName>chevents.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\kernel\include\chevents.h</FilePath>
+ </File>
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+ <FileName>chfiles.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\kernel\include\chfiles.h</FilePath>
+ </File>
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+ <FileName>chheap.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\kernel\include\chheap.h</FilePath>
+ </File>
+ <File>
+ <FileName>chinline.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\kernel\include\chinline.h</FilePath>
+ </File>
+ <File>
+ <FileName>chioch.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\kernel\include\chioch.h</FilePath>
+ </File>
+ <File>
+ <FileName>chlists.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\kernel\include\chlists.h</FilePath>
+ </File>
+ <File>
+ <FileName>chmboxes.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\kernel\include\chmboxes.h</FilePath>
+ </File>
+ <File>
+ <FileName>chmemcore.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\kernel\include\chmemcore.h</FilePath>
+ </File>
+ <File>
+ <FileName>chmempools.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\kernel\include\chmempools.h</FilePath>
+ </File>
+ <File>
+ <FileName>chmsg.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\kernel\include\chmsg.h</FilePath>
+ </File>
+ <File>
+ <FileName>chmtx.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\kernel\include\chmtx.h</FilePath>
+ </File>
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+ <FileName>chqueues.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\kernel\include\chqueues.h</FilePath>
+ </File>
+ <File>
+ <FileName>chregistry.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\kernel\include\chregistry.h</FilePath>
+ </File>
+ <File>
+ <FileName>chschd.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\kernel\include\chschd.h</FilePath>
+ </File>
+ <File>
+ <FileName>chsem.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\kernel\include\chsem.h</FilePath>
+ </File>
+ <File>
+ <FileName>chstreams.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\kernel\include\chstreams.h</FilePath>
+ </File>
+ <File>
+ <FileName>chsys.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\kernel\include\chsys.h</FilePath>
+ </File>
+ <File>
+ <FileName>chthreads.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\kernel\include\chthreads.h</FilePath>
+ </File>
+ <File>
+ <FileName>chvt.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\kernel\include\chvt.h</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>hal</GroupName>
+ <Files>
+ <File>
+ <FileName>adc.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\os\hal\src\adc.c</FilePath>
+ </File>
+ <File>
+ <FileName>can.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\os\hal\src\can.c</FilePath>
+ </File>
+ <File>
+ <FileName>hal.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\os\hal\src\hal.c</FilePath>
+ </File>
+ <File>
+ <FileName>i2c.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\os\hal\src\i2c.c</FilePath>
+ </File>
+ <File>
+ <FileName>mac.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\os\hal\src\mac.c</FilePath>
+ </File>
+ <File>
+ <FileName>mmc_spi.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\os\hal\src\mmc_spi.c</FilePath>
+ </File>
+ <File>
+ <FileName>pal.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\os\hal\src\pal.c</FilePath>
+ </File>
+ <File>
+ <FileName>pwm.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\os\hal\src\pwm.c</FilePath>
+ </File>
+ <File>
+ <FileName>serial.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\os\hal\src\serial.c</FilePath>
+ </File>
+ <File>
+ <FileName>spi.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\os\hal\src\spi.c</FilePath>
+ </File>
+ <File>
+ <FileName>uart.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\os\hal\src\uart.c</FilePath>
+ </File>
+ <File>
+ <FileName>adc.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\hal\include\adc.h</FilePath>
+ </File>
+ <File>
+ <FileName>can.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\hal\include\can.h</FilePath>
+ </File>
+ <File>
+ <FileName>hal.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\hal\include\hal.h</FilePath>
+ </File>
+ <File>
+ <FileName>i2c.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\hal\include\i2c.h</FilePath>
+ </File>
+ <File>
+ <FileName>mac.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\hal\include\mac.h</FilePath>
+ </File>
+ <File>
+ <FileName>mii.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\hal\include\mii.h</FilePath>
+ </File>
+ <File>
+ <FileName>mmc_spi.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\hal\include\mmc_spi.h</FilePath>
+ </File>
+ <File>
+ <FileName>pal.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\hal\include\pal.h</FilePath>
+ </File>
+ <File>
+ <FileName>pwm.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\hal\include\pwm.h</FilePath>
+ </File>
+ <File>
+ <FileName>serial.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\hal\include\serial.h</FilePath>
+ </File>
+ <File>
+ <FileName>spi.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\hal\include\spi.h</FilePath>
+ </File>
+ <File>
+ <FileName>uart.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\hal\include\uart.h</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>platform</GroupName>
+ <Files>
+ <File>
+ <FileName>core_cm0.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\hal\platforms\LPC11xx\core_cm0.h</FilePath>
+ </File>
+ <File>
+ <FileName>hal_lld.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\os\hal\platforms\LPC11xx\hal_lld.c</FilePath>
+ </File>
+ <File>
+ <FileName>hal_lld.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\hal\platforms\LPC11xx\hal_lld.h</FilePath>
+ </File>
+ <File>
+ <FileName>LPC11xx.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\hal\platforms\LPC11xx\LPC11xx.h</FilePath>
+ </File>
+ <File>
+ <FileName>pal_lld.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\os\hal\platforms\LPC11xx\pal_lld.c</FilePath>
+ </File>
+ <File>
+ <FileName>pal_lld.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\hal\platforms\LPC11xx\pal_lld.h</FilePath>
+ </File>
+ <File>
+ <FileName>serial_lld.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\os\hal\platforms\LPC11xx\serial_lld.c</FilePath>
+ </File>
+ <File>
+ <FileName>serial_lld.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\hal\platforms\LPC11xx\serial_lld.h</FilePath>
+ </File>
+ <File>
+ <FileName>spi_lld.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\os\hal\platforms\LPC11xx\spi_lld.c</FilePath>
+ </File>
+ <File>
+ <FileName>spi_lld.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\hal\platforms\LPC11xx\spi_lld.h</FilePath>
+ </File>
+ <File>
+ <FileName>system_LPC11xx.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\os\hal\platforms\LPC11xx\system_LPC11xx.h</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>test</GroupName>
+ <Files>
+ <File>
+ <FileName>test.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\test\test.c</FilePath>
+ </File>
+ <File>
+ <FileName>testbmk.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\test\testbmk.c</FilePath>
+ </File>
+ <File>
+ <FileName>testdyn.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\test\testdyn.c</FilePath>
+ </File>
+ <File>
+ <FileName>testevt.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\test\testevt.c</FilePath>
+ </File>
+ <File>
+ <FileName>testheap.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\test\testheap.c</FilePath>
+ </File>
+ <File>
+ <FileName>testmbox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\test\testmbox.c</FilePath>
+ </File>
+ <File>
+ <FileName>testmsg.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\test\testmsg.c</FilePath>
+ </File>
+ <File>
+ <FileName>testmtx.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\test\testmtx.c</FilePath>
+ </File>
+ <File>
+ <FileName>testpools.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\test\testpools.c</FilePath>
+ </File>
+ <File>
+ <FileName>testqueues.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\test\testqueues.c</FilePath>
+ </File>
+ <File>
+ <FileName>testsem.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\test\testsem.c</FilePath>
+ </File>
+ <File>
+ <FileName>testthd.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\test\testthd.c</FilePath>
+ </File>
+ <File>
+ <FileName>test.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\test\test.h</FilePath>
+ </File>
+ <File>
+ <FileName>testbmk.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\test\testbmk.h</FilePath>
+ </File>
+ <File>
+ <FileName>testdyn.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\test\testdyn.h</FilePath>
+ </File>
+ <File>
+ <FileName>testevt.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\test\testevt.h</FilePath>
+ </File>
+ <File>
+ <FileName>testheap.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\test\testheap.h</FilePath>
+ </File>
+ <File>
+ <FileName>testmbox.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\test\testmbox.h</FilePath>
+ </File>
+ <File>
+ <FileName>testmsg.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\test\testmsg.h</FilePath>
+ </File>
+ <File>
+ <FileName>testmtx.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\test\testmtx.h</FilePath>
+ </File>
+ <File>
+ <FileName>testpools.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\test\testpools.h</FilePath>
+ </File>
+ <File>
+ <FileName>testqueues.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\test\testqueues.h</FilePath>
+ </File>
+ <File>
+ <FileName>testsem.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\test\testsem.h</FilePath>
+ </File>
+ <File>
+ <FileName>testthd.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\test\testthd.h</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>demo</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\main.c</FilePath>
+ </File>
+ <File>
+ <FileName>chconf.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\chconf.h</FilePath>
+ </File>
+ <File>
+ <FileName>halconf.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\halconf.h</FilePath>
+ </File>
+ <File>
+ <FileName>mcuconf.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\mcuconf.h</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/os/ports/IAR/ARMCMx/chcore_v6m.h b/os/ports/IAR/ARMCMx/chcore_v6m.h
index fe6c68a92..9209fbaf4 100644
--- a/os/ports/IAR/ARMCMx/chcore_v6m.h
+++ b/os/ports/IAR/ARMCMx/chcore_v6m.h
@@ -190,12 +190,12 @@ struct intctx {
/**
* @brief Disables all the interrupt sources.
*/
-#define port_disable() __enable_interrupt()
+#define port_disable() __disable_interrupt()
/**
* @brief Disables the interrupt sources below kernel-level priority.
*/
-#define port_suspend() __enable_interrupt()
+#define port_suspend() __disable_interrupt()
/**
* @brief Enables all the interrupt sources.
diff --git a/os/ports/IAR/ARMCMx/chcoreasm_v6m.s b/os/ports/IAR/ARMCMx/chcoreasm_v6m.s
index c9ee6a0c8..5f0887960 100644
--- a/os/ports/IAR/ARMCMx/chcoreasm_v6m.s
+++ b/os/ports/IAR/ARMCMx/chcoreasm_v6m.s
@@ -30,10 +30,6 @@
#define CORTEX_PRIORITY_MASK(n) ((n) << (8 - CORTEX_PRIORITY_BITS))
-#ifndef CORTEX_PRIORITY_SVCALL
-#define CORTEX_PRIORITY_SVCALL 1
-#endif
-
EXTCTX_SIZE SET 32
CONTEXT_OFFSET SET 12
diff --git a/os/ports/RVCT/ARMCMx/chcore_v6m.c b/os/ports/RVCT/ARMCMx/chcore_v6m.c
new file mode 100644
index 000000000..6340df81c
--- /dev/null
+++ b/os/ports/RVCT/ARMCMx/chcore_v6m.c
@@ -0,0 +1,56 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file RVCT/ARMCMx/chcore_v6m.c
+ * @brief ARMv6-M architecture port code.
+ *
+ * @addtogroup RVCT_ARMCMx_V6M_CORE
+ * @{
+ */
+
+#include "ch.h"
+
+/**
+ * @brief PC register temporary storage.
+ */
+regarm_t _port_saved_pc;
+
+/**
+ * @brief IRQ nesting counter.
+ */
+unsigned _port_irq_nesting;
+
+/**
+ * @brief System Timer vector.
+ * @details This interrupt is used as system tick.
+ * @note The timer must be initialized in the startup code.
+ */
+CH_IRQ_HANDLER(SysTickVector) {
+
+ CH_IRQ_PROLOGUE();
+
+ chSysLockFromIsr();
+ chSysTimerHandlerI();
+ chSysUnlockFromIsr();
+
+ CH_IRQ_EPILOGUE();
+}
+
+/** @} */
diff --git a/os/ports/RVCT/ARMCMx/chcore_v6m.h b/os/ports/RVCT/ARMCMx/chcore_v6m.h
new file mode 100644
index 000000000..796b7f22e
--- /dev/null
+++ b/os/ports/RVCT/ARMCMx/chcore_v6m.h
@@ -0,0 +1,250 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file RVCT/ARMCMx/chcore_v6m.h
+ * @brief ARMv6-M architecture port macros and structures.
+ *
+ * @addtogroup RVCT_ARMCMx_V6M_CORE
+ * @{
+ */
+
+#ifndef _CHCORE_V6M_H_
+#define _CHCORE_V6M_H_
+
+/*===========================================================================*/
+/* Port implementation part. */
+/*===========================================================================*/
+
+/**
+ * @brief Cortex-Mx exception context.
+ */
+struct cmxctx {
+ regarm_t r0;
+ regarm_t r1;
+ regarm_t r2;
+ regarm_t r3;
+ regarm_t r12;
+ regarm_t lr_thd;
+ regarm_t pc;
+ regarm_t xpsr;
+};
+
+#if !defined(__DOXYGEN__)
+struct extctx {
+ regarm_t xpsr;
+ regarm_t r12;
+ regarm_t lr;
+ regarm_t r0;
+ regarm_t r1;
+ regarm_t r2;
+ regarm_t r3;
+ regarm_t pc;
+};
+
+struct intctx {
+ regarm_t r8;
+ regarm_t r9;
+ regarm_t r10;
+ regarm_t r11;
+ regarm_t r4;
+ regarm_t r5;
+ regarm_t r6;
+ regarm_t r7;
+ regarm_t lr;
+};
+#endif
+
+/**
+ * @brief Platform dependent part of the @p chThdInit() API.
+ * @details This code usually setup the context switching frame represented
+ * by an @p intctx structure.
+ */
+#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
+ tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \
+ wsize - \
+ sizeof(struct intctx)); \
+ tp->p_ctx.r13->r4 = (void *)pf; \
+ tp->p_ctx.r13->r5 = arg; \
+ tp->p_ctx.r13->lr = (void *)_port_thread_start; \
+}
+
+/**
+ * @brief Stack size for the system idle thread.
+ * @details This size depends on the idle thread implementation, usually
+ * the idle thread should take no more space than those reserved
+ * by @p INT_REQUIRED_STACK.
+ * @note In this port it is set to 8 because the idle thread does have
+ * a stack frame when compiling without optimizations. You may
+ * reduce this value to zero when compiling with optimizations.
+ */
+#ifndef IDLE_THREAD_STACK_SIZE
+#define IDLE_THREAD_STACK_SIZE 8
+#endif
+
+/**
+ * @brief Per-thread stack overhead for interrupts servicing.
+ * @details This constant is used in the calculation of the correct working
+ * area size.
+ * This value can be zero on those architecture where there is a
+ * separate interrupt stack and the stack space between @p intctx and
+ * @p extctx is known to be zero.
+ * @note In this port it is conservatively set to 16 because the function
+ * @p chSchDoRescheduleI() can have a stack frame, expecially with
+ * compiler optimizations disabled.
+ */
+#ifndef INT_REQUIRED_STACK
+#define INT_REQUIRED_STACK 16
+#endif
+
+/**
+ * @brief IRQ prologue code.
+ * @details This macro must be inserted at the start of all IRQ handlers
+ * enabled to invoke system APIs.
+ */
+#define PORT_IRQ_PROLOGUE() { \
+ port_lock_from_isr(); \
+ _port_irq_nesting++; \
+ port_unlock_from_isr(); \
+}
+
+/**
+ * @brief IRQ epilogue code.
+ * @details This macro must be inserted at the end of all IRQ handlers
+ * enabled to invoke system APIs.
+ */
+#define PORT_IRQ_EPILOGUE() _port_irq_epilogue()
+
+/**
+ * @brief IRQ handler function declaration.
+ * @note @p id can be a function name or a vector number depending on the
+ * port implementation.
+ */
+#define PORT_IRQ_HANDLER(id) void id(void)
+
+/**
+ * @brief Fast IRQ handler function declaration.
+ * @note @p id can be a function name or a vector number depending on the
+ * port implementation.
+ */
+#define PORT_FAST_IRQ_HANDLER(id) void id(void)
+
+/**
+ * @brief Port-related initialization code.
+ */
+#define port_init() { \
+ _port_irq_nesting = 0; \
+ SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \
+ NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \
+ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \
+}
+
+/**
+ * @brief Kernel-lock action.
+ * @details Usually this function just disables interrupts but may perform
+ * more actions.
+ */
+#define port_lock() __disable_irq()
+
+/**
+ * @brief Kernel-unlock action.
+ * @details Usually this function just disables interrupts but may perform
+ * more actions.
+ */
+#define port_unlock() __enable_irq()
+
+/**
+ * @brief Kernel-lock action from an interrupt handler.
+ * @details This function is invoked before invoking I-class APIs from
+ * interrupt handlers. The implementation is architecture dependent,
+ * in its simplest form it is void.
+ * @note Same as @p port_lock() in this port.
+ */
+#define port_lock_from_isr() port_lock()
+
+/**
+ * @brief Kernel-unlock action from an interrupt handler.
+ * @details This function is invoked after invoking I-class APIs from interrupt
+ * handlers. The implementation is architecture dependent, in its
+ * simplest form it is void.
+ * @note Same as @p port_lock() in this port.
+ */
+#define port_unlock_from_isr() port_unlock()
+
+/**
+ * @brief Disables all the interrupt sources.
+ */
+#define port_disable() __disable_irq()
+
+/**
+ * @brief Disables the interrupt sources below kernel-level priority.
+ */
+#define port_suspend() __disable_irq()
+
+/**
+ * @brief Enables all the interrupt sources.
+ */
+#define port_enable() __enable_irq()
+
+/**
+ * @brief Enters an architecture-dependent IRQ-waiting mode.
+ * @details The function is meant to return when an interrupt becomes pending.
+ * The simplest implementation is an empty function or macro but this
+ * would not take advantage of architecture-specific power saving
+ * modes.
+ * @note Implemented as an inlined @p WFI instruction.
+ */
+#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
+#define port_wait_for_interrupt() __wfi()
+#else
+#define port_wait_for_interrupt()
+#endif
+
+/**
+ * @brief Performs a context switch between two threads.
+ * @details This is the most critical code in any port, this function
+ * is responsible for the context switch between 2 threads.
+ * @note The implementation of this code affects <b>directly</b> the context
+ * switch performance so optimize here as much as you can.
+ *
+ * @param[in] ntp the thread to be switched in
+ * @param[in] otp the thread to be switched out
+ */
+#define port_switch(ntp, otp) _port_switch(ntp, otp)
+
+#if !defined(__DOXYGEN__)
+extern regarm_t _port_saved_pc;
+extern unsigned _port_irq_nesting;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void port_halt(void);
+ void _port_switch(Thread *ntp, Thread *otp);
+ void _port_irq_epilogue(void);
+ void _port_switch_from_isr(void);
+ void _port_thread_start(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CHCORE_V6M_H_ */
+
+/** @} */
diff --git a/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s b/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s
new file mode 100644
index 000000000..e813d7eca
--- /dev/null
+++ b/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s
@@ -0,0 +1,130 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/*
+ * Imports the Cortex-Mx parameters header and performs the same calculations
+ * done in chcore.h.
+ */
+#include "cmparams.h"
+
+#define CORTEX_PRIORITY_MASK(n) ((n) << (8 - CORTEX_PRIORITY_BITS))
+
+EXTCTX_SIZE EQU 32
+CONTEXT_OFFSET EQU 12
+
+ PRESERVE8
+ THUMB
+ AREA |.text|, CODE, READONLY
+
+ IMPORT chThdExit
+ IMPORT chSchIsRescRequiredExI
+ IMPORT chSchDoRescheduleI
+ IMPORT _port_saved_pc
+ IMPORT _port_irq_nesting
+
+/*
+ * Performs a context switch between two threads.
+ */
+ EXPORT _port_switch
+_port_switch PROC
+ push {r4, r5, r6, r7, lr}
+ mov r4, r8
+ mov r5, r9
+ mov r6, r10
+ mov r7, r11
+ push {r4, r5, r6, r7}
+ mov r3, sp
+ str r3, [r1, #CONTEXT_OFFSET]
+ ldr r3, [r0, #CONTEXT_OFFSET]
+ mov sp, r3
+ pop {r4, r5, r6, r7}
+ mov r8, r4
+ mov r9, r5
+ mov r10, r6
+ mov r11, r7
+ pop {r4, r5, r6, r7, pc}
+ ENDP
+
+/*
+ * Start a thread by invoking its work function.
+ * If the work function returns @p chThdExit() is automatically invoked.
+ */
+ EXPORT _port_thread_start
+_port_thread_start PROC
+ cpsie i
+ mov r0, r5
+ blx r4
+ bl chThdExit
+ ENDP
+
+/*
+ * Post-IRQ switch code.
+ * Exception handlers return here for context switching.
+ */
+ EXPORT _port_switch_from_isr
+_port_switch_from_isr PROC
+ /* Note, saves r4 to make space for the PC.*/
+ push {r0, r1, r2, r3, r4}
+ mrs r0, APSR
+ mov r1, r12
+ push {r0, r1, lr}
+ ldr r0, =_port_saved_pc
+ ldr r0, [r0]
+ adds r0, r0, #1
+ str r0, [sp, #28]
+ bl chSchDoRescheduleI
+ pop {r0, r1, r2}
+ mov r12, r1
+ msr APSR, r0
+ mov lr, r2
+ cpsie i
+ pop {r0, r1, r2, r3, pc}
+ ENDP
+
+/*
+ * Reschedule verification and setup after an IRQ.
+ */
+ EXPORT _port_irq_epilogue
+_port_irq_epilogue PROC
+ push {r4, lr}
+ cpsid i
+ ldr r2, =_port_irq_nesting
+ ldr r3, [r2]
+ subs r3, r3, #1
+ str r3, [r2]
+ cmp r3, #0
+ beq skipexit
+ cpsie i
+ pop {r4, pc}
+skipexit
+ bl chSchIsRescRequiredExI
+ cmp r0, #0
+ beq notrequired
+ mrs r1, PSP
+ ldr r2, =_port_saved_pc
+ ldr r3, [r1, #24]
+ str r3, [r2]
+ ldr r3, =_port_switch_from_isr
+ str r3, [r1, #24]
+notrequired
+ pop {r4, pc}
+ nop
+ ENDP
+
+ END
diff --git a/os/ports/RVCT/ARMCMx/cstartup.s b/os/ports/RVCT/ARMCMx/cstartup.s
index 0d3a03f99..d0a8104a8 100644
--- a/os/ports/RVCT/ARMCMx/cstartup.s
+++ b/os/ports/RVCT/ARMCMx/cstartup.s
@@ -72,7 +72,8 @@ Reset_Handler PROC
msr CONTROL, r0
isb
bl __early_init
- b __main
+ ldr r0, =__main
+ bx r0
ENDP
__early_init PROC