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authorbarthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>2014-09-01 16:03:49 +0000
committerbarthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>2014-09-01 16:03:49 +0000
commitb637ebe63c2433e0015ec807f5e9ff8c2f2d49ba (patch)
tree1150893e13b4f2c53b1cfa89d8f150f2abce4273
parent3ebd86c26577c978dd2e64ebf9197c3c178a0f5a (diff)
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[STM32 FSMC] Updated board files for testhal.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7233 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat
-rw-r--r--os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h47
-rw-r--r--testhal/STM32/STM32F4xx/FSMC_NAND/main.c4
2 files changed, 25 insertions, 26 deletions
diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h
index 778392efd..e022ca986 100644
--- a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h
+++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h
@@ -73,7 +73,7 @@
#define GPIOB_PIN2 2
#define GPIOB_JTDO 3
#define GPIOB_JTRST 4
-#define GPIOB_PIN5 5
+#define GPIOB_NVRAM_PWR 5
#define GPIOB_PIN6 6
#define GPIOB_PIN7 7
#define GPIOB_PIN8 8
@@ -177,8 +177,8 @@
#define GPIOH_PIN4 4
#define GPIOH_PIN5 5
#define GPIOH_PIN6 6
-#define GPIOH_PIN7 7
-#define GPIOH_PIN8 8
+#define GPIOH_I2C3_SCL 7
+#define GPIOH_I2C3_SDA 8
#define GPIOH_PIN9 9
#define GPIOH_PIN10 10
#define GPIOH_PIN11 11
@@ -334,7 +334,7 @@
PIN_MODE_INPUT(GPIOB_PIN2) | \
PIN_MODE_ALTERNATE(GPIOB_JTDO) | \
PIN_MODE_ALTERNATE(GPIOB_JTRST) | \
- PIN_MODE_INPUT(GPIOB_PIN5) | \
+ PIN_MODE_OUTPUT(GPIOB_NVRAM_PWR) | \
PIN_MODE_INPUT(GPIOB_PIN6) | \
PIN_MODE_INPUT(GPIOB_PIN7) | \
PIN_MODE_INPUT(GPIOB_PIN8) | \
@@ -351,7 +351,7 @@
PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
PIN_OTYPE_PUSHPULL(GPIOB_JTDO) | \
PIN_OTYPE_PUSHPULL(GPIOB_JTRST) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
+ PIN_OTYPE_OPENDRAIN(GPIOB_NVRAM_PWR) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \
@@ -367,7 +367,7 @@
PIN_OSPEED_100M(GPIOB_PIN2) | \
PIN_OSPEED_100M(GPIOB_JTDO) | \
PIN_OSPEED_100M(GPIOB_JTRST) | \
- PIN_OSPEED_100M(GPIOB_PIN5) | \
+ PIN_OSPEED_2M(GPIOB_NVRAM_PWR) | \
PIN_OSPEED_100M(GPIOB_PIN6) | \
PIN_OSPEED_100M(GPIOB_PIN7) | \
PIN_OSPEED_100M(GPIOB_PIN8) | \
@@ -383,7 +383,7 @@
PIN_PUPDR_FLOATING(GPIOB_PIN2) | \
PIN_PUPDR_FLOATING(GPIOB_JTDO) | \
PIN_PUPDR_FLOATING(GPIOB_JTRST) | \
- PIN_PUPDR_FLOATING(GPIOB_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOB_NVRAM_PWR) | \
PIN_PUPDR_FLOATING(GPIOB_PIN6) | \
PIN_PUPDR_FLOATING(GPIOB_PIN7) | \
PIN_PUPDR_FLOATING(GPIOB_PIN8) | \
@@ -399,7 +399,7 @@
PIN_ODR_HIGH(GPIOB_PIN2) | \
PIN_ODR_HIGH(GPIOB_JTDO) | \
PIN_ODR_HIGH(GPIOB_JTRST) | \
- PIN_ODR_HIGH(GPIOB_PIN5) | \
+ PIN_ODR_LOW(GPIOB_NVRAM_PWR) | \
PIN_ODR_HIGH(GPIOB_PIN6) | \
PIN_ODR_HIGH(GPIOB_PIN7) | \
PIN_ODR_HIGH(GPIOB_PIN8) | \
@@ -415,7 +415,7 @@
PIN_AFIO_AF(GPIOB_PIN2, 0) | \
PIN_AFIO_AF(GPIOB_JTDO, 0) | \
PIN_AFIO_AF(GPIOB_JTRST, 0) | \
- PIN_AFIO_AF(GPIOB_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOB_NVRAM_PWR, 0) | \
PIN_AFIO_AF(GPIOB_PIN6, 0) | \
PIN_AFIO_AF(GPIOB_PIN7, 0))
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \
@@ -949,8 +949,8 @@
PIN_MODE_INPUT(GPIOH_PIN4) | \
PIN_MODE_INPUT(GPIOH_PIN5) | \
PIN_MODE_INPUT(GPIOH_PIN6) | \
- PIN_MODE_INPUT(GPIOH_PIN7) | \
- PIN_MODE_INPUT(GPIOH_PIN8) | \
+ PIN_MODE_ALTERNATE(GPIOH_I2C3_SCL) | \
+ PIN_MODE_ALTERNATE(GPIOH_I2C3_SDA) | \
PIN_MODE_INPUT(GPIOH_PIN9) | \
PIN_MODE_INPUT(GPIOH_PIN10) | \
PIN_MODE_INPUT(GPIOH_PIN11) | \
@@ -965,8 +965,8 @@
PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \
+ PIN_OTYPE_OPENDRAIN(GPIOH_I2C3_SCL) | \
+ PIN_OTYPE_OPENDRAIN(GPIOH_I2C3_SDA) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \
PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \
@@ -981,8 +981,8 @@
PIN_OSPEED_100M(GPIOH_PIN4) | \
PIN_OSPEED_100M(GPIOH_PIN5) | \
PIN_OSPEED_100M(GPIOH_PIN6) | \
- PIN_OSPEED_100M(GPIOH_PIN7) | \
- PIN_OSPEED_100M(GPIOH_PIN8) | \
+ PIN_OSPEED_2M(GPIOH_I2C3_SCL) | \
+ PIN_OSPEED_2M(GPIOH_I2C3_SDA) | \
PIN_OSPEED_100M(GPIOH_PIN9) | \
PIN_OSPEED_100M(GPIOH_PIN10) | \
PIN_OSPEED_100M(GPIOH_PIN11) | \
@@ -997,8 +997,8 @@
PIN_PUPDR_FLOATING(GPIOH_PIN4) | \
PIN_PUPDR_FLOATING(GPIOH_PIN5) | \
PIN_PUPDR_FLOATING(GPIOH_PIN6) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN7) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOH_I2C3_SCL) | \
+ PIN_PUPDR_FLOATING(GPIOH_I2C3_SDA) | \
PIN_PUPDR_FLOATING(GPIOH_PIN9) | \
PIN_PUPDR_FLOATING(GPIOH_PIN10) | \
PIN_PUPDR_FLOATING(GPIOH_PIN11) | \
@@ -1013,8 +1013,8 @@
PIN_ODR_HIGH(GPIOH_PIN4) | \
PIN_ODR_HIGH(GPIOH_PIN5) | \
PIN_ODR_HIGH(GPIOH_PIN6) | \
- PIN_ODR_HIGH(GPIOH_PIN7) | \
- PIN_ODR_HIGH(GPIOH_PIN8) | \
+ PIN_ODR_HIGH(GPIOH_I2C3_SCL) | \
+ PIN_ODR_HIGH(GPIOH_I2C3_SDA) | \
PIN_ODR_HIGH(GPIOH_PIN9) | \
PIN_ODR_HIGH(GPIOH_PIN10) | \
PIN_ODR_HIGH(GPIOH_PIN11) | \
@@ -1029,8 +1029,8 @@
PIN_AFIO_AF(GPIOH_PIN4, 0) | \
PIN_AFIO_AF(GPIOH_PIN5, 0) | \
PIN_AFIO_AF(GPIOH_PIN6, 0) | \
- PIN_AFIO_AF(GPIOH_PIN7, 0))
-#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOH_I2C3_SCL, 4))
+#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_I2C3_SDA, 4) | \
PIN_AFIO_AF(GPIOH_PIN9, 0) | \
PIN_AFIO_AF(GPIOH_PIN10, 0) | \
PIN_AFIO_AF(GPIOH_PIN11, 0) | \
@@ -1139,11 +1139,6 @@
PIN_AFIO_AF(GPIOI_PIN14, 0) | \
PIN_AFIO_AF(GPIOI_PIN15, 0))
-#define nand_wp_assert() palClearPad(GPIOB, GPIOB_NAND_WP)
-#define nand_wp_release() palSetPad(GPIOB, GPIOB_NAND_WP)
-#define red_led_on() palSetPad(GPIOI, GPIOI_LED_R)
-#define red_led_off() palClearPad(GPIOI, GPIOI_LED_R)
-
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {
diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/main.c b/testhal/STM32/STM32F4xx/FSMC_NAND/main.c
index 9067f1c8a..e69589443 100644
--- a/testhal/STM32/STM32F4xx/FSMC_NAND/main.c
+++ b/testhal/STM32/STM32F4xx/FSMC_NAND/main.c
@@ -198,6 +198,10 @@ static uint32_t KillCycle = 0;
******************************************************************************
******************************************************************************
*/
+static void nand_wp_assert(void) {palClearPad(GPIOB, GPIOB_NAND_WP);}
+static void nand_wp_release(void) {palSetPad(GPIOB, GPIOB_NAND_WP);}
+static void red_led_on(void) {palSetPad(GPIOI, GPIOI_LED_R);}
+static void red_led_off(void) {palClearPad(GPIOI, GPIOI_LED_R);}
#if STM32_NAND_USE_EXT_INT
static void nand_ready_cb(EXTDriver *extp, expchannel_t channel){
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-13 18:35:02 +0000