diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-01-15 08:01:07 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-01-15 08:01:07 +0000 |
| commit | ac6372224526c8de6f6a040d33e0309c501df73d (patch) | |
| tree | 38651d4002288a1b33e46f5b486d0ccc8d921162 | |
| parent | 8f86368f15cc28d4879a50ec8d4d6f8139e4d57a (diff) | |
| download | ChibiOS-ac6372224526c8de6f6a040d33e0309c501df73d.tar.gz ChibiOS-ac6372224526c8de6f6a040d33e0309c501df73d.tar.bz2 ChibiOS-ac6372224526c8de6f6a040d33e0309c501df73d.zip | |
Added OTG clock setting to the STM32 HAL.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2641 35acf78f-673a-0410-8e92-d51de3d6d3f4
| -rw-r--r-- | demos/ARMCM3-STM32F107-GCC/mcuconf.h | 1 | ||||
| -rw-r--r-- | os/hal/platforms/STM32/hal_lld.c | 9 | ||||
| -rw-r--r-- | os/hal/platforms/STM32/hal_lld.h | 14 | ||||
| -rw-r--r-- | os/hal/platforms/STM32/hal_lld_f105_f107.h | 18 | ||||
| -rw-r--r-- | readme.txt | 1 |
5 files changed, 34 insertions, 9 deletions
diff --git a/demos/ARMCM3-STM32F107-GCC/mcuconf.h b/demos/ARMCM3-STM32F107-GCC/mcuconf.h index a0374fc04..853707cc6 100644 --- a/demos/ARMCM3-STM32F107-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F107-GCC/mcuconf.h @@ -45,6 +45,7 @@ #define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_ADCPRE STM32_ADCPRE_DIV4
+#define STM32_OTGFSPRE STM32_OTGFSPRE_DIV3
#define STM32_MCO STM32_MCO_NOCLOCK
/*
diff --git a/os/hal/platforms/STM32/hal_lld.c b/os/hal/platforms/STM32/hal_lld.c index df99c3b53..97fbabcfc 100644 --- a/os/hal/platforms/STM32/hal_lld.c +++ b/os/hal/platforms/STM32/hal_lld.c @@ -180,8 +180,13 @@ void stm32_clock_init(void) { #endif
/* Clock settings.*/
- RCC->CFGR = STM32_MCO | STM32_PLLMUL | STM32_PLLSRC |
- STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
+#if STM32_HAS_OTG1
+ RCC->CFGR = STM32_MCO | STM32_OTGFSPRE | STM32_PLLMUL | STM32_PLLSRC |
+ STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
+#else
+ RCC->CFGR = STM32_MCO | STM32_PLLMUL | STM32_PLLSRC |
+ STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
+#endif
/* Flash setup and final clock selection. */
FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock. */
diff --git a/os/hal/platforms/STM32/hal_lld.h b/os/hal/platforms/STM32/hal_lld.h index 9cca9401f..0abac770c 100644 --- a/os/hal/platforms/STM32/hal_lld.h +++ b/os/hal/platforms/STM32/hal_lld.h @@ -125,7 +125,7 @@ #define STM32_HAS_UART4 FALSE
#define STM32_HAS_USB FALSE
-#define STM32_HAS_USBOTG FALSE
+#define STM32_HAS_OTG1 FALSE
#elif defined(STM32F10X_MD_VL)
/*
@@ -192,7 +192,7 @@ #define STM32_HAS_UART4 FALSE
#define STM32_HAS_USB FALSE
-#define STM32_HAS_USBOTG FALSE
+#define STM32_HAS_OTG1 FALSE
#elif defined(STM32F10X_LD)
/*
@@ -259,7 +259,7 @@ #define STM32_HAS_UART4 FALSE
#define STM32_HAS_USB FALSE
-#define STM32_HAS_USBOTG FALSE
+#define STM32_HAS_OTG1 FALSE
#elif defined(STM32F10X_MD)
/*
@@ -326,7 +326,7 @@ #define STM32_HAS_UART4 FALSE
#define STM32_HAS_USB TRUE
-#define STM32_HAS_USBOTG FALSE
+#define STM32_HAS_OTG1 FALSE
#elif defined(STM32F10X_HD)
/*
@@ -393,7 +393,7 @@ #define STM32_HAS_UART4 TRUE
#define STM32_HAS_USB TRUE
-#define STM32_HAS_USBOTG FALSE
+#define STM32_HAS_OTG1 FALSE
#elif defined(STM32F10X_XD)
/*
@@ -460,7 +460,7 @@ #define STM32_HAS_UART4 TRUE
#define STM32_HAS_USB TRUE
-#define STM32_HAS_USBOTG FALSE
+#define STM32_HAS_OTG1 FALSE
#elif defined(STM32F10X_CL)
/*
@@ -527,7 +527,7 @@ #define STM32_HAS_UART4 TRUE
#define STM32_HAS_USB FALSE
-#define STM32_HAS_USBOTG TRUE
+#define STM32_HAS_OTG1 TRUE
#else
#error "unspecified, unsupported or invalid STM32 platform"
diff --git a/os/hal/platforms/STM32/hal_lld_f105_f107.h b/os/hal/platforms/STM32/hal_lld_f105_f107.h index 8345917cc..d4477e705 100644 --- a/os/hal/platforms/STM32/hal_lld_f105_f107.h +++ b/os/hal/platforms/STM32/hal_lld_f105_f107.h @@ -277,6 +277,13 @@ #endif
/**
+ * @brief OTG prescaler initialization.
+ */
+#if !defined(STM32_OTGFSPRE) || defined(__DOXYGEN__)
+#define STM32_OTGFSPRE STM32_OTGFSPRE_DIV3
+#endif
+
+/**
* @brief MCO pin setting.
*/
#if !defined(STM32_MCO) || defined(__DOXYGEN__)
@@ -505,6 +512,17 @@ #endif
/**
+ * @brief OTG frequency.
+ */
+#if (STM32_OTGFSPRE == STM32_OTGFSPRE_DIV3) || defined(__DOXYGEN__)
+#define STM32_OTGFSCLK ((STM32_PLLCLKOUT * 2) / 3)
+#elif (STM32_OTGFSPRE == STM32_OTGFSPRE_DIV2)
+#define STM32_OTGFSCLK STM32_PLLCLKOUT
+#else
+#error "invalid STM32_OTGFSPRE value specified"
+#endif
+
+/**
* @brief Timers 2, 3, 4, 5, 6, 7 clock.
*/
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
diff --git a/readme.txt b/readme.txt index 0b009ddc0..87f958738 100644 --- a/readme.txt +++ b/readme.txt @@ -66,6 +66,7 @@ *** 2.1.8 ***
- FIX: Fixed STM32F103 demo's incorrect clock settings (bug 3153746).
+- NEW: Added OTG clock setting to the STM32 HAL.
*** 2.1.7 ***
- FIX: Fixed various errors in the HAL documentation (bug 3153591).
|