git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4835 35acf78f-673a-0410-8e92-d51de3d6d3f4

6 files changed, 43 insertions, 502 deletions

diff --git a/docs/reports/SPC560B50-64.txt b/docs/reports/SPC560B50-64.txt
index 877340f6b..ce05e6b3c 100644
--- a/docs/reports/SPC560B50-64.txt
+++ b/docs/reports/SPC560B50-64.txt
@@ -6,7 +6,7 @@ Settings: SYSCLK=64
 *** ChibiOS/RT test suite

 ***

 *** Kernel:       2.5.1unstable

-*** Compiled:     Nov 20 2012 - 16:19:08

+*** Compiled:     Nov 21 2012 - 11:53:56

 *** Compiler:     GCC 4.5.2 (build: 2011.11)  build on 2011-11-30 Tool Version v1.4

 *** Architecture: Power Architecture

 *** Core Variant: e200z0

@@ -100,23 +100,23 @@ Settings: SYSCLK=64
 --- Result: SUCCESS

 ----------------------------------------------------------------------------

 --- Test Case 11.1 (Benchmark, messages #1)

---- Score : 199448 msgs/S, 398896 ctxswc/S

+--- Score : 199440 msgs/S, 398880 ctxswc/S

 --- Result: SUCCESS

 ----------------------------------------------------------------------------

 --- Test Case 11.2 (Benchmark, messages #2)

---- Score : 167946 msgs/S, 335892 ctxswc/S

+--- Score : 167943 msgs/S, 335886 ctxswc/S

 --- Result: SUCCESS

 ----------------------------------------------------------------------------

 --- Test Case 11.3 (Benchmark, messages #3)

---- Score : 167945 msgs/S, 335890 ctxswc/S

+--- Score : 167942 msgs/S, 335884 ctxswc/S

 --- Result: SUCCESS

 ----------------------------------------------------------------------------

 --- Test Case 11.4 (Benchmark, context switch)

---- Score : 582216 ctxswc/S

+--- Score : 582232 ctxswc/S

 --- Result: SUCCESS

 ----------------------------------------------------------------------------

 --- Test Case 11.5 (Benchmark, threads, full cycle)

---- Score : 133232 threads/S

+--- Score : 133234 threads/S

 --- Result: SUCCESS

 ----------------------------------------------------------------------------

 --- Test Case 11.6 (Benchmark, threads, create only)

@@ -124,7 +124,7 @@ Settings: SYSCLK=64
 --- Result: SUCCESS

 ----------------------------------------------------------------------------

 --- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)

---- Score : 51758 reschedules/S, 310548 ctxswc/S

+--- Score : 51926 reschedules/S, 311556 ctxswc/S

 --- Result: SUCCESS

 ----------------------------------------------------------------------------

 --- Test Case 11.8 (Benchmark, round robin context switching)

@@ -132,19 +132,19 @@ Settings: SYSCLK=64
 --- Result: SUCCESS

 ----------------------------------------------------------------------------

 --- Test Case 11.9 (Benchmark, I/O Queues throughput)

---- Score : 593352 bytes/S

+--- Score : 593368 bytes/S

 --- Result: SUCCESS

 ----------------------------------------------------------------------------

 --- Test Case 11.10 (Benchmark, virtual timers set/reset)

---- Score : 813014 timers/S

+--- Score : 818254 timers/S

 --- Result: SUCCESS

 ----------------------------------------------------------------------------

 --- Test Case 11.11 (Benchmark, semaphores wait/signal)

---- Score : 818228 wait+signal/S

+--- Score : 818264 wait+signal/S

 --- Result: SUCCESS

 ----------------------------------------------------------------------------

 --- Test Case 11.12 (Benchmark, mutexes lock/unlock)

---- Score : 643056 lock+unlock/S

+--- Score : 643064 lock+unlock/S

 --- Result: SUCCESS

 ----------------------------------------------------------------------------

 --- Test Case 11.13 (Benchmark, RAM footprint)

diff --git a/os/hal/platforms/SPC560BCxx/hal_lld.c b/os/hal/platforms/SPC560BCxx/hal_lld.c
index b7e157dc5..0be4cfb57 100644
--- a/os/hal/platforms/SPC560BCxx/hal_lld.c
+++ b/os/hal/platforms/SPC560BCxx/hal_lld.c
@@ -176,6 +176,9 @@ void spc_clock_init(void) {
   CFLASH.PFCR1.B.BK1_APC  = 2;

   CFLASH.PFCR1.B.BK1_RWSC = 2;

 

+  /* Initialization of e200z0 special registers.*/

+  port_mtspr(1013, 0x00000001);         /* BPEN=1.                          */

+

 #endif /* !SPC5_NO_INIT */

 }

 

diff --git a/os/hal/platforms/SPC560BCxx/spc560bc_registry.h b/os/hal/platforms/SPC560BCxx/spc560bc_registry.h
index 6fe68be87..92158b107 100644
--- a/os/hal/platforms/SPC560BCxx/spc560bc_registry.h
+++ b/os/hal/platforms/SPC560BCxx/spc560bc_registry.h
@@ -81,6 +81,7 @@
 #define SPC5_SIU_NUM_PORTS                  8

 #define SPC5_SIU_NUM_PCRS                   123

 #define SPC5_SIU_NUM_PADSELS                32

+#define SPC5_SIU_SYSTEM_PINS                32,33,121,122

 /** @} */

 

 #endif /* _SPC560BC_REGISTRY_H_ */

diff --git a/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c b/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c
index e098391ce..ec0b576e9 100644
--- a/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c
+++ b/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c
@@ -43,6 +43,10 @@
 /* Driver local variables.                                                   */

 /*===========================================================================*/

 

+#if defined(SPC5_SIU_SYSTEM_PINS)

+static const unsigned system_pins[] = {SPC5_SIU_SYSTEM_PINS};

+#endif

+

 /*===========================================================================*/

 /* Driver local functions.                                                   */

 /*===========================================================================*/

@@ -72,8 +76,22 @@ void _pal_lld_init(const PALConfig *config) {
 #endif

 

   /* Initialize PCR registers for undefined pads.*/

-  for (i = 0; i < SPC5_SIU_NUM_PCRS; i++)

+  for (i = 0; i < SPC5_SIU_NUM_PCRS; i++) {

+#if defined(SPC5_SIU_SYSTEM_PINS)

+    /* Handling the case where some SIU pins are not meant to be reprogrammed,

+       for example JTAG pins.*/

+    unsigned j;

+    for (j = 0; j < sizeof system_pins; j++) {

+      if (i == system_pins[j])

+        goto skip;

+    }

+    SIU.PCR[i].R = config->default_mode;

+skip:

+    ;

+#else

     SIU.PCR[i].R = config->default_mode;

+#endif

+  }

 

   /* Initialize PADSEL registers.*/

   for (i = 0; i < SPC5_SIU_NUM_PADSELS; i++)

diff --git a/os/ports/GCC/PPC/chcore.h b/os/ports/GCC/PPC/chcore.h
index 0a4476ea4..4fd1cd300 100644
--- a/os/ports/GCC/PPC/chcore.h
+++ b/os/ports/GCC/PPC/chcore.h
@@ -345,6 +345,15 @@ struct context {
 #define port_enable() asm volatile ("wrteei  1" : : : "memory")

 

 /**

+ * @brief   Writes to a special register.

+ *

+ * @param[in] spr       special register number

+ * @param[in] val       value to be written

+ */

+#define port_mtspr(spr, val)                                                \

+  asm volatile ("mtspr %0,%1" : : "n" (spr), "r" (val))

+

+/**

  * @details This port function is implemented as inlined code for performance

  *          reasons.

  */

diff --git a/os/ports/common/PPC/spr_z0h.h b/os/ports/common/PPC/spr_z0h.h
deleted file mode 100644
index f6fdbae00..000000000
--- a/os/ports/common/PPC/spr_z0h.h
+++ /dev/null
@@ -1,490 +0,0 @@
-/***************************************************************** 

- * PROJECT     : MPC560xB, MPC560xP & MPC560xS

- *               SPC560xB, SPC560xP & SPC560xS 

- * FILE        : jdp_spr_z0h.h 

- * 

- * DESCRIPTION : This file defines the Z0H core registers for the 

- *               named projects. 

- * 

- * COPYRIGHT   :(c) 2008, Freescale & STMicroelectronics 

- * 

- * VERSION     : 0.1 

- * DATE        : 02.21.2008 

- * AUTHOR      : b04629 

- * HISTORY     :  

- ******************************************************************/

-

-/* >>>NOTE! This file describes fixed special purpose registers.  */

-/*          Please do not edit it directly!<<<<                   */

-

-#ifndef _JDP_SPR_Z0_

-#define _JDP_SPR_Z0_

-/* This ifndef has a corresponding #endif at the bottom of this   */

-/* file so that it will only be included once.                    */

-

-#include "typedefs.h"

-

-#ifdef  __cplusplus

-extern "C" {

-#endif

-

-/***************************************************************** 

-* Example instantiation and use:

-*  union CRVAL my_cr;           

-*  my_cr.B.CR0 = 1;             

-*  my_cr.R = 0x10000000         

-******************************************************************/

-

-

-

-/***************************************************************** 

-* CPU REGISTERS: General Registers

-******************************************************************/

-        union SPR_CRVAL { 

-            vuint32_t R;

-            struct {

-                vuint32_t CR0:4;

-                vuint32_t CR1:4;

-                vuint32_t CR2:4;

-                vuint32_t CR3:4;

-                vuint32_t CR4:4;

-                vuint32_t CR5:4;

-                vuint32_t CR6:4;

-                vuint32_t CR7:4;

-            } B;

-        };

-

-        union SPR_LRVAL { 

-            vuint32_t R;

-            struct {

-                vuint32_t LINKADDRESS:32;

-            } B;

-        };

-

-        union SPR_CTRVAL {

-            vuint32_t R;

-            struct {

-                vuint32_t COUNTVALUE:32;

-            } B;

-        };

-

-        union SPR_XERVAL {   

-            vuint32_t R;

-            struct {

-                vuint32_t SO:1;

-                vuint32_t OV:1;

-                vuint32_t CA:1;

-                vuint32_t :22;

-                vuint32_t BYTECNT:7;

-            } B;

-        };

-

-/*****************************************************************  

-* CPU REGISTERS: Processor Control Registers                                  

-******************************************************************/ 

-        union SPR_MSRVAL {  

-            vuint32_t R;

-            struct {

-                vuint32_t :5;

-                vuint32_t UCLE:1;

-                vuint32_t :7;

-                vuint32_t WE:1;

-                vuint32_t CE:1;

-                vuint32_t :1;

-                vuint32_t EE:1;

-                vuint32_t PR:1;

-                vuint32_t FP:1;

-                vuint32_t ME:1;

-                vuint32_t FE0:1;

-                vuint32_t :1;

-                vuint32_t DE:1;

-                vuint32_t FE1:1;

-                vuint32_t :2;

-                vuint32_t IS:1;

-                vuint32_t DS:1;

-                vuint32_t :2;

-                vuint32_t RI:1;

-                vuint32_t :1;

-            } B;

-        };

-

-        union SPR_PIRVAL {   

-            vuint32_t R;

-            struct {

-                vuint32_t :24;

-                vuint32_t ID:8;

-            } B;

-        };

-

-        union SPR_PVRVAL {   

-            vuint32_t R;

-            struct {

-                vuint32_t :12;

-                vuint32_t VER:4;

-                vuint32_t MGBUSE:8;

-                vuint32_t MJRREV:4;

-                vuint32_t MGBID:4;

-            } B;

-        };

-

-         union SPR_SVRVAL {   

-            vuint32_t R;

-            struct {

-                vuint32_t SYSVER:32;

-            } B;

-        };

-

-        union SPR_HID0VAL {  

-            vuint32_t R;

-            struct {

-                vuint32_t EMCP:1;

-                vuint32_t :5;

-                vuint32_t BPRED:2;

-                vuint32_t DOZE:1;

-                vuint32_t NAP:1;

-                vuint32_t SLEEP:1;

-                vuint32_t :3;

-                vuint32_t ICR:1;

-                vuint32_t NHR:1;

-                vuint32_t :1;

-                vuint32_t TBEN:1;

-                vuint32_t SEL_TBCLK:1;

-                vuint32_t DCLREE:1;

-                vuint32_t DCLRCE:1;

-                vuint32_t CICLRDE:1;

-                vuint32_t MCCLRDE:1;

-                vuint32_t DAPUEN:1;

-                vuint32_t :8;

-            } B;

-        };

-

-        union SPR_HID1VAL {  

-            vuint32_t R;

-            struct {

-                vuint32_t :16;

-                vuint32_t SYSCTL:8;

-                vuint32_t ATS:1;

-                vuint32_t :7;

-            } B;

-        };

-

-        union SPR_BUCSRVAL {  

-            vuint32_t R;

-            struct {

-                vuint32_t :22;

-                vuint32_t BBFI:1;

-                vuint32_t :8;

-                vuint32_t BPEN:1;

-            } B;

-        };        

-        

-/***************************************************************** 

-* CPU REGISTERS: Exception Handling/Control Registers

-******************************************************************/

-        union SPR_SPRGVAL {  /* There are [2] entries for this tag */

-            vuint32_t R;

-            struct {

-                vuint32_t SPRDATA:32;

-            } B;

-        };

-

-       union SPR_SRR0VAL { 

-            vuint32_t R;

-            struct {

-                vuint32_t NXTADDR:32;

-            } B;

-        };

-

-       union SPR_SRR1VAL { 

-            vuint32_t R;

-            struct {

-                vuint32_t MSRSTATE:32;

-            } B;

-        };

-

-        union SPR_CSRR0VAL { 

-            vuint32_t R;

-            struct {

-                vuint32_t CRITNXTADDR:32;

-            } B;

-        };

-

-       union SPR_CSRR1VAL { 

-            vuint32_t R;

-            struct {

-                vuint32_t CRITMSRSTATE:32;

-            } B;

-        };

-

-        union SPR_DSRR0VAL { 

-            vuint32_t R;

-            struct {

-                vuint32_t DBGNXTADDR:32;

-            } B;

-        };

-

-       union SPR_DSRR1VAL { 

-            vuint32_t R;

-            struct {

-                vuint32_t DBGMSRSTATE:32;

-            } B;

-        };

-

-       union SPR_DEARVAL { 

-            vuint32_t R;

-            struct {

-                vuint32_t DATEFADDR:16;

-                vuint32_t :16;

-            } B;

-        };

-

-        union SPR_ESRVAL { 

-            vuint32_t R;

-            struct {

-                vuint32_t :4;

-                vuint32_t PIL:1;

-                vuint32_t PPR:1;

-                vuint32_t PTR:1;

-                vuint32_t FP:1;

-                vuint32_t ST:1;

-                vuint32_t :1;

-                vuint32_t DLK:1;

-                vuint32_t ILK:1;

-                vuint32_t AP:1;

-                vuint32_t PUO:1;

-                vuint32_t BO:1;

-                vuint32_t PIE:1;

-                vuint32_t :8;

-                vuint32_t EFP:1;

-                vuint32_t :1;

-                vuint32_t VLEMI:1;

-                vuint32_t :3;

-                vuint32_t MIF:1;

-                vuint32_t XTE:1;

-            } B;

-        };

-

-

-        union SPR_MCSRVAL {  

-            vuint32_t R;

-            struct {

-                vuint32_t MCP:1;

-                vuint32_t :1;

-                vuint32_t CP_PERR:1;

-                vuint32_t CPERR:1;

-                vuint32_t EXCP_ERR:1;

-                vuint32_t :6;

-                vuint32_t NMI:1;

-                vuint32_t :15;

-                vuint32_t BUS_IRERR:1;

-                vuint32_t BUS_DRERR:1;

-                vuint32_t BUS_WRERR:1;

-                vuint32_t :2;

-            } B;

-        };

-

-       union SPR_IVPRVAL { 

-            vuint32_t R;

-            struct {

-                vuint32_t VECBASE:20;

-                vuint32_t :12;

-            } B;

-        };

-

-/***************************************************************** 

-* CPU REGISTERS: DEBUG

-******************************************************************/

-        union SPR_DBCR0VAL {

-            vuint32_t R;

-            struct { 

-                vuint32_t EDM:1;

-                vuint32_t IDM:1;

-                vuint32_t RST:2;

-                vuint32_t ICMP:1;

-                vuint32_t BRT:1;

-                vuint32_t IRPT:1;

-                vuint32_t TRAP:1;

-                vuint32_t IAC1:1;

-                vuint32_t IAC2:1;

-                vuint32_t IAC3:1;

-                vuint32_t IAC4:1;

-                vuint32_t DAC1:2;

-                vuint32_t DAC2:2;

-                vuint32_t RET:1;

-                vuint32_t :4;

-                vuint32_t DEVT1:1;

-                vuint32_t DEVT2:1;

-                vuint32_t :2;

-                vuint32_t CIRPT:1;

-                vuint32_t CRET:1;

-                vuint32_t :5;

-            } B;

-        };

-

-        union SPR_DBCR1VAL { 

-            vuint32_t R;

-            struct {

-                vuint32_t IAC1US:2;

-                vuint32_t IAC1ER:2;

-                vuint32_t IAC2US:2;

-                vuint32_t IAC2ER:2;

-                vuint32_t IAC12M:2;

-                vuint32_t :6;

-                vuint32_t IAC3US:2;

-                vuint32_t IAC3ER:2;

-                vuint32_t IAC4US:2;

-                vuint32_t IAC4ER:2;

-                vuint32_t IAC34M:2;

-                vuint32_t :6;

-            } B;

-        };

-

-        union SPR_DBCR2VAL { 

-            vuint32_t R;

-            struct {

-                vuint32_t DAC1US:2;

-                vuint32_t DAC1ER:2;

-                vuint32_t DAC2US:2;

-                vuint32_t DAC2ER:2;

-                vuint32_t DAC12M:2;

-                vuint32_t DAC1LNK:2;

-                vuint32_t DAC2LNK:2;

-                vuint32_t :20;

-            } B;

-        };

-

-        union SPR_DBSRVAL {  

-            vuint32_t R;

-            struct {

-                vuint32_t IDE:1;

-                vuint32_t UDE:1;

-                vuint32_t MRR:2;

-                vuint32_t ICMP:1;

-                vuint32_t BRT:1;

-                vuint32_t IRPT:1;

-                vuint32_t TRAP:1;

-                vuint32_t IAC1:1;

-                vuint32_t IAC2:1;

-                vuint32_t IAC3:1;

-                vuint32_t IAC4:1;

-                vuint32_t DAC1R:1;

-                vuint32_t DAC1W:1;

-                vuint32_t DAC2R:1;

-                vuint32_t DAC2W:1;

-                vuint32_t RET:1;

-                vuint32_t :4;

-                vuint32_t DEVT1:1;

-                vuint32_t DEVT2:1;

-                vuint32_t :2;

-                vuint32_t CIRPT:1;

-                vuint32_t CRET:1;

-                vuint32_t VLES:1; 

-                vuint32_t :4;

-            } B;

-        };

-

-        union SPR_IAC1VAL {

-            vuint32_t R;

-            struct {

-                vuint32_t INSTADDR:30;

-                vuint32_t :2;

-           } B;

-        };

-

-        union SPR_IAC2VAL {

-            vuint32_t R;

-            struct {

-                vuint32_t INSTADDR:30;

-                vuint32_t :2;

-           } B;

-        };

-

-        union SPR_IAC3VAL {

-            vuint32_t R;

-            struct {

-                vuint32_t INSTADDR:30;

-                vuint32_t :2;

-           } B;

-        };

-

-        union SPR_IAC4VAL {

-            vuint32_t R;

-            struct {

-                vuint32_t INSTADDR:30;

-                vuint32_t :2;

-           } B;

-        };

-

-

-        union SPR_DAC1VAL {

-            vuint32_t R;

-            struct {

-                vuint32_t DATTADDR:32;

-           } B;

-        };

-

-        union SPR_DAC2VAL {

-            vuint32_t R;

-            struct {

-                vuint32_t DATTADDR:32;

-           } B;

-        };

-

-

-/***************************************************************** 

-* Define instances of modules with special register numbers

-******************************************************************/

-/* The CR register does not have an SPR#  */

-/* The GPR registers do not have an SPR#  */

-/* The MSR register does not have an SPR# */

-

-#define SPR_LR          8

-#define SPR_CTR         9

-#define SPR_XER         1

-

-#define SPR_PIR       286

-#define SPR_PVR       287

-#define SPR_SVR      1023

-#define SPR_HID0     1008

-#define SPR_HID1     1009

-

-#define SPR_PID0       48

-#define SPR_MMUCFG   1015

-

-#define SPR_L1CFG0    515

-

-#define SPR_SPRG0     272

-#define SPR_SPRG1     273

-#define SPR_SRR0       26

-#define SPR_SRR1       27

-#define SPR_CSRR0      58

-#define SPR_CSRR1      59

-#define SPR_DSRR0     574

-#define SPR_DSRR1     575

-#define SPR_ESR        62

-#define SPR_MCSR      572

-#define SPR_DEAR       61

-#define SPR_IVPR       63

-

-#define SPR_DBCR0     308

-#define SPR_DBCR1     309

-#define SPR_DBCR2     310

-#define SPR_DBSR      304

-#define SPR_IAC1      312

-#define SPR_IAC2      313

-#define SPR_IAC3      314

-#define SPR_IAC4      315

-#define SPR_DAC1      316

-#define SPR_DAC2      317

-

-#define SPR_BUCSR    1013 

-

-

-

-#ifdef  __cplusplus

-}

-#endif

-

-#endif  /* ends inclusion of #ifndef _JDP_SPR_Z0_ for one instantiation */

-

-/* End of file */