diff options
| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-10-22 12:32:43 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-10-22 12:32:43 +0000 |
| commit | 51e94075b0fd08e41765ff379cdd011f181550da (patch) | |
| tree | 67d09e17f8431d971cf3a9392a51779a32a0f6bc | |
| parent | c499423d9c87fe2ef3c5b9a0cd11aeb871a9701e (diff) | |
| download | ChibiOS-51e94075b0fd08e41765ff379cdd011f181550da.tar.gz ChibiOS-51e94075b0fd08e41765ff379cdd011f181550da.tar.bz2 ChibiOS-51e94075b0fd08e41765ff379cdd011f181550da.zip | |
STM32F091RC Nucleo demo added.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8377 35acf78f-673a-0410-8e92-d51de3d6d3f4
| -rw-r--r-- | demos/STM32/RT-STM32F091RC-NUCLEO/.cproject | 52 | ||||
| -rw-r--r-- | demos/STM32/RT-STM32F091RC-NUCLEO/.project | 43 | ||||
| -rw-r--r-- | demos/STM32/RT-STM32F091RC-NUCLEO/Makefile | 211 | ||||
| -rw-r--r-- | demos/STM32/RT-STM32F091RC-NUCLEO/chconf.h | 499 | ||||
| -rw-r--r-- | demos/STM32/RT-STM32F091RC-NUCLEO/debug/RT-STM32F091RC-NUCLEO (OpenOCD, Flash and Run).launch | 52 | ||||
| -rw-r--r-- | demos/STM32/RT-STM32F091RC-NUCLEO/halconf.h | 334 | ||||
| -rw-r--r-- | demos/STM32/RT-STM32F091RC-NUCLEO/main.c | 71 | ||||
| -rw-r--r-- | demos/STM32/RT-STM32F091RC-NUCLEO/mcuconf.h | 165 | ||||
| -rw-r--r-- | demos/STM32/RT-STM32F091RC-NUCLEO/readme.txt | 28 | ||||
| -rw-r--r-- | os/common/ports/ARMCMx/compilers/GCC/ld/STM32F091xC.ld | 53 | ||||
| -rw-r--r-- | os/hal/boards/ST_NUCLEO_F091RC/board.c | 102 | ||||
| -rw-r--r-- | os/hal/boards/ST_NUCLEO_F091RC/board.h | 889 | ||||
| -rw-r--r-- | os/hal/boards/ST_NUCLEO_F091RC/board.mk | 5 | ||||
| -rw-r--r-- | os/hal/boards/ST_NUCLEO_F091RC/cfg/board.chcfg | 799 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F0xx/hal_lld.h | 4 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F0xx/stm32_registry.h | 4 |
16 files changed, 3307 insertions, 4 deletions
diff --git a/demos/STM32/RT-STM32F091RC-NUCLEO/.cproject b/demos/STM32/RT-STM32F091RC-NUCLEO/.cproject new file mode 100644 index 000000000..b64046319 --- /dev/null +++ b/demos/STM32/RT-STM32F091RC-NUCLEO/.cproject @@ -0,0 +1,52 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+ <storageModule moduleId="org.eclipse.cdt.core.settings">
+ <cconfiguration id="0.2077824274">
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="0.2077824274" moduleId="org.eclipse.cdt.core.settings" name="Default">
+ <externalSettings/>
+ <extensions>
+ <extension id="org.eclipse.cdt.core.VCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ </extensions>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <configuration artifactName="${ProjName}" buildProperties="" description="" id="0.2077824274" name="Default" parent="org.eclipse.cdt.build.core.prefbase.cfg">
+ <folderInfo id="0.2077824274." name="/" resourcePath="">
+ <toolChain id="org.eclipse.cdt.build.core.prefbase.toolchain.203229382" name="No ToolChain" resourceTypeBasedDiscovery="false" superClass="org.eclipse.cdt.build.core.prefbase.toolchain">
+ <targetPlatform id="org.eclipse.cdt.build.core.prefbase.toolchain.203229382.921093738" name=""/>
+ <builder autoBuildTarget="all" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="org.eclipse.cdt.build.core.settings.default.builder.1981534797" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.settings.default.builder"/>
+ <tool id="org.eclipse.cdt.build.core.settings.holder.libs.1014159428" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/>
+ <tool id="org.eclipse.cdt.build.core.settings.holder.1125060063" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder">
+ <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.501348595" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+ </tool>
+ <tool id="org.eclipse.cdt.build.core.settings.holder.524434484" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder">
+ <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1642681620" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+ </tool>
+ <tool id="org.eclipse.cdt.build.core.settings.holder.698212794" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder">
+ <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.243558710" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+ </tool>
+ </toolChain>
+ </folderInfo>
+ </configuration>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+ </cconfiguration>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <project id="RT-STM32F091RC-NUCLEO.null.1777534423" name="RT-STM32F091RC-NUCLEO"/>
+ </storageModule>
+ <storageModule moduleId="scannerConfiguration">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ <scannerConfigBuildInfo instanceId="0.2077824274">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/>
+ </scannerConfigBuildInfo>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+ <storageModule moduleId="refreshScope"/>
+</cproject>
diff --git a/demos/STM32/RT-STM32F091RC-NUCLEO/.project b/demos/STM32/RT-STM32F091RC-NUCLEO/.project new file mode 100644 index 000000000..cf2af0cfb --- /dev/null +++ b/demos/STM32/RT-STM32F091RC-NUCLEO/.project @@ -0,0 +1,43 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>RT-STM32F091RC-NUCLEO</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <triggers>clean,full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+ <triggers>full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+ </natures>
+ <linkedResources>
+ <link>
+ <name>board</name>
+ <type>2</type>
+ <locationURI>CHIBIOS/os/hal/boards/ST_NUCLEO_F091RC</locationURI>
+ </link>
+ <link>
+ <name>os</name>
+ <type>2</type>
+ <locationURI>CHIBIOS/os</locationURI>
+ </link>
+ <link>
+ <name>test</name>
+ <type>2</type>
+ <locationURI>CHIBIOS/test</locationURI>
+ </link>
+ </linkedResources>
+</projectDescription>
diff --git a/demos/STM32/RT-STM32F091RC-NUCLEO/Makefile b/demos/STM32/RT-STM32F091RC-NUCLEO/Makefile new file mode 100644 index 000000000..71e404723 --- /dev/null +++ b/demos/STM32/RT-STM32F091RC-NUCLEO/Makefile @@ -0,0 +1,211 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+ USE_LTO = yes
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+# If enabled, this option makes the build process faster by not compiling
+# modules not used in the current configuration.
+ifeq ($(USE_SMART_BUILD),)
+ USE_SMART_BUILD = yes
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the Cortex-M process stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ USE_PROCESS_STACKSIZE = 0x200
+endif
+
+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
+# stack is used for processing interrupts and exceptions.
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ USE_EXCEPTIONS_STACKSIZE = 0x400
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../../..
+# Startup files.
+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f0xx.mk
+# HAL-OSAL files (optional).
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/platform.mk
+include $(CHIBIOS)/os/hal/boards/ST_NUCLEO_F091RC/board.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+# RTOS files (optional).
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk
+# Other files (optional).
+include $(CHIBIOS)/test/rt/test.mk
+
+# Define linker script file here
+LDSCRIPT= $(STARTUPLD)/STM32F091xC.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(STARTUPSRC) \
+ $(KERNSRC) \
+ $(PORTSRC) \
+ $(OSALSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ $(TESTSRC) \
+ main.c
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
+
+INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
+ $(CHIBIOS)/os/various
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = cortex-m0
+
+#TRGT = arm-elf-
+TRGT = arm-none-eabi-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+AR = $(TRGT)ar
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra -Wundef
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC
+include $(RULESPATH)/rules.mk
diff --git a/demos/STM32/RT-STM32F091RC-NUCLEO/chconf.h b/demos/STM32/RT-STM32F091RC-NUCLEO/chconf.h new file mode 100644 index 000000000..3efdfc677 --- /dev/null +++ b/demos/STM32/RT-STM32F091RC-NUCLEO/chconf.h @@ -0,0 +1,499 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/chconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 16
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 2
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 0
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM FALSE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_QUEUES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK FALSE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS FALSE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS FALSE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE FALSE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK FALSE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS FALSE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/demos/STM32/RT-STM32F091RC-NUCLEO/debug/RT-STM32F091RC-NUCLEO (OpenOCD, Flash and Run).launch b/demos/STM32/RT-STM32F091RC-NUCLEO/debug/RT-STM32F091RC-NUCLEO (OpenOCD, Flash and Run).launch new file mode 100644 index 000000000..0a8beb859 --- /dev/null +++ b/demos/STM32/RT-STM32F091RC-NUCLEO/debug/RT-STM32F091RC-NUCLEO (OpenOCD, Flash and Run).launch @@ -0,0 +1,52 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="org.eclipse.cdt.debug.gdbjtag.launchConfigurationType">
+<stringAttribute key="bad_container_name" value="\RT-STM32F030R8-NUCLEO\debug"/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="1"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="set remotetimeout 20 monitor reset init monitor sleep 50 "/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="Generic TCP/IP"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="arm-none-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><contentList/>"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <globalVariableList/> "/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList/> "/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="RT-STM32F030R8-NUCLEO"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="0.1984968159"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/RT-STM32F030R8-NUCLEO"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.ui.favoriteGroups">
+<listEntry value="org.eclipse.debug.ui.launchGroup.debug"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/demos/STM32/RT-STM32F091RC-NUCLEO/halconf.h b/demos/STM32/RT-STM32F091RC-NUCLEO/halconf.h new file mode 100644 index 000000000..3e61eeaf9 --- /dev/null +++ b/demos/STM32/RT-STM32F091RC-NUCLEO/halconf.h @@ -0,0 +1,334 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL TRUE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/demos/STM32/RT-STM32F091RC-NUCLEO/main.c b/demos/STM32/RT-STM32F091RC-NUCLEO/main.c new file mode 100644 index 000000000..bd50f191d --- /dev/null +++ b/demos/STM32/RT-STM32F091RC-NUCLEO/main.c @@ -0,0 +1,71 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+#include "test.h"
+
+/*
+ * Red LED blinker thread, times are in milliseconds.
+ */
+static THD_WORKING_AREA(waThread1, 128);
+static THD_FUNCTION(Thread1, arg) {
+
+ (void)arg;
+ chRegSetThreadName("blinker");
+ while (true) {
+ palClearPad(GPIOA, GPIOA_LED_GREEN);
+ chThdSleepMilliseconds(500);
+ palSetPad(GPIOA, GPIOA_LED_GREEN);
+ chThdSleepMilliseconds(500);
+ }
+}
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * Activates the serial driver 2 using the driver default configuration.
+ */
+ sdStart(&SD2, NULL);
+
+ /*
+ * Creates the blinker thread.
+ */
+ chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
+
+ /*
+ * Normal main() thread activity, in this demo it does nothing except
+ * sleeping in a loop and check the button state.
+ */
+ while (true) {
+ if (!palReadPad(GPIOC, GPIOC_BUTTON))
+ TestThread(&SD2);
+ chThdSleepMilliseconds(500);
+ }
+}
diff --git a/demos/STM32/RT-STM32F091RC-NUCLEO/mcuconf.h b/demos/STM32/RT-STM32F091RC-NUCLEO/mcuconf.h new file mode 100644 index 000000000..73a87484f --- /dev/null +++ b/demos/STM32/RT-STM32F091RC-NUCLEO/mcuconf.h @@ -0,0 +1,165 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+/*
+ * STM32F0xx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 3...0 Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3 Lowest...Highest.
+ */
+
+#define STM32F0xx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define STM32_NO_INIT FALSE
+#define STM32_PVD_ENABLE FALSE
+#define STM32_PLS STM32_PLS_LEV0
+#define STM32_HSI_ENABLED TRUE
+#define STM32_HSI14_ENABLED TRUE
+#define STM32_LSI_ENABLED TRUE
+#define STM32_HSE_ENABLED FALSE
+#define STM32_LSE_ENABLED FALSE
+#define STM32_SW STM32_SW_PLL
+#define STM32_PLLSRC STM32_PLLSRC_HSI_DIV2
+#define STM32_PREDIV_VALUE 1
+#define STM32_PLLMUL_VALUE 12
+#define STM32_HPRE STM32_HPRE_DIV1
+#define STM32_PPRE STM32_PPRE_DIV1
+#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
+#define STM32_CECSW STM32_CECSW_HSI
+#define STM32_I2C1SW STM32_I2C1SW_HSI
+#define STM32_USART1SW STM32_USART1SW_PCLK
+#define STM32_RTCSEL STM32_RTCSEL_LSI
+
+/*
+ * ADC driver system settings.
+ */
+#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+
+/*
+ * EXT driver system settings.
+ */
+#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3
+#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3
+#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3
+#define STM32_EXT_EXTI16_IRQ_PRIORITY 3
+#define STM32_EXT_EXTI17_20_IRQ_PRIORITY 3
+
+/*
+ * GPT driver system settings.
+ */
+#define STM32_GPT_USE_TIM1 FALSE
+#define STM32_GPT_USE_TIM3 FALSE
+#define STM32_GPT_USE_TIM14 FALSE
+#define STM32_GPT_TIM1_IRQ_PRIORITY 2
+#define STM32_GPT_TIM3_IRQ_PRIORITY 2
+#define STM32_GPT_TIM14_IRQ_PRIORITY 2
+
+/*
+ * I2C driver system settings.
+ */
+#define STM32_I2C_USE_I2C1 FALSE
+#define STM32_I2C_USE_I2C2 FALSE
+#define STM32_I2C_BUSY_TIMEOUT 50
+#define STM32_I2C_I2C1_IRQ_PRIORITY 3
+#define STM32_I2C_I2C2_IRQ_PRIORITY 3
+#define STM32_I2C_USE_DMA TRUE
+#define STM32_I2C_I2C1_DMA_PRIORITY 1
+#define STM32_I2C_I2C2_DMA_PRIORITY 1
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
+
+/*
+ * ICU driver system settings.
+ */
+#define STM32_ICU_USE_TIM1 FALSE
+#define STM32_ICU_USE_TIM3 FALSE
+#define STM32_ICU_TIM1_IRQ_PRIORITY 3
+#define STM32_ICU_TIM3_IRQ_PRIORITY 3
+
+/*
+ * PWM driver system settings.
+ */
+#define STM32_PWM_USE_ADVANCED FALSE
+#define STM32_PWM_USE_TIM1 FALSE
+#define STM32_PWM_USE_TIM3 FALSE
+#define STM32_PWM_TIM1_IRQ_PRIORITY 3
+#define STM32_PWM_TIM3_IRQ_PRIORITY 3
+
+/*
+ * SERIAL driver system settings.
+ */
+#define STM32_SERIAL_USE_USART1 FALSE
+#define STM32_SERIAL_USE_USART2 TRUE
+#define STM32_SERIAL_USART1_PRIORITY 3
+#define STM32_SERIAL_USART2_PRIORITY 3
+
+/*
+ * SPI driver system settings.
+ */
+#define STM32_SPI_USE_SPI1 FALSE
+#define STM32_SPI_USE_SPI2 FALSE
+#define STM32_SPI_SPI1_DMA_PRIORITY 1
+#define STM32_SPI_SPI2_DMA_PRIORITY 1
+#define STM32_SPI_SPI1_IRQ_PRIORITY 2
+#define STM32_SPI_SPI2_IRQ_PRIORITY 2
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
+
+/*
+ * ST driver system settings.
+ */
+#define STM32_ST_IRQ_PRIORITY 2
+#define STM32_ST_USE_TIMER 3
+
+/*
+ * UART driver system settings.
+ */
+#define STM32_UART_USE_USART1 FALSE
+#define STM32_UART_USE_USART2 FALSE
+#define STM32_UART_USART1_IRQ_PRIORITY 3
+#define STM32_UART_USART2_IRQ_PRIORITY 3
+#define STM32_UART_USART1_DMA_PRIORITY 0
+#define STM32_UART_USART2_DMA_PRIORITY 0
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
+
+#endif /* _MCUCONF_H_ */
diff --git a/demos/STM32/RT-STM32F091RC-NUCLEO/readme.txt b/demos/STM32/RT-STM32F091RC-NUCLEO/readme.txt new file mode 100644 index 000000000..ee5983f58 --- /dev/null +++ b/demos/STM32/RT-STM32F091RC-NUCLEO/readme.txt @@ -0,0 +1,28 @@ +*****************************************************************************
+** ChibiOS/RT port for ARM-Cortex-M0 STM32F091. **
+*****************************************************************************
+
+** TARGET **
+
+The demo runs on an ST_NUCLEO_F091RC board.
+
+** The Demo **
+
+The demo flashes the board LED using a thread, by pressing the button located
+on the board the test procedure is activated with output on the serial port
+SD2 (USART2, mapped on USB virtual COM port).
+
+** Build Procedure **
+
+The demo has been tested by using the free Codesourcery GCC-based toolchain
+and YAGARTO. just modify the TRGT line in the makefile in order to use
+different GCC toolchains.
+
+** Notes **
+
+Some files used by the demo are not part of ChibiOS/RT but are copyright of
+ST Microelectronics and are licensed under a different license.
+Also note that not all the files present in the ST library are distributed
+with ChibiOS/RT, you can find the whole library on the ST web site:
+
+ http://www.st.com
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F091xC.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F091xC.ld new file mode 100644 index 000000000..6d0ca2692 --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F091xC.ld @@ -0,0 +1,53 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/*
+ * STM32F091xC memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x08000000, len = 256k
+ ram0 : org = 0x20000000, len = 32k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+INCLUDE rules.ld
diff --git a/os/hal/boards/ST_NUCLEO_F091RC/board.c b/os/hal/boards/ST_NUCLEO_F091RC/board.c new file mode 100644 index 000000000..29d04aba5 --- /dev/null +++ b/os/hal/boards/ST_NUCLEO_F091RC/board.c @@ -0,0 +1,102 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config = {
+#if STM32_HAS_GPIOA
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
+#endif
+};
+#endif
+
+/**
+ * @brief Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ * and before any other initialization.
+ */
+void __early_init(void) {
+
+ stm32_clock_init();
+}
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* TODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* TODO: Fill the implementation.*/
+ return false;
+}
+#endif
+
+/**
+ * @brief Board-specific initialization code.
+ * @todo Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/ST_NUCLEO_F091RC/board.h b/os/hal/boards/ST_NUCLEO_F091RC/board.h new file mode 100644 index 000000000..a0f4a8072 --- /dev/null +++ b/os/hal/boards/ST_NUCLEO_F091RC/board.h @@ -0,0 +1,889 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for STMicroelectronics NUCLEO-F091RC board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_NUCLEO_F091RC
+#define BOARD_NAME "STMicroelectronics NUCLEO-F091RC"
+
+/*
+ * Board oscillators-related settings.
+ * NOTE: LSE not fitted.
+ * NOTE: HSE not fitted.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK 0U
+#endif
+
+#define STM32_LSEDRV (3U << 3U)
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK 0U
+#endif
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32F091xC
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_PIN0 0U
+#define GPIOA_PIN1 1U
+#define GPIOA_USART_TX 2U
+#define GPIOA_USART_RX 3U
+#define GPIOA_PIN4 4U
+#define GPIOA_LED_GREEN 5U
+#define GPIOA_PIN6 6U
+#define GPIOA_PIN7 7U
+#define GPIOA_PIN8 8U
+#define GPIOA_PIN9 9U
+#define GPIOA_PIN10 10U
+#define GPIOA_OTG_FS_DM 11U
+#define GPIOA_OTG_FS_DP 12U
+#define GPIOA_SWDIO 13U
+#define GPIOA_SWCLK 14U
+#define GPIOA_PIN15 15U
+
+#define GPIOB_PIN0 0U
+#define GPIOB_PIN1 1U
+#define GPIOB_PIN2 2U
+#define GPIOB_SWO 3U
+#define GPIOB_PIN4 4U
+#define GPIOB_PIN5 5U
+#define GPIOB_PIN6 6U
+#define GPIOB_PIN7 7U
+#define GPIOB_PIN8 8U
+#define GPIOB_PIN9 9U
+#define GPIOB_PIN10 10U
+#define GPIOB_PIN11 11U
+#define GPIOB_PIN12 12U
+#define GPIOB_PIN13 13U
+#define GPIOB_PIN14 14U
+#define GPIOB_PIN15 15U
+
+#define GPIOC_PIN0 0U
+#define GPIOC_PIN1 1U
+#define GPIOC_PIN2 2U
+#define GPIOC_PIN3 3U
+#define GPIOC_PIN4 4U
+#define GPIOC_PIN5 5U
+#define GPIOC_PIN6 6U
+#define GPIOC_PIN7 7U
+#define GPIOC_PIN8 8U
+#define GPIOC_PIN9 9U
+#define GPIOC_PIN10 10U
+#define GPIOC_PIN11 11U
+#define GPIOC_PIN12 12U
+#define GPIOC_BUTTON 13U
+#define GPIOC_PIN14 14U
+#define GPIOC_PIN15 15U
+
+#define GPIOD_PIN0 0U
+#define GPIOD_PIN1 1U
+#define GPIOD_PIN2 2U
+#define GPIOD_PIN3 3U
+#define GPIOD_PIN4 4U
+#define GPIOD_PIN5 5U
+#define GPIOD_PIN6 6U
+#define GPIOD_PIN7 7U
+#define GPIOD_PIN8 8U
+#define GPIOD_PIN9 9U
+#define GPIOD_PIN10 10U
+#define GPIOD_PIN11 11U
+#define GPIOD_PIN12 12U
+#define GPIOD_PIN13 13U
+#define GPIOD_PIN14 14U
+#define GPIOD_PIN15 15U
+
+#define GPIOE_PIN0 0U
+#define GPIOE_PIN1 1U
+#define GPIOE_PIN2 2U
+#define GPIOE_PIN3 3U
+#define GPIOE_PIN4 4U
+#define GPIOE_PIN5 5U
+#define GPIOE_PIN6 6U
+#define GPIOE_PIN7 7U
+#define GPIOE_PIN8 8U
+#define GPIOE_PIN9 9U
+#define GPIOE_PIN10 10U
+#define GPIOE_PIN11 11U
+#define GPIOE_PIN12 12U
+#define GPIOE_PIN13 13U
+#define GPIOE_PIN14 14U
+#define GPIOE_PIN15 15U
+
+#define GPIOF_PIN0 0U
+#define GPIOF_PIN1 1U
+#define GPIOF_PIN2 2U
+#define GPIOF_PIN3 3U
+#define GPIOF_PIN4 4U
+#define GPIOF_PIN5 5U
+#define GPIOF_PIN6 6U
+#define GPIOF_PIN7 7U
+#define GPIOF_PIN8 8U
+#define GPIOF_PIN9 9U
+#define GPIOF_PIN10 10U
+#define GPIOF_PIN11 11U
+#define GPIOF_PIN12 12U
+#define GPIOF_PIN13 13U
+#define GPIOF_PIN14 14U
+#define GPIOF_PIN15 15U
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
+#define PIN_ODR_LOW(n) (0U << (n))
+#define PIN_ODR_HIGH(n) (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_2M(n) (0U << ((n) * 2U))
+#define PIN_OSPEED_10M(n) (1U << ((n) * 2U))
+#define PIN_OSPEED_40M(n) (3U << ((n) * 2U))
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
+#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0 - PIN0 (input pullup).
+ * PA1 - PIN1 (input pullup).
+ * PA2 - USART_TX (alternate 7).
+ * PA3 - USART_RX (alternate 7).
+ * PA4 - PIN4 (input pullup).
+ * PA5 - LED_GREEN (output pushpull high).
+ * PA6 - PIN6 (input pullup).
+ * PA7 - PIN7 (input pullup).
+ * PA8 - PIN8 (input pullup).
+ * PA9 - PIN9 (input pullup).
+ * PA10 - PIN10 (input pullup).
+ * PA11 - OTG_FS_DM (alternate 10).
+ * PA12 - OTG_FS_DP (alternate 10).
+ * PA13 - SWDIO (alternate 0).
+ * PA14 - SWCLK (alternate 0).
+ * PA15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_PIN0) | \
+ PIN_MODE_INPUT(GPIOA_PIN1) | \
+ PIN_MODE_ALTERNATE(GPIOA_USART_TX) | \
+ PIN_MODE_ALTERNATE(GPIOA_USART_RX) | \
+ PIN_MODE_INPUT(GPIOA_PIN4) | \
+ PIN_MODE_OUTPUT(GPIOA_LED_GREEN) | \
+ PIN_MODE_INPUT(GPIOA_PIN6) | \
+ PIN_MODE_INPUT(GPIOA_PIN7) | \
+ PIN_MODE_INPUT(GPIOA_PIN8) | \
+ PIN_MODE_INPUT(GPIOA_PIN9) | \
+ PIN_MODE_INPUT(GPIOA_PIN10) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
+ PIN_MODE_INPUT(GPIOA_PIN15))
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_USART_TX) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_USART_RX) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_LED_GREEN) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_40M(GPIOA_PIN0) | \
+ PIN_OSPEED_40M(GPIOA_PIN1) | \
+ PIN_OSPEED_10M(GPIOA_USART_TX) | \
+ PIN_OSPEED_10M(GPIOA_USART_RX) | \
+ PIN_OSPEED_40M(GPIOA_PIN4) | \
+ PIN_OSPEED_10M(GPIOA_LED_GREEN) | \
+ PIN_OSPEED_40M(GPIOA_PIN6) | \
+ PIN_OSPEED_40M(GPIOA_PIN7) | \
+ PIN_OSPEED_40M(GPIOA_PIN8) | \
+ PIN_OSPEED_40M(GPIOA_PIN9) | \
+ PIN_OSPEED_40M(GPIOA_PIN10) | \
+ PIN_OSPEED_40M(GPIOA_OTG_FS_DM) | \
+ PIN_OSPEED_40M(GPIOA_OTG_FS_DP) | \
+ PIN_OSPEED_40M(GPIOA_SWDIO) | \
+ PIN_OSPEED_40M(GPIOA_SWCLK) | \
+ PIN_OSPEED_40M(GPIOA_PIN15))
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOA_USART_TX) | \
+ PIN_PUPDR_FLOATING(GPIOA_USART_RX) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOA_LED_GREEN) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \
+ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \
+ PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \
+ PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN15))
+#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \
+ PIN_ODR_HIGH(GPIOA_PIN1) | \
+ PIN_ODR_HIGH(GPIOA_USART_TX) | \
+ PIN_ODR_HIGH(GPIOA_USART_RX) | \
+ PIN_ODR_HIGH(GPIOA_PIN4) | \
+ PIN_ODR_LOW(GPIOA_LED_GREEN) | \
+ PIN_ODR_HIGH(GPIOA_PIN6) | \
+ PIN_ODR_HIGH(GPIOA_PIN7) | \
+ PIN_ODR_HIGH(GPIOA_PIN8) | \
+ PIN_ODR_HIGH(GPIOA_PIN9) | \
+ PIN_ODR_HIGH(GPIOA_PIN10) | \
+ PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \
+ PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \
+ PIN_ODR_HIGH(GPIOA_SWDIO) | \
+ PIN_ODR_HIGH(GPIOA_SWCLK) | \
+ PIN_ODR_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOA_USART_TX, 7) | \
+ PIN_AFIO_AF(GPIOA_USART_RX, 7) | \
+ PIN_AFIO_AF(GPIOA_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOA_LED_GREEN, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN7, 0))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \
+ PIN_AFIO_AF(GPIOA_SWDIO, 0) | \
+ PIN_AFIO_AF(GPIOA_SWCLK, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN15, 0))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0 - PIN0 (input pullup).
+ * PB1 - PIN1 (input pullup).
+ * PB2 - PIN2 (input pullup).
+ * PB3 - SWO (alternate 0).
+ * PB4 - PIN4 (input pullup).
+ * PB5 - PIN5 (input pullup).
+ * PB6 - PIN6 (input pullup).
+ * PB7 - PIN7 (input pullup).
+ * PB8 - PIN8 (input pullup).
+ * PB9 - PIN9 (input pullup).
+ * PB10 - PIN10 (input pullup).
+ * PB11 - PIN11 (input pullup).
+ * PB12 - PIN12 (input pullup).
+ * PB13 - PIN13 (input pullup).
+ * PB14 - PIN14 (input pullup).
+ * PB15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \
+ PIN_MODE_INPUT(GPIOB_PIN1) | \
+ PIN_MODE_INPUT(GPIOB_PIN2) | \
+ PIN_MODE_ALTERNATE(GPIOB_SWO) | \
+ PIN_MODE_INPUT(GPIOB_PIN4) | \
+ PIN_MODE_INPUT(GPIOB_PIN5) | \
+ PIN_MODE_INPUT(GPIOB_PIN6) | \
+ PIN_MODE_INPUT(GPIOB_PIN7) | \
+ PIN_MODE_INPUT(GPIOB_PIN8) | \
+ PIN_MODE_INPUT(GPIOB_PIN9) | \
+ PIN_MODE_INPUT(GPIOB_PIN10) | \
+ PIN_MODE_INPUT(GPIOB_PIN11) | \
+ PIN_MODE_INPUT(GPIOB_PIN12) | \
+ PIN_MODE_INPUT(GPIOB_PIN13) | \
+ PIN_MODE_INPUT(GPIOB_PIN14) | \
+ PIN_MODE_INPUT(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_40M(GPIOB_PIN0) | \
+ PIN_OSPEED_40M(GPIOB_PIN1) | \
+ PIN_OSPEED_40M(GPIOB_PIN2) | \
+ PIN_OSPEED_40M(GPIOB_SWO) | \
+ PIN_OSPEED_40M(GPIOB_PIN4) | \
+ PIN_OSPEED_40M(GPIOB_PIN5) | \
+ PIN_OSPEED_40M(GPIOB_PIN6) | \
+ PIN_OSPEED_40M(GPIOB_PIN7) | \
+ PIN_OSPEED_40M(GPIOB_PIN8) | \
+ PIN_OSPEED_40M(GPIOB_PIN9) | \
+ PIN_OSPEED_40M(GPIOB_PIN10) | \
+ PIN_OSPEED_40M(GPIOB_PIN11) | \
+ PIN_OSPEED_40M(GPIOB_PIN12) | \
+ PIN_OSPEED_40M(GPIOB_PIN13) | \
+ PIN_OSPEED_40M(GPIOB_PIN14) | \
+ PIN_OSPEED_40M(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOB_SWO) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN15))
+#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \
+ PIN_ODR_HIGH(GPIOB_PIN1) | \
+ PIN_ODR_HIGH(GPIOB_PIN2) | \
+ PIN_ODR_HIGH(GPIOB_SWO) | \
+ PIN_ODR_HIGH(GPIOB_PIN4) | \
+ PIN_ODR_HIGH(GPIOB_PIN5) | \
+ PIN_ODR_HIGH(GPIOB_PIN6) | \
+ PIN_ODR_HIGH(GPIOB_PIN7) | \
+ PIN_ODR_HIGH(GPIOB_PIN8) | \
+ PIN_ODR_HIGH(GPIOB_PIN9) | \
+ PIN_ODR_HIGH(GPIOB_PIN10) | \
+ PIN_ODR_HIGH(GPIOB_PIN11) | \
+ PIN_ODR_HIGH(GPIOB_PIN12) | \
+ PIN_ODR_HIGH(GPIOB_PIN13) | \
+ PIN_ODR_HIGH(GPIOB_PIN14) | \
+ PIN_ODR_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOB_SWO, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN7, 0))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN15, 0))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0 - PIN0 (input pullup).
+ * PC1 - PIN1 (input pullup).
+ * PC2 - PIN2 (input pullup).
+ * PC3 - PIN3 (input pullup).
+ * PC4 - PIN4 (input pullup).
+ * PC5 - PIN5 (input pullup).
+ * PC6 - PIN6 (input pullup).
+ * PC7 - PIN7 (input pullup).
+ * PC8 - PIN8 (input pullup).
+ * PC9 - PIN9 (input pullup).
+ * PC10 - PIN10 (input pullup).
+ * PC11 - PIN11 (input pullup).
+ * PC12 - PIN12 (input pullup).
+ * PC13 - BUTTON (input floating).
+ * PC14 - PIN14 (input pullup).
+ * PC15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \
+ PIN_MODE_INPUT(GPIOC_PIN1) | \
+ PIN_MODE_INPUT(GPIOC_PIN2) | \
+ PIN_MODE_INPUT(GPIOC_PIN3) | \
+ PIN_MODE_INPUT(GPIOC_PIN4) | \
+ PIN_MODE_INPUT(GPIOC_PIN5) | \
+ PIN_MODE_INPUT(GPIOC_PIN6) | \
+ PIN_MODE_INPUT(GPIOC_PIN7) | \
+ PIN_MODE_INPUT(GPIOC_PIN8) | \
+ PIN_MODE_INPUT(GPIOC_PIN9) | \
+ PIN_MODE_INPUT(GPIOC_PIN10) | \
+ PIN_MODE_INPUT(GPIOC_PIN11) | \
+ PIN_MODE_INPUT(GPIOC_PIN12) | \
+ PIN_MODE_INPUT(GPIOC_BUTTON) | \
+ PIN_MODE_INPUT(GPIOC_PIN14) | \
+ PIN_MODE_INPUT(GPIOC_PIN15))
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN15))
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_40M(GPIOC_PIN0) | \
+ PIN_OSPEED_40M(GPIOC_PIN1) | \
+ PIN_OSPEED_40M(GPIOC_PIN2) | \
+ PIN_OSPEED_40M(GPIOC_PIN3) | \
+ PIN_OSPEED_40M(GPIOC_PIN4) | \
+ PIN_OSPEED_40M(GPIOC_PIN5) | \
+ PIN_OSPEED_40M(GPIOC_PIN6) | \
+ PIN_OSPEED_40M(GPIOC_PIN7) | \
+ PIN_OSPEED_40M(GPIOC_PIN8) | \
+ PIN_OSPEED_40M(GPIOC_PIN9) | \
+ PIN_OSPEED_40M(GPIOC_PIN10) | \
+ PIN_OSPEED_40M(GPIOC_PIN11) | \
+ PIN_OSPEED_40M(GPIOC_PIN12) | \
+ PIN_OSPEED_40M(GPIOC_BUTTON) | \
+ PIN_OSPEED_40M(GPIOC_PIN14) | \
+ PIN_OSPEED_40M(GPIOC_PIN15))
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN15))
+#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \
+ PIN_ODR_HIGH(GPIOC_PIN1) | \
+ PIN_ODR_HIGH(GPIOC_PIN2) | \
+ PIN_ODR_HIGH(GPIOC_PIN3) | \
+ PIN_ODR_HIGH(GPIOC_PIN4) | \
+ PIN_ODR_HIGH(GPIOC_PIN5) | \
+ PIN_ODR_HIGH(GPIOC_PIN6) | \
+ PIN_ODR_HIGH(GPIOC_PIN7) | \
+ PIN_ODR_HIGH(GPIOC_PIN8) | \
+ PIN_ODR_HIGH(GPIOC_PIN9) | \
+ PIN_ODR_HIGH(GPIOC_PIN10) | \
+ PIN_ODR_HIGH(GPIOC_PIN11) | \
+ PIN_ODR_HIGH(GPIOC_PIN12) | \
+ PIN_ODR_HIGH(GPIOC_BUTTON) | \
+ PIN_ODR_HIGH(GPIOC_PIN14) | \
+ PIN_ODR_HIGH(GPIOC_PIN15))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN7, 0))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOC_BUTTON, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN15, 0))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0 - PIN0 (input pullup).
+ * PD1 - PIN1 (input pullup).
+ * PD2 - PIN2 (input pullup).
+ * PD3 - PIN3 (input pullup).
+ * PD4 - PIN4 (input pullup).
+ * PD5 - PIN5 (input pullup).
+ * PD6 - PIN6 (input pullup).
+ * PD7 - PIN7 (input pullup).
+ * PD8 - PIN8 (input pullup).
+ * PD9 - PIN9 (input pullup).
+ * PD10 - PIN10 (input pullup).
+ * PD11 - PIN11 (input pullup).
+ * PD12 - PIN12 (input pullup).
+ * PD13 - PIN13 (input pullup).
+ * PD14 - PIN14 (input pullup).
+ * PD15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \
+ PIN_MODE_INPUT(GPIOD_PIN1) | \
+ PIN_MODE_INPUT(GPIOD_PIN2) | \
+ PIN_MODE_INPUT(GPIOD_PIN3) | \
+ PIN_MODE_INPUT(GPIOD_PIN4) | \
+ PIN_MODE_INPUT(GPIOD_PIN5) | \
+ PIN_MODE_INPUT(GPIOD_PIN6) | \
+ PIN_MODE_INPUT(GPIOD_PIN7) | \
+ PIN_MODE_INPUT(GPIOD_PIN8) | \
+ PIN_MODE_INPUT(GPIOD_PIN9) | \
+ PIN_MODE_INPUT(GPIOD_PIN10) | \
+ PIN_MODE_INPUT(GPIOD_PIN11) | \
+ PIN_MODE_INPUT(GPIOD_PIN12) | \
+ PIN_MODE_INPUT(GPIOD_PIN13) | \
+ PIN_MODE_INPUT(GPIOD_PIN14) | \
+ PIN_MODE_INPUT(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_40M(GPIOD_PIN0) | \
+ PIN_OSPEED_40M(GPIOD_PIN1) | \
+ PIN_OSPEED_40M(GPIOD_PIN2) | \
+ PIN_OSPEED_40M(GPIOD_PIN3) | \
+ PIN_OSPEED_40M(GPIOD_PIN4) | \
+ PIN_OSPEED_40M(GPIOD_PIN5) | \
+ PIN_OSPEED_40M(GPIOD_PIN6) | \
+ PIN_OSPEED_40M(GPIOD_PIN7) | \
+ PIN_OSPEED_40M(GPIOD_PIN8) | \
+ PIN_OSPEED_40M(GPIOD_PIN9) | \
+ PIN_OSPEED_40M(GPIOD_PIN10) | \
+ PIN_OSPEED_40M(GPIOD_PIN11) | \
+ PIN_OSPEED_40M(GPIOD_PIN12) | \
+ PIN_OSPEED_40M(GPIOD_PIN13) | \
+ PIN_OSPEED_40M(GPIOD_PIN14) | \
+ PIN_OSPEED_40M(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN15))
+#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
+ PIN_ODR_HIGH(GPIOD_PIN1) | \
+ PIN_ODR_HIGH(GPIOD_PIN2) | \
+ PIN_ODR_HIGH(GPIOD_PIN3) | \
+ PIN_ODR_HIGH(GPIOD_PIN4) | \
+ PIN_ODR_HIGH(GPIOD_PIN5) | \
+ PIN_ODR_HIGH(GPIOD_PIN6) | \
+ PIN_ODR_HIGH(GPIOD_PIN7) | \
+ PIN_ODR_HIGH(GPIOD_PIN8) | \
+ PIN_ODR_HIGH(GPIOD_PIN9) | \
+ PIN_ODR_HIGH(GPIOD_PIN10) | \
+ PIN_ODR_HIGH(GPIOD_PIN11) | \
+ PIN_ODR_HIGH(GPIOD_PIN12) | \
+ PIN_ODR_HIGH(GPIOD_PIN13) | \
+ PIN_ODR_HIGH(GPIOD_PIN14) | \
+ PIN_ODR_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN7, 0))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN15, 0))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0 - PIN0 (input pullup).
+ * PE1 - PIN1 (input pullup).
+ * PE2 - PIN2 (input floating).
+ * PE3 - PIN3 (input pullup).
+ * PE4 - PIN4 (input floating).
+ * PE5 - PIN5 (input floating).
+ * PE6 - PIN6 (input floating).
+ * PE7 - PIN7 (input floating).
+ * PE8 - PIN8 (input floating).
+ * PE9 - PIN9 (input floating).
+ * PE10 - PIN10 (input floating).
+ * PE11 - PIN11 (input floating).
+ * PE12 - PIN12 (input floating).
+ * PE13 - PIN13 (input floating).
+ * PE14 - PIN14 (input floating).
+ * PE15 - PIN15 (input floating).
+ */
+#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \
+ PIN_MODE_INPUT(GPIOE_PIN1) | \
+ PIN_MODE_INPUT(GPIOE_PIN2) | \
+ PIN_MODE_INPUT(GPIOE_PIN3) | \
+ PIN_MODE_INPUT(GPIOE_PIN4) | \
+ PIN_MODE_INPUT(GPIOE_PIN5) | \
+ PIN_MODE_INPUT(GPIOE_PIN6) | \
+ PIN_MODE_INPUT(GPIOE_PIN7) | \
+ PIN_MODE_INPUT(GPIOE_PIN8) | \
+ PIN_MODE_INPUT(GPIOE_PIN9) | \
+ PIN_MODE_INPUT(GPIOE_PIN10) | \
+ PIN_MODE_INPUT(GPIOE_PIN11) | \
+ PIN_MODE_INPUT(GPIOE_PIN12) | \
+ PIN_MODE_INPUT(GPIOE_PIN13) | \
+ PIN_MODE_INPUT(GPIOE_PIN14) | \
+ PIN_MODE_INPUT(GPIOE_PIN15))
+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
+#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_40M(GPIOE_PIN0) | \
+ PIN_OSPEED_40M(GPIOE_PIN1) | \
+ PIN_OSPEED_40M(GPIOE_PIN2) | \
+ PIN_OSPEED_40M(GPIOE_PIN3) | \
+ PIN_OSPEED_40M(GPIOE_PIN4) | \
+ PIN_OSPEED_40M(GPIOE_PIN5) | \
+ PIN_OSPEED_40M(GPIOE_PIN6) | \
+ PIN_OSPEED_40M(GPIOE_PIN7) | \
+ PIN_OSPEED_40M(GPIOE_PIN8) | \
+ PIN_OSPEED_40M(GPIOE_PIN9) | \
+ PIN_OSPEED_40M(GPIOE_PIN10) | \
+ PIN_OSPEED_40M(GPIOE_PIN11) | \
+ PIN_OSPEED_40M(GPIOE_PIN12) | \
+ PIN_OSPEED_40M(GPIOE_PIN13) | \
+ PIN_OSPEED_40M(GPIOE_PIN14) | \
+ PIN_OSPEED_40M(GPIOE_PIN15))
+#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN15))
+#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \
+ PIN_ODR_HIGH(GPIOE_PIN1) | \
+ PIN_ODR_HIGH(GPIOE_PIN2) | \
+ PIN_ODR_HIGH(GPIOE_PIN3) | \
+ PIN_ODR_HIGH(GPIOE_PIN4) | \
+ PIN_ODR_HIGH(GPIOE_PIN5) | \
+ PIN_ODR_HIGH(GPIOE_PIN6) | \
+ PIN_ODR_HIGH(GPIOE_PIN7) | \
+ PIN_ODR_HIGH(GPIOE_PIN8) | \
+ PIN_ODR_HIGH(GPIOE_PIN9) | \
+ PIN_ODR_HIGH(GPIOE_PIN10) | \
+ PIN_ODR_HIGH(GPIOE_PIN11) | \
+ PIN_ODR_HIGH(GPIOE_PIN12) | \
+ PIN_ODR_HIGH(GPIOE_PIN13) | \
+ PIN_ODR_HIGH(GPIOE_PIN14) | \
+ PIN_ODR_HIGH(GPIOE_PIN15))
+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN7, 0))
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN15, 0))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0 - PIN0 (input floating).
+ * PF1 - PIN1 (input floating).
+ * PF2 - PIN2 (input floating).
+ * PF3 - PIN3 (input floating).
+ * PF4 - PIN4 (input floating).
+ * PF5 - PIN5 (input floating).
+ * PF6 - PIN6 (input floating).
+ * PF7 - PIN7 (input floating).
+ * PF8 - PIN8 (input floating).
+ * PF9 - PIN9 (input floating).
+ * PF10 - PIN10 (input floating).
+ * PF11 - PIN11 (input floating).
+ * PF12 - PIN12 (input floating).
+ * PF13 - PIN13 (input floating).
+ * PF14 - PIN14 (input floating).
+ * PF15 - PIN15 (input floating).
+ */
+#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \
+ PIN_MODE_INPUT(GPIOF_PIN1) | \
+ PIN_MODE_INPUT(GPIOF_PIN2) | \
+ PIN_MODE_INPUT(GPIOF_PIN3) | \
+ PIN_MODE_INPUT(GPIOF_PIN4) | \
+ PIN_MODE_INPUT(GPIOF_PIN5) | \
+ PIN_MODE_INPUT(GPIOF_PIN6) | \
+ PIN_MODE_INPUT(GPIOF_PIN7) | \
+ PIN_MODE_INPUT(GPIOF_PIN8) | \
+ PIN_MODE_INPUT(GPIOF_PIN9) | \
+ PIN_MODE_INPUT(GPIOF_PIN10) | \
+ PIN_MODE_INPUT(GPIOF_PIN11) | \
+ PIN_MODE_INPUT(GPIOF_PIN12) | \
+ PIN_MODE_INPUT(GPIOF_PIN13) | \
+ PIN_MODE_INPUT(GPIOF_PIN14) | \
+ PIN_MODE_INPUT(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_40M(GPIOF_PIN0) | \
+ PIN_OSPEED_40M(GPIOF_PIN1) | \
+ PIN_OSPEED_40M(GPIOF_PIN2) | \
+ PIN_OSPEED_40M(GPIOF_PIN3) | \
+ PIN_OSPEED_40M(GPIOF_PIN4) | \
+ PIN_OSPEED_40M(GPIOF_PIN5) | \
+ PIN_OSPEED_40M(GPIOF_PIN6) | \
+ PIN_OSPEED_40M(GPIOF_PIN7) | \
+ PIN_OSPEED_40M(GPIOF_PIN8) | \
+ PIN_OSPEED_40M(GPIOF_PIN9) | \
+ PIN_OSPEED_40M(GPIOF_PIN10) | \
+ PIN_OSPEED_40M(GPIOF_PIN11) | \
+ PIN_OSPEED_40M(GPIOF_PIN12) | \
+ PIN_OSPEED_40M(GPIOF_PIN13) | \
+ PIN_OSPEED_40M(GPIOF_PIN14) | \
+ PIN_OSPEED_40M(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN15))
+#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \
+ PIN_ODR_HIGH(GPIOF_PIN1) | \
+ PIN_ODR_HIGH(GPIOF_PIN2) | \
+ PIN_ODR_HIGH(GPIOF_PIN3) | \
+ PIN_ODR_HIGH(GPIOF_PIN4) | \
+ PIN_ODR_HIGH(GPIOF_PIN5) | \
+ PIN_ODR_HIGH(GPIOF_PIN6) | \
+ PIN_ODR_HIGH(GPIOF_PIN7) | \
+ PIN_ODR_HIGH(GPIOF_PIN8) | \
+ PIN_ODR_HIGH(GPIOF_PIN9) | \
+ PIN_ODR_HIGH(GPIOF_PIN10) | \
+ PIN_ODR_HIGH(GPIOF_PIN11) | \
+ PIN_ODR_HIGH(GPIOF_PIN12) | \
+ PIN_ODR_HIGH(GPIOF_PIN13) | \
+ PIN_ODR_HIGH(GPIOF_PIN14) | \
+ PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN7, 0))
+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN15, 0))
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_NUCLEO_F091RC/board.mk b/os/hal/boards/ST_NUCLEO_F091RC/board.mk new file mode 100644 index 000000000..d272871dd --- /dev/null +++ b/os/hal/boards/ST_NUCLEO_F091RC/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_NUCLEO_F091RC/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/ST_NUCLEO_F091RC
diff --git a/os/hal/boards/ST_NUCLEO_F091RC/cfg/board.chcfg b/os/hal/boards/ST_NUCLEO_F091RC/cfg/board.chcfg new file mode 100644 index 000000000..3388fd83d --- /dev/null +++ b/os/hal/boards/ST_NUCLEO_F091RC/cfg/board.chcfg @@ -0,0 +1,799 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- STM32F4xx board Template --> +<board + xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" + xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32f0xx_board.xsd"> + <configuration_settings> + <templates_path>resources/gencfg/processors/boards/stm32f0xx/templates</templates_path> + <output_path>..</output_path> + <hal_version>3.0.x</hal_version> + </configuration_settings> + <board_name>STMicroelectronics NUCLEO-F091RC</board_name> + <board_id>ST_NUCLEO_F091RC</board_id> + <board_functions></board_functions> + <subtype>STM32F091xC</subtype> + <clocks HSEFrequency="0" HSEBypass="false" LSEFrequency="0" + LSEBypass="false" LSEDrive="3 High Drive (default)" /> + <ports> + <GPIOA> + <pin0 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin2 + ID="USART_TX" + Type="PushPull" + Level="High" + Speed="High" + Resistor="Floating" + Mode="Alternate" + Alternate="7" /> + <pin3 + ID="USART_RX" + Type="PushPull" + Level="High" + Speed="High" + Resistor="Floating" + Mode="Alternate" + Alternate="7" ></pin3> + <pin4 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin5 + ID="LED_GREEN" + Type="PushPull" + Level="Low" + Speed="High" + Resistor="Floating" + Mode="Output" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin11 + ID="OTG_FS_DM" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="10" /> + <pin12 + ID="OTG_FS_DP" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="10" /> + <pin13 + ID="SWDIO" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Alternate" + Alternate="0" /> + <pin14 + ID="SWCLK" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullDown" + Mode="Alternate" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + </GPIOA> + <GPIOB> + <pin0 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin3 + ID="SWO" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Alternate" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + </GPIOB> + <GPIOC> + <pin0 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin13 + ID="BUTTON" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + </GPIOC> + <GPIOD> + <pin0 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + </GPIOD> + <GPIOE> + <pin0 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + </GPIOE> + <GPIOF> + <pin0 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + </GPIOF> + </ports> +</board> diff --git a/os/hal/ports/STM32/STM32F0xx/hal_lld.h b/os/hal/ports/STM32/STM32F0xx/hal_lld.h index c6f93a541..cb2c4129f 100644 --- a/os/hal/ports/STM32/STM32F0xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F0xx/hal_lld.h @@ -96,8 +96,8 @@ #elif defined(STM32F070xB)
#define PLATFORM_NAME "STM32F070xB Entry Level Value Line devices"
-#elif defined(STM32F091x8)
-#define PLATFORM_NAME "STM32F091x8 Entry Level Medium Density devices"
+#elif defined(STM32F091xC)
+#define PLATFORM_NAME "STM32F091xC Entry Level Medium Density devices"
#elif defined(STM32F098xx)
#define PLATFORM_NAME "STM32F098xx Entry Level Medium Density devices"
diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_registry.h b/os/hal/ports/STM32/STM32F0xx/stm32_registry.h index c1fba4bbb..2f9055f14 100644 --- a/os/hal/ports/STM32/STM32F0xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F0xx/stm32_registry.h @@ -1625,9 +1625,9 @@ #define STM32_CRC_PROGRAMMABLE FALSE
/*===========================================================================*/
-/* STM32F091x8, STM32F098xx. */
+/* STM32F091xC, STM32F098xx. */
/*===========================================================================*/
-#elif defined(STM32F091x8) || defined(STM32F098xx)
+#elif defined(STM32F091xC) || defined(STM32F098xx)
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
|