diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-06-01 17:56:23 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-06-01 17:56:23 +0000 |
| commit | 33ecba3fd8ea17494b7154d20e677dd50f57b510 (patch) | |
| tree | 60bbb4dccbe930a0c8e2850d7e7df982c1aa3c54 | |
| parent | 03c0617a9fe69f113d3a55b3760a566643475394 (diff) | |
| download | ChibiOS-33ecba3fd8ea17494b7154d20e677dd50f57b510.tar.gz ChibiOS-33ecba3fd8ea17494b7154d20e677dd50f57b510.tar.bz2 ChibiOS-33ecba3fd8ea17494b7154d20e677dd50f57b510.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3005 35acf78f-673a-0410-8e92-d51de3d6d3f4
| -rw-r--r-- | docs/reports/STM32F103-72-GCC.txt | 4 | ||||
| -rw-r--r-- | docs/reports/STM32F103-72-IAR.txt | 30 | ||||
| -rw-r--r-- | docs/reports/STM32F103-72-RVCT.txt | 30 | ||||
| -rw-r--r-- | os/ports/GCC/ARMCMx/chcore.h | 49 | ||||
| -rw-r--r-- | os/ports/GCC/ARMCMx/chcore_v6m.h | 23 | ||||
| -rw-r--r-- | os/ports/GCC/ARMCMx/chcore_v7m.h | 19 | ||||
| -rw-r--r-- | os/ports/IAR/ARMCMx/chcore.h | 224 | ||||
| -rw-r--r-- | os/ports/IAR/ARMCMx/chcore_v6m.h | 96 | ||||
| -rw-r--r-- | os/ports/IAR/ARMCMx/chcore_v7m.h | 164 | ||||
| -rw-r--r-- | os/ports/RVCT/ARMCMx/chcore.h | 221 | ||||
| -rw-r--r-- | os/ports/RVCT/ARMCMx/chcore_v6m.h | 96 | ||||
| -rw-r--r-- | os/ports/RVCT/ARMCMx/chcore_v7m.h | 165 | ||||
| -rw-r--r-- | readme.txt | 4 |
13 files changed, 616 insertions, 509 deletions
diff --git a/docs/reports/STM32F103-72-GCC.txt b/docs/reports/STM32F103-72-GCC.txt index 28041072a..9c017adae 100644 --- a/docs/reports/STM32F103-72-GCC.txt +++ b/docs/reports/STM32F103-72-GCC.txt @@ -5,7 +5,7 @@ Settings: SYSCLK=72, ACR=0x12 (2 wait states) *** ChibiOS/RT test suite
***
-*** Kernel: 2.3.3unstable
+*** Kernel: 2.3.4unstable
*** Compiler: GCC 4.5.2
*** Architecture: ARMv7-M
*** Core Variant: Cortex-M3
@@ -131,7 +131,7 @@ Settings: SYSCLK=72, ACR=0x12 (2 wait states) --- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.9 (Benchmark, I/O Queues throughput)
---- Score : 581768 bytes/S
+--- Score : 592560 bytes/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.10 (Benchmark, virtual timers set/reset)
diff --git a/docs/reports/STM32F103-72-IAR.txt b/docs/reports/STM32F103-72-IAR.txt index 0ad93a193..45c9f2345 100644 --- a/docs/reports/STM32F103-72-IAR.txt +++ b/docs/reports/STM32F103-72-IAR.txt @@ -6,9 +6,11 @@ Compiler: IAR C/C++ Compiler for ARM 6.10.1.32143 *** ChibiOS/RT test suite
***
-*** Kernel: 2.1.7unstable
+*** Kernel: 2.3.4unstable
+*** Compiler: IAR
*** Architecture: ARMv7-M
*** Core Variant: Cortex-M3
+*** Port Info: Advanced kernel mode
*** Platform: STM32 Performance Line Medium Density
*** Test Board: Olimex STM32-P103
@@ -98,55 +100,55 @@ Compiler: IAR C/C++ Compiler for ARM 6.10.1.32143 --- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.1 (Benchmark, messages #1)
---- Score : 237880 msgs/S, 475760 ctxswc/S
+--- Score : 243531 msgs/S, 487062 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.2 (Benchmark, messages #2)
---- Score : 206437 msgs/S, 412874 ctxswc/S
+--- Score : 208238 msgs/S, 416476 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.3 (Benchmark, messages #3)
---- Score : 204672 msgs/S, 409344 ctxswc/S
+--- Score : 211298 msgs/S, 422596 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.4 (Benchmark, context switch)
---- Score : 861664 ctxswc/S
+--- Score : 839040 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.5 (Benchmark, threads, full cycle)
---- Score : 149986 threads/S
+--- Score : 145142 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.6 (Benchmark, threads, create only)
---- Score : 228798 threads/S
+--- Score : 221062 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)
---- Score : 68159 reschedules/S, 408954 ctxswc/S
+--- Score : 66643 reschedules/S, 399858 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.8 (Benchmark, round robin context switching)
---- Score : 459052 ctxswc/S
+--- Score : 459060 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.9 (Benchmark, I/O Queues throughput)
---- Score : 523436 bytes/S
+--- Score : 668300 bytes/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.10 (Benchmark, virtual timers set/reset)
---- Score : 674558 timers/S
+--- Score : 704334 timers/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.11 (Benchmark, semaphores wait/signal)
---- Score : 1056488 wait+signal/S
+--- Score : 1052652 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.12 (Benchmark, mutexes lock/unlock)
---- Score : 621992 lock+unlock/S
+--- Score : 623376 lock+unlock/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.13 (Benchmark, RAM footprint)
---- System: 360 bytes
+--- System: 368 bytes
--- Thread: 68 bytes
--- Timer : 20 bytes
--- Semaph: 12 bytes
diff --git a/docs/reports/STM32F103-72-RVCT.txt b/docs/reports/STM32F103-72-RVCT.txt index 0a1ab838c..1b0183a33 100644 --- a/docs/reports/STM32F103-72-RVCT.txt +++ b/docs/reports/STM32F103-72-RVCT.txt @@ -6,9 +6,11 @@ Compiler: RealView C/C++ Compiler V4.1.0.561 [Evaluation]. *** ChibiOS/RT test suite
***
-*** Kernel: 2.1.7unstable
+*** Kernel: 2.3.4unstable
+*** Compiler: RVCT
*** Architecture: ARMv7-M
*** Core Variant: Cortex-M3
+*** Port Info: Advanced kernel mode
*** Platform: STM32 Performance Line Medium Density
*** Test Board: Olimex STM32-P103
@@ -98,55 +100,55 @@ Compiler: RealView C/C++ Compiler V4.1.0.561 [Evaluation]. --- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.1 (Benchmark, messages #1)
---- Score : 230298 msgs/S, 460596 ctxswc/S
+--- Score : 244398 msgs/S, 488796 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.2 (Benchmark, messages #2)
---- Score : 202403 msgs/S, 404806 ctxswc/S
+--- Score : 214497 msgs/S, 428994 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.3 (Benchmark, messages #3)
---- Score : 201268 msgs/S, 402536 ctxswc/S
+--- Score : 214497 msgs/S, 428994 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.4 (Benchmark, context switch)
---- Score : 818864 ctxswc/S
+--- Score : 863120 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.5 (Benchmark, threads, full cycle)
---- Score : 154859 threads/S
+--- Score : 156887 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.6 (Benchmark, threads, create only)
---- Score : 221776 threads/S
+--- Score : 229569 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)
---- Score : 67404 reschedules/S, 404424 ctxswc/S
+--- Score : 68757 reschedules/S, 412542 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.8 (Benchmark, round robin context switching)
---- Score : 487136 ctxswc/S
+--- Score : 490452 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.9 (Benchmark, I/O Queues throughput)
---- Score : 547444 bytes/S
+--- Score : 612440 bytes/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.10 (Benchmark, virtual timers set/reset)
---- Score : 565768 timers/S
+--- Score : 591340 timers/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.11 (Benchmark, semaphores wait/signal)
---- Score : 876268 wait+signal/S
+--- Score : 886992 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.12 (Benchmark, mutexes lock/unlock)
---- Score : 607628 lock+unlock/S
+--- Score : 634396 lock+unlock/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.13 (Benchmark, RAM footprint)
---- System: 360 bytes
+--- System: 368 bytes
--- Thread: 68 bytes
--- Timer : 20 bytes
--- Semaph: 12 bytes
diff --git a/os/ports/GCC/ARMCMx/chcore.h b/os/ports/GCC/ARMCMx/chcore.h index 42df48a09..5d47a6699 100644 --- a/os/ports/GCC/ARMCMx/chcore.h +++ b/os/ports/GCC/ARMCMx/chcore.h @@ -29,12 +29,18 @@ #ifndef _CHCORE_H_
#define _CHCORE_H_
-#include "nvic.h"
-
/*===========================================================================*/
-/* Port constants. */
+/* Port constants (common). */
/*===========================================================================*/
+/* Added to make the header stand-alone when included from asm.*/
+#ifndef FALSE
+#define FALSE 0
+#endif
+#ifndef TRUE
+#define TRUE (!FALSE)
+#endif
+
#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */
#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
@@ -69,14 +75,8 @@ */
#define CORTEX_MAXIMUM_PRIORITY 0
-/**
- * @brief Disabled value for BASEPRI register.
- * @note ARMv7-M architecture only.
- */
-#define CORTEX_BASEPRI_DISABLED 0
-
/*===========================================================================*/
-/* Port macros. */
+/* Port macros (common). */
/*===========================================================================*/
/**
@@ -92,7 +92,7 @@ ((n) << (8 - CORTEX_PRIORITY_BITS))
/*===========================================================================*/
-/* Port configurable parameters. */
+/* Port configurable parameters (common). */
/*===========================================================================*/
/**
@@ -156,11 +156,11 @@ #endif
/*===========================================================================*/
-/* Port derived parameters. */
+/* Port derived parameters (common). */
/*===========================================================================*/
/*===========================================================================*/
-/* Port exported info. */
+/* Port exported info (common). */
/*===========================================================================*/
/**
@@ -177,6 +177,17 @@ /* Port implementation part (common). */
/*===========================================================================*/
+/* Includes the sub-architecture-specific part.*/
+#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1)
+#include "chcore_v6m.h"
+#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4)
+#include "chcore_v7m.h"
+#endif
+
+#if !defined(_FROM_ASM_)
+
+#include "nvic.h"
+
/**
* @brief Stack and memory alignment enforcement.
*/
@@ -193,11 +204,6 @@ typedef uint32_t stkalign_t __attribute__ ((aligned (4))); #error "invalid stack alignment selected"
#endif
-/**
- * @brief Generic ARM register.
- */
-typedef void *regarm_t;
-
#if defined(__DOXYGEN__)
/**
* @brief Interrupt saved context.
@@ -262,12 +268,7 @@ struct context { */
#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
-/* Includes the architecture-specific implementation part.*/
-#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1)
-#include "chcore_v6m.h"
-#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4)
-#include "chcore_v7m.h"
-#endif
+#endif /* _FROM_ASM_ */
#endif /* _CHCORE_H_ */
diff --git a/os/ports/GCC/ARMCMx/chcore_v6m.h b/os/ports/GCC/ARMCMx/chcore_v6m.h index 3154bde56..e6aeabc2d 100644 --- a/os/ports/GCC/ARMCMx/chcore_v6m.h +++ b/os/ports/GCC/ARMCMx/chcore_v6m.h @@ -34,20 +34,12 @@ /*===========================================================================*/
/**
- * @brief BASEPRI level within kernel lock.
- * @note The ARMv6-M architecture does not implement the BASEPRI register
- * so the kernel always masks the whole priority range during
- * a kernel lock.
- */
-#define CORTEX_BASEPRI_KERNEL 0
-
-/**
* @brief PendSV priority level.
- * @note This priority is enforced to be equal to @p CORTEX_BASEPRI_KERNEL,
+ * @note This priority is enforced to be equal to @p 0,
* this handler always have the highest priority that cannot preempt
* the kernel.
*/
-#define CORTEX_PRIORITY_PENDSV CORTEX_BASEPRI_KERNEL
+#define CORTEX_PRIORITY_PENDSV 0
/*===========================================================================*/
/* Port configurable parameters. */
@@ -64,7 +56,7 @@ /**
* @brief Macro defining the specific ARM architecture.
*/
-#define CH_ARCHITECTURE_ARM_v7M
+#define CH_ARCHITECTURE_ARM_v6M
/**
* @brief Name of the implemented architecture.
@@ -84,6 +76,13 @@ /* Port implementation part. */
/*===========================================================================*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief Generic ARM register.
+ */
+typedef void *regarm_t;
+
#if !defined(__DOXYGEN__)
struct extctx {
regarm_t r0;
@@ -244,6 +243,8 @@ extern "C" { }
#endif
+#endif /* _FROM_ASM_ */
+
#endif /* _CHCORE_V6M_H_ */
/** @} */
diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.h b/os/ports/GCC/ARMCMx/chcore_v7m.h index 7a7eaeb53..297bd4e54 100644 --- a/os/ports/GCC/ARMCMx/chcore_v7m.h +++ b/os/ports/GCC/ARMCMx/chcore_v7m.h @@ -33,6 +33,11 @@ /* Port constants. */
/*===========================================================================*/
+/**
+ * @brief Disabled value for BASEPRI register.
+ */
+#define CORTEX_BASEPRI_DISABLED 0
+
/*===========================================================================*/
/* Port configurable parameters. */
/*===========================================================================*/
@@ -88,6 +93,7 @@ /* Port exported info. */
/*===========================================================================*/
+#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
/**
* @brief Macro defining the specific ARM architecture.
*/
@@ -101,9 +107,11 @@ /**
* @brief Name of the architecture variant.
*/
-#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
#define CH_CORE_VARIANT_NAME "Cortex-M3"
+
#elif (CORTEX_MODEL == CORTEX_M4)
+#define CH_ARCHITECTURE_ARM_v7ME
+#define CH_ARCHITECTURE_NAME "ARMv7-ME"
#define CH_CORE_VARIANT_NAME "Cortex-M4"
#endif
@@ -120,6 +128,13 @@ /* Port implementation part. */
/*===========================================================================*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief Generic ARM register.
+ */
+typedef void *regarm_t;
+
#if !defined(__DOXYGEN__)
struct extctx {
regarm_t r0;
@@ -315,6 +330,8 @@ extern "C" { }
#endif
+#endif /* _FROM_ASM_ */
+
#endif /* _CHCORE_V7M_H_ */
/** @} */
diff --git a/os/ports/IAR/ARMCMx/chcore.h b/os/ports/IAR/ARMCMx/chcore.h index 9c6a63730..177205fa6 100644 --- a/os/ports/IAR/ARMCMx/chcore.h +++ b/os/ports/IAR/ARMCMx/chcore.h @@ -29,18 +29,22 @@ #ifndef _CHCORE_H_
#define _CHCORE_H_
-#include <intrinsics.h>
-
-#include "nvic.h"
-
/*===========================================================================*/
-/* Port constants. */
+/* Port constants (common). */
/*===========================================================================*/
-#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
-#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */
-#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
-#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */
+/* Added to make the header stand-alone when included from asm.*/
+#ifndef FALSE
+#define FALSE 0
+#endif
+#ifndef TRUE
+#define TRUE (!FALSE)
+#endif
+
+#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
+#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */
+#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
+#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */
/* Inclusion of the Cortex-Mx implementation specific parameters.*/
#include "cmparams.h"
@@ -53,36 +57,26 @@ #error "unknown or unsupported Cortex-M model"
#endif
-/*===========================================================================*/
-/* Port statically derived parameters. */
-/*===========================================================================*/
-
/**
* @brief Total priority levels.
*/
-#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS)
+#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS)
/**
* @brief Minimum priority level.
* @details This minimum priority level is calculated from the number of
* priority bits supported by the specific Cortex-Mx implementation.
*/
-#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1)
+#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1)
/**
* @brief Maximum priority level.
* @details The maximum allowed priority level is always zero.
*/
-#define CORTEX_MAXIMUM_PRIORITY 0
-
-/**
- * @brief Disabled value for BASEPRI register.
- * @note ARMv7-M architecture only.
- */
-#define CORTEX_BASEPRI_DISABLED 0
+#define CORTEX_MAXIMUM_PRIORITY 0
/*===========================================================================*/
-/* Port macros. */
+/* Port macros (common). */
/*===========================================================================*/
/**
@@ -98,75 +92,56 @@ ((n) << (8 - CORTEX_PRIORITY_BITS))
/*===========================================================================*/
-/* Port configurable parameters. */
+/* Port configurable parameters (common). */
/*===========================================================================*/
/**
- * @brief Enables the use of the WFI instruction in the idle thread loop.
+ * @brief Stack size for the system idle thread.
+ * @details This size depends on the idle thread implementation, usually
+ * the idle thread should take no more space than those reserved
+ * by @p PORT_INT_REQUIRED_STACK.
+ * @note In this port it is set to 16 because the idle thread does have
+ * a stack frame when compiling without optimizations. You may
+ * reduce this value to zero when compiling with optimizations.
*/
-#ifndef CORTEX_ENABLE_WFI_IDLE
-#define CORTEX_ENABLE_WFI_IDLE FALSE
+#ifndef PORT_IDLE_THREAD_STACK_SIZE
+#define PORT_IDLE_THREAD_STACK_SIZE 16
#endif
/**
- * @brief SYSTICK handler priority.
- * @note The default SYSTICK handler priority is calculated as the priority
- * level in the middle of the numeric priorities range.
+ * @brief Per-thread stack overhead for interrupts servicing.
+ * @details This constant is used in the calculation of the correct working
+ * area size.
+ * This value can be zero on those architecture where there is a
+ * separate interrupt stack and the stack space between @p intctx and
+ * @p extctx is known to be zero.
+ * @note In this port it is conservatively set to 16 because the function
+ * @p chSchDoRescheduleI() can have a stack frame, expecially with
+ * compiler optimizations disabled.
*/
-#ifndef CORTEX_PRIORITY_SYSTICK
-#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1)
-#else
-/* If it is externally redefined then better perform a validity check on it.*/
-#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)
-#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"
-#endif
+#ifndef PORT_INT_REQUIRED_STACK
+#define PORT_INT_REQUIRED_STACK 16
#endif
/**
- * @brief SVCALL handler priority.
- * @note The default SVCALL handler priority is calculated as
- * @p CORTEX_MAXIMUM_PRIORITY+1, in the ARMv7-M port this reserves
- * the @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts
- * priority level.
- * @note The SVCALL vector is only used in the ARMv7-M port, it is available
- * to user in the ARMv6-M port.
+ * @brief Enables the use of the WFI instruction in the idle thread loop.
*/
-#ifndef CORTEX_PRIORITY_SVCALL
-#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1)
-#else
-/* If it is externally redefined then better perform a validity check on it.*/
-#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)
-#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"
-#endif
+#ifndef CORTEX_ENABLE_WFI_IDLE
+#define CORTEX_ENABLE_WFI_IDLE FALSE
#endif
/**
- * @brief PENDSV handler priority.
- * @note The default PENDSV handler priority is set at the
- * @p CORTEX_MINIMUM_PRIORITY priority level.
- * @note The PENDSV vector is only used in the ARMv7-M legacy port, it is
- * available to user in the ARMv6-M and ARMv7-M ports.
- * @note In the ARMv7-M legacy port this value should be not changed from
- * the minimum priority level.
+ * @brief SYSTICK handler priority.
+ * @note The default SYSTICK handler priority is calculated as the priority
+ * level in the middle of the numeric priorities range.
*/
-#ifndef CORTEX_PRIORITY_PENDSV
-#define CORTEX_PRIORITY_PENDSV CORTEX_MINIMUM_PRIORITY
+#ifndef CORTEX_PRIORITY_SYSTICK
+#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1)
#else
/* If it is externally redefined then better perform a validity check on it.*/
-#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_PENDSV)
-#error "invalid priority level specified for CORTEX_PRIORITY_PENDSV"
-#endif
+#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)
+#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"
#endif
-
-/**
- * @brief BASEPRI level within kernel lock.
- * @note This value must not mask the SVCALL priority level or the
- * kernel would hard fault.
- * @note ARMv7-M architecture only.
- */
-#ifndef CORTEX_BASEPRI_KERNEL
-#define CORTEX_BASEPRI_KERNEL \
- CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL+1)
#endif
/**
@@ -177,11 +152,15 @@ * @note Allowed values are 32 or 64.
*/
#ifndef CORTEX_STACK_ALIGNMENT
-#define CORTEX_STACK_ALIGNMENT 64
+#define CORTEX_STACK_ALIGNMENT 64
#endif
/*===========================================================================*/
-/* Port exported info. */
+/* Port derived parameters (common). */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Port exported info (common). */
/*===========================================================================*/
/**
@@ -189,62 +168,27 @@ */
#define CH_ARCHITECTURE_ARM
-#if defined(__DOXYGEN__)
/**
- * @brief Macro defining the specific ARM architecture.
- * @note This macro is for documentation only, the real name changes
- * depending on the selected architecture, the possible names are:
- * - CH_ARCHITECTURE_ARM_v6M.
- * - CH_ARCHITECTURE_ARM_v7M.
- * .
+ * @brief Name of the compiler supported by this port.
*/
-#define CH_ARCHITECTURE_ARM_vxm
-
-/**
- * @brief Name of the implemented architecture.
- * @note The value is for documentation only, the real value changes
- * depending on the selected architecture, the possible values are:
- * - "ARMv6-M".
- * - "ARMv7-M".
- * - "ARMv7-ME".
- * .
- */
-#define CH_ARCHITECTURE_NAME "ARMvx-M"
-
-/**
- * @brief Name of the architecture variant (optional).
- * @note The value is for documentation only, the real value changes
- * depending on the selected architecture, the possible values are:
- * - "Cortex-M0"
- * - "Cortex-M1"
- * - "Cortex-M3"
- * - "Cortex-M4"
- * .
- */
-#define CH_CORE_VARIANT_NAME "Cortex-Mx"
-
-#elif CORTEX_MODEL == CORTEX_M4
-#define CH_ARCHITECTURE_ARM_v7M
-#define CH_ARCHITECTURE_NAME "ARMv7-ME"
-#define CH_CORE_VARIANT_NAME "Cortex-M4"
-#elif CORTEX_MODEL == CORTEX_M3
-#define CH_ARCHITECTURE_ARM_v7M
-#define CH_ARCHITECTURE_NAME "ARMv7-M"
-#define CH_CORE_VARIANT_NAME "Cortex-M3"
-#elif CORTEX_MODEL == CORTEX_M1
-#define CH_ARCHITECTURE_ARM_v6M
-#define CH_ARCHITECTURE_NAME "ARMv6-M"
-#define CH_CORE_VARIANT_NAME "Cortex-M1"
-#elif CORTEX_MODEL == CORTEX_M0
-#define CH_ARCHITECTURE_ARM_v6M
-#define CH_ARCHITECTURE_NAME "ARMv6-M"
-#define CH_CORE_VARIANT_NAME "Cortex-M0"
-#endif
+#define CH_COMPILER_NAME "IAR"
/*===========================================================================*/
/* Port implementation part (common). */
/*===========================================================================*/
+/* Includes the sub-architecture-specific part.*/
+#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1)
+#include "chcore_v6m.h"
+#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4)
+#include "chcore_v7m.h"
+#endif
+
+#if !defined(_FROM_ASM_)
+
+#include <intrinsics.h>
+#include "nvic.h"
+
/**
* @brief Stack and memory alignment enforcement.
*/
@@ -256,11 +200,6 @@ typedef uint32_t stkalign_t; #error "invalid stack alignment selected"
#endif
-/**
- * @brief Generic ARM register.
- */
-typedef void *regarm_t;
-
#if defined(__DOXYGEN__)
/**
* @brief Interrupt saved context.
@@ -292,6 +231,20 @@ struct context { };
/**
+ * @brief Platform dependent part of the @p chThdCreateI() API.
+ * @details This code usually setup the context switching frame represented
+ * by an @p intctx structure.
+ */
+#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
+ tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \
+ wsize - \
+ sizeof(struct intctx)); \
+ tp->p_ctx.r13->r4 = (void *)pf; \
+ tp->p_ctx.r13->r5 = (void *)arg; \
+ tp->p_ctx.r13->lr = (void *)_port_thread_start; \
+}
+
+/**
* @brief Enforces a correct alignment for a stack area size value.
*/
#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
@@ -299,9 +252,9 @@ struct context { /**
* @brief Computes the thread working area global size.
*/
-#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
- sizeof(struct intctx) + \
- sizeof(struct extctx) + \
+#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
+ sizeof(struct intctx) + \
+ sizeof(struct extctx) + \
(n) + (PORT_INT_REQUIRED_STACK))
/**
@@ -311,12 +264,7 @@ struct context { */
#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
-/* Includes the architecture-specific implementation part.*/
-#if defined(CH_ARCHITECTURE_ARM_v6M)
-#include "chcore_v6m.h"
-#elif defined(CH_ARCHITECTURE_ARM_v7M)
-#include "chcore_v7m.h"
-#endif
+#endif /* _FROM_ASM_ */
#endif /* _CHCORE_H_ */
diff --git a/os/ports/IAR/ARMCMx/chcore_v6m.h b/os/ports/IAR/ARMCMx/chcore_v6m.h index 41b656532..8ab9ff583 100644 --- a/os/ports/IAR/ARMCMx/chcore_v6m.h +++ b/os/ports/IAR/ARMCMx/chcore_v6m.h @@ -30,9 +30,59 @@ #define _CHCORE_V6M_H_
/*===========================================================================*/
+/* Port constants. */
+/*===========================================================================*/
+
+/**
+ * @brief PendSV priority level.
+ * @note This priority is enforced to be equal to @p 0,
+ * this handler always have the highest priority that cannot preempt
+ * the kernel.
+ */
+#define CORTEX_PRIORITY_PENDSV 0
+
+/*===========================================================================*/
+/* Port configurable parameters. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Port derived parameters. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Port exported info. */
+/*===========================================================================*/
+
+/**
+ * @brief Macro defining the specific ARM architecture.
+ */
+#define CH_ARCHITECTURE_ARM_v6M
+
+/**
+ * @brief Name of the implemented architecture.
+ */
+#define CH_ARCHITECTURE_NAME "ARMv6-M"
+
+/**
+ * @brief Name of the architecture variant.
+ */
+#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__)
+#define CH_CORE_VARIANT_NAME "Cortex-M0"
+#elif (CORTEX_MODEL == CORTEX_M1)
+#define CH_CORE_VARIANT_NAME "Cortex-M1"
+#endif
+
+/*===========================================================================*/
/* Port implementation part. */
/*===========================================================================*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief Generic ARM register.
+ */
+typedef void *regarm_t;
+
#if !defined(__DOXYGEN__)
struct extctx {
regarm_t r0;
@@ -59,48 +109,6 @@ struct intctx { #endif
/**
- * @brief Platform dependent part of the @p chThdInit() API.
- * @details This code usually setup the context switching frame represented
- * by an @p intctx structure.
- */
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
- tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \
- wsize - \
- sizeof(struct intctx)); \
- tp->p_ctx.r13->r4 = (void *)pf; \
- tp->p_ctx.r13->r5 = arg; \
- tp->p_ctx.r13->lr = (void *)_port_thread_start; \
-}
-
-/**
- * @brief Stack size for the system idle thread.
- * @details This size depends on the idle thread implementation, usually
- * the idle thread should take no more space than those reserved
- * by @p PORT_INT_REQUIRED_STACK.
- * @note In this port it is set to 8 because the idle thread does have
- * a stack frame when compiling without optimizations. You may
- * reduce this value to zero when compiling with optimizations.
- */
-#ifndef PORT_IDLE_THREAD_STACK_SIZE
-#define PORT_IDLE_THREAD_STACK_SIZE 16
-#endif
-
-/**
- * @brief Per-thread stack overhead for interrupts servicing.
- * @details This constant is used in the calculation of the correct working
- * area size.
- * This value can be zero on those architecture where there is a
- * separate interrupt stack and the stack space between @p intctx and
- * @p extctx is known to be zero.
- * @note In this port it is conservatively set to 16 because the function
- * @p chSchDoRescheduleI() can have a stack frame, expecially with
- * compiler optimizations disabled.
- */
-#ifndef PORT_INT_REQUIRED_STACK
-#define PORT_INT_REQUIRED_STACK 16
-#endif
-
-/**
* @brief IRQ prologue code.
* @details This macro must be inserted at the start of all IRQ handlers
* enabled to invoke system APIs.
@@ -133,6 +141,8 @@ struct intctx { */
#define port_init() { \
SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \
+ NVICSetSystemHandlerPriority(HANDLER_PENDSV, \
+ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \
NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \
}
@@ -230,6 +240,8 @@ extern "C" { }
#endif
+#endif /* _FROM_ASM_ */
+
#endif /* _CHCORE_V6M_H_ */
/** @} */
diff --git a/os/ports/IAR/ARMCMx/chcore_v7m.h b/os/ports/IAR/ARMCMx/chcore_v7m.h index 31be9a04a..ac757a563 100644 --- a/os/ports/IAR/ARMCMx/chcore_v7m.h +++ b/os/ports/IAR/ARMCMx/chcore_v7m.h @@ -30,9 +30,111 @@ #define _CHCORE_V7M_H_
/*===========================================================================*/
+/* Port constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Disabled value for BASEPRI register.
+ */
+#define CORTEX_BASEPRI_DISABLED 0
+
+/*===========================================================================*/
+/* Port configurable parameters. */
+/*===========================================================================*/
+
+/**
+ * @brief Simplified priority handling flag.
+ * @details Activating this option will make the Kernel work in compact mode.
+ */
+#ifndef CORTEX_SIMPLIFIED_PRIORITY
+#define CORTEX_SIMPLIFIED_PRIORITY FALSE
+#endif
+
+/**
+ * @brief SVCALL handler priority.
+ * @note The default SVCALL handler priority is defaulted to
+ * @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the
+ * @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts
+ * priority level.
+ */
+#ifndef CORTEX_PRIORITY_SVCALL
+#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1)
+#else
+/* If it is externally redefined then better perform a validity check on it.*/
+#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)
+#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"
+#endif
+#endif
+
+/*===========================================================================*/
+/* Port derived parameters. */
+/*===========================================================================*/
+
+/**
+ * @brief BASEPRI level within kernel lock.
+ * @note In compact kernel mode this constant value is enforced to zero.
+ */
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+#define CORTEX_BASEPRI_KERNEL \
+ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL+1)
+#else
+#define CORTEX_BASEPRI_KERNEL 0
+#endif
+
+/**
+ * @brief PendSV priority level.
+ * @note This priority is enforced to be equal to @p CORTEX_BASEPRI_KERNEL,
+ * this handler always have the highest priority that cannot preempt
+ * the kernel.
+ */
+#define CORTEX_PRIORITY_PENDSV CORTEX_BASEPRI_KERNEL
+
+/*===========================================================================*/
+/* Port exported info. */
+/*===========================================================================*/
+
+#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
+/**
+ * @brief Macro defining the specific ARM architecture.
+ */
+#define CH_ARCHITECTURE_ARM_v7M
+
+/**
+ * @brief Name of the implemented architecture.
+ */
+#define CH_ARCHITECTURE_NAME "ARMv7-M"
+
+/**
+ * @brief Name of the architecture variant.
+ */
+#define CH_CORE_VARIANT_NAME "Cortex-M3"
+
+#elif (CORTEX_MODEL == CORTEX_M4)
+#define CH_ARCHITECTURE_ARM_v7ME
+#define CH_ARCHITECTURE_NAME "ARMv7-ME"
+#define CH_CORE_VARIANT_NAME "Cortex-M4"
+#endif
+
+/**
+ * @brief Port-specific information string.
+ */
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+#define CH_PORT_INFO "Advanced kernel mode"
+#else
+#define CH_PORT_INFO "Compact kernel mode"
+#endif
+
+/*===========================================================================*/
/* Port implementation part. */
/*===========================================================================*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief Generic ARM register.
+ */
+typedef void *regarm_t;
+
#if !defined(__DOXYGEN__)
struct extctx {
regarm_t r0;
@@ -59,48 +161,6 @@ struct intctx { #endif
/**
- * @brief Platform dependent part of the @p chThdCreateI() API.
- * @details This code usually setup the context switching frame represented
- * by an @p intctx structure.
- */
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
- tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \
- wsize - \
- sizeof(struct intctx)); \
- tp->p_ctx.r13->r4 = (void *)pf; \
- tp->p_ctx.r13->r5 = arg; \
- tp->p_ctx.r13->lr = (void *)_port_thread_start; \
-}
-
-/**
- * @brief Stack size for the system idle thread.
- * @details This size depends on the idle thread implementation, usually
- * the idle thread should take no more space than those reserved
- * by @p PORT_INT_REQUIRED_STACK.
- * @note In this port it is set to 16 because the idle thread does have
- * a stack frame when compiling without optimizations. You may
- * reduce this value to zero when compiling with optimizations.
- */
-#ifndef PORT_IDLE_THREAD_STACK_SIZE
-#define PORT_IDLE_THREAD_STACK_SIZE 16
-#endif
-
-/**
- * @brief Per-thread stack overhead for interrupts servicing.
- * @details This constant is used in the calculation of the correct working
- * area size.
- * This value can be zero on those architecture where there is a
- * separate interrupt stack and the stack space between @p intctx and
- * @p extctx is known to be zero.
- * @note In this port it is conservatively set to 16 because the function
- * @p chSchDoRescheduleI() can have a stack frame, expecially with
- * compiler optimizations disabled.
- */
-#ifndef PORT_INT_REQUIRED_STACK
-#define PORT_INT_REQUIRED_STACK 16
-#endif
-
-/**
* @brief IRQ prologue code.
* @details This macro must be inserted at the start of all IRQ handlers
* enabled to invoke system APIs.
@@ -135,6 +195,8 @@ struct intctx { SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \
NVICSetSystemHandlerPriority(HANDLER_SVCALL, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); \
+ NVICSetSystemHandlerPriority(HANDLER_PENDSV, \
+ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \
NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \
}
@@ -145,7 +207,11 @@ struct intctx { * more actions.
* @note In this port this it raises the base priority to kernel level.
*/
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
#define port_lock() __set_BASEPRI(CORTEX_BASEPRI_KERNEL)
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+#define port_lock() __disable_interrupt()
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
/**
* @brief Kernel-unlock action.
@@ -153,7 +219,11 @@ struct intctx { * more actions.
* @note In this port this it lowers the base priority to user level.
*/
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
#define port_unlock() __set_BASEPRI(CORTEX_BASEPRI_DISABLED)
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+#define port_unlock() __enable_interrupt()
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
/**
* @brief Kernel-lock action from an interrupt handler.
@@ -186,19 +256,27 @@ struct intctx { * @note Interrupt sources above kernel level remains enabled.
* @note In this port it raises/lowers the base priority to kernel level.
*/
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
#define port_suspend() { \
__set_BASEPRI(CORTEX_BASEPRI_KERNEL); \
__enable_interrupt(); \
}
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+#define port_suspend() __disable_interrupt()
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
/**
* @brief Enables all the interrupt sources.
* @note In this port it lowers the base priority to user level.
*/
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
#define port_enable() { \
__set_BASEPRI(CORTEX_BASEPRI_DISABLED); \
__enable_interrupt(); \
}
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+#define port_enable() __enable_interrupt()
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
/**
* @brief Enters an architecture-dependent IRQ-waiting mode.
@@ -246,6 +324,8 @@ extern "C" { }
#endif
+#endif /* _FROM_ASM_ */
+
#endif /* _CHCORE_V7M_H_ */
/** @} */
diff --git a/os/ports/RVCT/ARMCMx/chcore.h b/os/ports/RVCT/ARMCMx/chcore.h index 767f71923..42b397e93 100644 --- a/os/ports/RVCT/ARMCMx/chcore.h +++ b/os/ports/RVCT/ARMCMx/chcore.h @@ -29,16 +29,22 @@ #ifndef _CHCORE_H_
#define _CHCORE_H_
-#include "nvic.h"
-
/*===========================================================================*/
-/* Port constants. */
+/* Port constants (common). */
/*===========================================================================*/
-#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
-#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */
-#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
-#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */
+/* Added to make the header stand-alone when included from asm.*/
+#ifndef FALSE
+#define FALSE 0
+#endif
+#ifndef TRUE
+#define TRUE (!FALSE)
+#endif
+
+#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
+#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */
+#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
+#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */
/* Inclusion of the Cortex-Mx implementation specific parameters.*/
#include "cmparams.h"
@@ -51,36 +57,26 @@ #error "unknown or unsupported Cortex-M model"
#endif
-/*===========================================================================*/
-/* Port statically derived parameters. */
-/*===========================================================================*/
-
/**
* @brief Total priority levels.
*/
-#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS)
+#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS)
/**
* @brief Minimum priority level.
* @details This minimum priority level is calculated from the number of
* priority bits supported by the specific Cortex-Mx implementation.
*/
-#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1)
+#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1)
/**
* @brief Maximum priority level.
* @details The maximum allowed priority level is always zero.
*/
-#define CORTEX_MAXIMUM_PRIORITY 0
-
-/**
- * @brief Disabled value for BASEPRI register.
- * @note ARMv7-M architecture only.
- */
-#define CORTEX_BASEPRI_DISABLED 0
+#define CORTEX_MAXIMUM_PRIORITY 0
/*===========================================================================*/
-/* Port macros. */
+/* Port macros (common). */
/*===========================================================================*/
/**
@@ -96,75 +92,56 @@ ((n) << (8 - CORTEX_PRIORITY_BITS))
/*===========================================================================*/
-/* Port configurable parameters. */
+/* Port configurable parameters (common). */
/*===========================================================================*/
/**
- * @brief Enables the use of the WFI instruction in the idle thread loop.
+ * @brief Stack size for the system idle thread.
+ * @details This size depends on the idle thread implementation, usually
+ * the idle thread should take no more space than those reserved
+ * by @p PORT_INT_REQUIRED_STACK.
+ * @note In this port it is set to 16 because the idle thread does have
+ * a stack frame when compiling without optimizations. You may
+ * reduce this value to zero when compiling with optimizations.
*/
-#ifndef CORTEX_ENABLE_WFI_IDLE
-#define CORTEX_ENABLE_WFI_IDLE FALSE
+#ifndef PORT_IDLE_THREAD_STACK_SIZE
+#define PORT_IDLE_THREAD_STACK_SIZE 16
#endif
/**
- * @brief SYSTICK handler priority.
- * @note The default SYSTICK handler priority is calculated as the priority
- * level in the middle of the numeric priorities range.
+ * @brief Per-thread stack overhead for interrupts servicing.
+ * @details This constant is used in the calculation of the correct working
+ * area size.
+ * This value can be zero on those architecture where there is a
+ * separate interrupt stack and the stack space between @p intctx and
+ * @p extctx is known to be zero.
+ * @note In this port it is conservatively set to 16 because the function
+ * @p chSchDoRescheduleI() can have a stack frame, expecially with
+ * compiler optimizations disabled.
*/
-#ifndef CORTEX_PRIORITY_SYSTICK
-#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1)
-#else
-/* If it is externally redefined then better perform a validity check on it.*/
-#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)
-#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"
-#endif
+#ifndef PORT_INT_REQUIRED_STACK
+#define PORT_INT_REQUIRED_STACK 16
#endif
/**
- * @brief SVCALL handler priority.
- * @note The default SVCALL handler priority is calculated as
- * @p CORTEX_MAXIMUM_PRIORITY+1, in the ARMv7-M port this reserves
- * the @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts
- * priority level.
- * @note The SVCALL vector is only used in the ARMv7-M port, it is available
- * to user in the ARMv6-M port.
+ * @brief Enables the use of the WFI instruction in the idle thread loop.
*/
-#ifndef CORTEX_PRIORITY_SVCALL
-#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1)
-#else
-/* If it is externally redefined then better perform a validity check on it.*/
-#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)
-#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"
-#endif
+#ifndef CORTEX_ENABLE_WFI_IDLE
+#define CORTEX_ENABLE_WFI_IDLE FALSE
#endif
/**
- * @brief PENDSV handler priority.
- * @note The default PENDSV handler priority is set at the
- * @p CORTEX_MINIMUM_PRIORITY priority level.
- * @note The PENDSV vector is only used in the ARMv7-M legacy port, it is
- * available to user in the ARMv6-M and ARMv7-M ports.
- * @note In the ARMv7-M legacy port this value should be not changed from
- * the minimum priority level.
+ * @brief SYSTICK handler priority.
+ * @note The default SYSTICK handler priority is calculated as the priority
+ * level in the middle of the numeric priorities range.
*/
-#ifndef CORTEX_PRIORITY_PENDSV
-#define CORTEX_PRIORITY_PENDSV CORTEX_MINIMUM_PRIORITY
+#ifndef CORTEX_PRIORITY_SYSTICK
+#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1)
#else
/* If it is externally redefined then better perform a validity check on it.*/
-#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_PENDSV)
-#error "invalid priority level specified for CORTEX_PRIORITY_PENDSV"
-#endif
+#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)
+#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"
#endif
-
-/**
- * @brief BASEPRI level within kernel lock.
- * @note This value must not mask the SVCALL priority level or the
- * kernel would hard fault.
- * @note ARMv7-M architecture only.
- */
-#ifndef CORTEX_BASEPRI_KERNEL
-#define CORTEX_BASEPRI_KERNEL \
- CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL+1)
#endif
/**
@@ -175,11 +152,15 @@ * @note Allowed values are 32 or 64.
*/
#ifndef CORTEX_STACK_ALIGNMENT
-#define CORTEX_STACK_ALIGNMENT 64
+#define CORTEX_STACK_ALIGNMENT 64
#endif
/*===========================================================================*/
-/* Port exported info. */
+/* Port derived parameters (common). */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Port exported info (common). */
/*===========================================================================*/
/**
@@ -187,62 +168,26 @@ */
#define CH_ARCHITECTURE_ARM
-#if defined(__DOXYGEN__)
-/**
- * @brief Macro defining the specific ARM architecture.
- * @note This macro is for documentation only, the real name changes
- * depending on the selected architecture, the possible names are:
- * - CH_ARCHITECTURE_ARM_v6M.
- * - CH_ARCHITECTURE_ARM_v7M.
- * .
- */
-#define CH_ARCHITECTURE_ARM_vxm
-
/**
- * @brief Name of the implemented architecture.
- * @note The value is for documentation only, the real value changes
- * depending on the selected architecture, the possible values are:
- * - "ARMv6-M".
- * - "ARMv7-M".
- * - "ARMv7-ME".
- * .
+ * @brief Name of the compiler supported by this port.
*/
-#define CH_ARCHITECTURE_NAME "ARMvx-M"
-
-/**
- * @brief Name of the architecture variant (optional).
- * @note The value is for documentation only, the real value changes
- * depending on the selected architecture, the possible values are:
- * - "Cortex-M0"
- * - "Cortex-M1"
- * - "Cortex-M3"
- * - "Cortex-M4"
- * .
- */
-#define CH_CORE_VARIANT_NAME "Cortex-Mx"
-
-#elif CORTEX_MODEL == CORTEX_M4
-#define CH_ARCHITECTURE_ARM_v7M
-#define CH_ARCHITECTURE_NAME "ARMv7-ME"
-#define CH_CORE_VARIANT_NAME "Cortex-M4"
-#elif CORTEX_MODEL == CORTEX_M3
-#define CH_ARCHITECTURE_ARM_v7M
-#define CH_ARCHITECTURE_NAME "ARMv7-M"
-#define CH_CORE_VARIANT_NAME "Cortex-M3"
-#elif CORTEX_MODEL == CORTEX_M1
-#define CH_ARCHITECTURE_ARM_v6M
-#define CH_ARCHITECTURE_NAME "ARMv6-M"
-#define CH_CORE_VARIANT_NAME "Cortex-M1"
-#elif CORTEX_MODEL == CORTEX_M0
-#define CH_ARCHITECTURE_ARM_v6M
-#define CH_ARCHITECTURE_NAME "ARMv6-M"
-#define CH_CORE_VARIANT_NAME "Cortex-M0"
-#endif
+#define CH_COMPILER_NAME "RVCT"
/*===========================================================================*/
/* Port implementation part (common). */
/*===========================================================================*/
+/* Includes the sub-architecture-specific part.*/
+#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1)
+#include "chcore_v6m.h"
+#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4)
+#include "chcore_v7m.h"
+#endif
+
+#if !defined(_FROM_ASM_)
+
+#include "nvic.h"
+
/**
* @brief Stack and memory alignment enforcement.
*/
@@ -259,11 +204,6 @@ typedef uint32_t stkalign_t __attribute__ ((aligned (4))); #error "invalid stack alignment selected"
#endif
-/**
- * @brief Generic ARM register.
- */
-typedef void *regarm_t;
-
#if defined(__DOXYGEN__)
/**
* @brief Interrupt saved context.
@@ -295,6 +235,20 @@ struct context { };
/**
+ * @brief Platform dependent part of the @p chThdCreateI() API.
+ * @details This code usually setup the context switching frame represented
+ * by an @p intctx structure.
+ */
+#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
+ tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \
+ wsize - \
+ sizeof(struct intctx)); \
+ tp->p_ctx.r13->r4 = (void *)pf; \
+ tp->p_ctx.r13->r5 = (void *)arg; \
+ tp->p_ctx.r13->lr = (void *)_port_thread_start; \
+}
+
+/**
* @brief Enforces a correct alignment for a stack area size value.
*/
#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
@@ -302,9 +256,9 @@ struct context { /**
* @brief Computes the thread working area global size.
*/
-#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
- sizeof(struct intctx) + \
- sizeof(struct extctx) + \
+#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
+ sizeof(struct intctx) + \
+ sizeof(struct extctx) + \
(n) + (PORT_INT_REQUIRED_STACK))
/**
@@ -314,12 +268,7 @@ struct context { */
#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
-/* Includes the architecture-specific implementation part.*/
-#if defined(CH_ARCHITECTURE_ARM_v6M)
-#include "chcore_v6m.h"
-#elif defined(CH_ARCHITECTURE_ARM_v7M)
-#include "chcore_v7m.h"
-#endif
+#endif /* _FROM_ASM_ */
#endif /* _CHCORE_H_ */
diff --git a/os/ports/RVCT/ARMCMx/chcore_v6m.h b/os/ports/RVCT/ARMCMx/chcore_v6m.h index 1c4af7da9..bff8c4fe4 100644 --- a/os/ports/RVCT/ARMCMx/chcore_v6m.h +++ b/os/ports/RVCT/ARMCMx/chcore_v6m.h @@ -30,9 +30,59 @@ #define _CHCORE_V6M_H_
/*===========================================================================*/
+/* Port constants. */
+/*===========================================================================*/
+
+/**
+ * @brief PendSV priority level.
+ * @note This priority is enforced to be equal to @p 0,
+ * this handler always have the highest priority that cannot preempt
+ * the kernel.
+ */
+#define CORTEX_PRIORITY_PENDSV 0
+
+/*===========================================================================*/
+/* Port configurable parameters. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Port derived parameters. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Port exported info. */
+/*===========================================================================*/
+
+/**
+ * @brief Macro defining the specific ARM architecture.
+ */
+#define CH_ARCHITECTURE_ARM_v6M
+
+/**
+ * @brief Name of the implemented architecture.
+ */
+#define CH_ARCHITECTURE_NAME "ARMv6-M"
+
+/**
+ * @brief Name of the architecture variant.
+ */
+#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__)
+#define CH_CORE_VARIANT_NAME "Cortex-M0"
+#elif (CORTEX_MODEL == CORTEX_M1)
+#define CH_CORE_VARIANT_NAME "Cortex-M1"
+#endif
+
+/*===========================================================================*/
/* Port implementation part. */
/*===========================================================================*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief Generic ARM register.
+ */
+typedef void *regarm_t;
+
#if !defined(__DOXYGEN__)
struct extctx {
regarm_t r0;
@@ -59,48 +109,6 @@ struct intctx { #endif
/**
- * @brief Platform dependent part of the @p chThdInit() API.
- * @details This code usually setup the context switching frame represented
- * by an @p intctx structure.
- */
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
- tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \
- wsize - \
- sizeof(struct intctx)); \
- tp->p_ctx.r13->r4 = (void *)pf; \
- tp->p_ctx.r13->r5 = arg; \
- tp->p_ctx.r13->lr = (void *)_port_thread_start; \
-}
-
-/**
- * @brief Stack size for the system idle thread.
- * @details This size depends on the idle thread implementation, usually
- * the idle thread should take no more space than those reserved
- * by @p PORT_INT_REQUIRED_STACK.
- * @note In this port it is set to 8 because the idle thread does have
- * a stack frame when compiling without optimizations. You may
- * reduce this value to zero when compiling with optimizations.
- */
-#ifndef PORT_IDLE_THREAD_STACK_SIZE
-#define PORT_IDLE_THREAD_STACK_SIZE 16
-#endif
-
-/**
- * @brief Per-thread stack overhead for interrupts servicing.
- * @details This constant is used in the calculation of the correct working
- * area size.
- * This value can be zero on those architecture where there is a
- * separate interrupt stack and the stack space between @p intctx and
- * @p extctx is known to be zero.
- * @note In this port it is conservatively set to 16 because the function
- * @p chSchDoRescheduleI() can have a stack frame, expecially with
- * compiler optimizations disabled.
- */
-#ifndef PORT_INT_REQUIRED_STACK
-#define PORT_INT_REQUIRED_STACK 16
-#endif
-
-/**
* @brief IRQ prologue code.
* @details This macro must be inserted at the start of all IRQ handlers
* enabled to invoke system APIs.
@@ -133,6 +141,8 @@ struct intctx { */
#define port_init() { \
SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \
+ NVICSetSystemHandlerPriority(HANDLER_PENDSV, \
+ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \
NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \
}
@@ -231,6 +241,8 @@ extern "C" { }
#endif
+#endif /* _FROM_ASM_ */
+
#endif /* _CHCORE_V6M_H_ */
/** @} */
diff --git a/os/ports/RVCT/ARMCMx/chcore_v7m.h b/os/ports/RVCT/ARMCMx/chcore_v7m.h index 7f7d8c5be..14b25fd8c 100644 --- a/os/ports/RVCT/ARMCMx/chcore_v7m.h +++ b/os/ports/RVCT/ARMCMx/chcore_v7m.h @@ -30,9 +30,111 @@ #define _CHCORE_V7M_H_
/*===========================================================================*/
+/* Port constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Disabled value for BASEPRI register.
+ */
+#define CORTEX_BASEPRI_DISABLED 0
+
+/*===========================================================================*/
+/* Port configurable parameters. */
+/*===========================================================================*/
+
+/**
+ * @brief Simplified priority handling flag.
+ * @details Activating this option will make the Kernel work in compact mode.
+ */
+#ifndef CORTEX_SIMPLIFIED_PRIORITY
+#define CORTEX_SIMPLIFIED_PRIORITY FALSE
+#endif
+
+/**
+ * @brief SVCALL handler priority.
+ * @note The default SVCALL handler priority is defaulted to
+ * @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the
+ * @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts
+ * priority level.
+ */
+#ifndef CORTEX_PRIORITY_SVCALL
+#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1)
+#else
+/* If it is externally redefined then better perform a validity check on it.*/
+#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)
+#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"
+#endif
+#endif
+
+/*===========================================================================*/
+/* Port derived parameters. */
+/*===========================================================================*/
+
+/**
+ * @brief BASEPRI level within kernel lock.
+ * @note In compact kernel mode this constant value is enforced to zero.
+ */
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+#define CORTEX_BASEPRI_KERNEL \
+ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL+1)
+#else
+#define CORTEX_BASEPRI_KERNEL 0
+#endif
+
+/**
+ * @brief PendSV priority level.
+ * @note This priority is enforced to be equal to @p CORTEX_BASEPRI_KERNEL,
+ * this handler always have the highest priority that cannot preempt
+ * the kernel.
+ */
+#define CORTEX_PRIORITY_PENDSV CORTEX_BASEPRI_KERNEL
+
+/*===========================================================================*/
+/* Port exported info. */
+/*===========================================================================*/
+
+#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
+/**
+ * @brief Macro defining the specific ARM architecture.
+ */
+#define CH_ARCHITECTURE_ARM_v7M
+
+/**
+ * @brief Name of the implemented architecture.
+ */
+#define CH_ARCHITECTURE_NAME "ARMv7-M"
+
+/**
+ * @brief Name of the architecture variant.
+ */
+#define CH_CORE_VARIANT_NAME "Cortex-M3"
+
+#elif (CORTEX_MODEL == CORTEX_M4)
+#define CH_ARCHITECTURE_ARM_v7ME
+#define CH_ARCHITECTURE_NAME "ARMv7-ME"
+#define CH_CORE_VARIANT_NAME "Cortex-M4"
+#endif
+
+/**
+ * @brief Port-specific information string.
+ */
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+#define CH_PORT_INFO "Advanced kernel mode"
+#else
+#define CH_PORT_INFO "Compact kernel mode"
+#endif
+
+/*===========================================================================*/
/* Port implementation part. */
/*===========================================================================*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief Generic ARM register.
+ */
+typedef void *regarm_t;
+
#if !defined(__DOXYGEN__)
struct extctx {
regarm_t r0;
@@ -59,48 +161,6 @@ struct intctx { #endif
/**
- * @brief Platform dependent part of the @p chThdCreateI() API.
- * @details This code usually setup the context switching frame represented
- * by an @p intctx structure.
- */
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
- tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \
- wsize - \
- sizeof(struct intctx)); \
- tp->p_ctx.r13->r4 = (void *)pf; \
- tp->p_ctx.r13->r5 = arg; \
- tp->p_ctx.r13->lr = (void *)_port_thread_start; \
-}
-
-/**
- * @brief Stack size for the system idle thread.
- * @details This size depends on the idle thread implementation, usually
- * the idle thread should take no more space than those reserved
- * by @p PORT_INT_REQUIRED_STACK.
- * @note In this port it is set to 16 because the idle thread does have
- * a stack frame when compiling without optimizations. You may
- * reduce this value to zero when compiling with optimizations.
- */
-#ifndef PORT_IDLE_THREAD_STACK_SIZE
-#define PORT_IDLE_THREAD_STACK_SIZE 16
-#endif
-
-/**
- * @brief Per-thread stack overhead for interrupts servicing.
- * @details This constant is used in the calculation of the correct working
- * area size.
- * This value can be zero on those architecture where there is a
- * separate interrupt stack and the stack space between @p intctx and
- * @p extctx is known to be zero.
- * @note In this port it is conservatively set to 16 because the function
- * @p chSchDoRescheduleI() can have a stack frame, expecially with
- * compiler optimizations disabled.
- */
-#ifndef PORT_INT_REQUIRED_STACK
-#define PORT_INT_REQUIRED_STACK 16
-#endif
-
-/**
* @brief IRQ prologue code.
* @details This macro must be inserted at the start of all IRQ handlers
* enabled to invoke system APIs.
@@ -135,6 +195,8 @@ struct intctx { SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \
NVICSetSystemHandlerPriority(HANDLER_SVCALL, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); \
+ NVICSetSystemHandlerPriority(HANDLER_PENDSV, \
+ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \
NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \
}
@@ -145,10 +207,14 @@ struct intctx { * more actions.
* @note In this port this it raises the base priority to kernel level.
*/
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
#define port_lock() { \
register uint32_t basepri __asm("basepri"); \
basepri = CORTEX_BASEPRI_KERNEL; \
}
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+#define port_lock() __disable_irq()
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
/**
* @brief Kernel-unlock action.
@@ -156,10 +222,14 @@ struct intctx { * more actions.
* @note In this port this it lowers the base priority to user level.
*/
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
#define port_unlock() { \
register uint32_t basepri __asm("basepri"); \
basepri = CORTEX_BASEPRI_DISABLED; \
}
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+#define port_unlock() __enable_irq()
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
/**
* @brief Kernel-lock action from an interrupt handler.
@@ -192,21 +262,28 @@ struct intctx { * @note Interrupt sources above kernel level remains enabled.
* @note In this port it raises/lowers the base priority to kernel level.
*/
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
#define port_suspend() { \
register uint32_t basepri __asm("basepri"); \
basepri = CORTEX_BASEPRI_KERNEL; \
- __enable_irq(); \
}
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+#define port_suspend() __disable_irq()
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
/**
* @brief Enables all the interrupt sources.
* @note In this port it lowers the base priority to user level.
*/
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
#define port_enable() { \
register uint32_t basepri __asm("basepri"); \
basepri = CORTEX_BASEPRI_DISABLED; \
__enable_irq(); \
}
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+#define port_enable() __enable_irq()
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
/**
* @brief Enters an architecture-dependent IRQ-waiting mode.
@@ -255,6 +332,8 @@ extern "C" { }
#endif
+#endif /* _FROM_ASM_ */
+
#endif /* _CHCORE_V7M_H_ */
/** @} */
diff --git a/readme.txt b/readme.txt index 851f2e0b0..c3cbb14ab 100644 --- a/readme.txt +++ b/readme.txt @@ -71,8 +71,12 @@ *****************************************************************************
*** 2.3.4 ***
+- FIX: Fixed wrong macro definition in ARMv6-M architecture files (bug
+ 3310084).
- NEW: Now the STM32 SDC driver supports unaligned buffers transparently.
Optimized the driver for single block read and write operations.
+- NEW: Finished the reorganization of the Cortex-Mx ports, now also the
+ IAR and RVCT ports support the new Compact mode.
*** 2.3.3 ***
- FIX: Fixed race condition in output queues (bug 3303908)(backported
|