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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2014-03-18 10:57:31 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2014-03-18 10:57:31 +0000 |
| commit | 13364b3ca951146a39a3f03ec7b6b36ca929d4bd (patch) | |
| tree | 2a24093a825b0899a83a82dd084197f4d7ad0908 | |
| parent | 3976d935b831fd5062b8c4a458d873392aadf164 (diff) | |
| download | ChibiOS-13364b3ca951146a39a3f03ec7b6b36ca929d4bd.tar.gz ChibiOS-13364b3ca951146a39a3f03ec7b6b36ca929d4bd.tar.bz2 ChibiOS-13364b3ca951146a39a3f03ec7b6b36ca929d4bd.zip | |
Fixed bug #474.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6782 35acf78f-673a-0410-8e92-d51de3d6d3f4
| -rw-r--r-- | os/hal/platforms/STM32F30x/hal_lld.h | 28 | ||||
| -rw-r--r-- | readme.txt | 2 |
2 files changed, 16 insertions, 14 deletions
diff --git a/os/hal/platforms/STM32F30x/hal_lld.h b/os/hal/platforms/STM32F30x/hal_lld.h index b2d138877..7085abb94 100644 --- a/os/hal/platforms/STM32F30x/hal_lld.h +++ b/os/hal/platforms/STM32F30x/hal_lld.h @@ -220,20 +220,20 @@ #define STM32_ADC12PRES_DIV64 (25 << 4) /**< ADC12 clock is PLL/64. */
#define STM32_ADC12PRES_DIV128 (26 << 4) /**< ADC12 clock is PLL/128. */
#define STM32_ADC12PRES_DIV256 (27 << 4) /**< ADC12 clock is PLL/256. */
-#define STM32_ADC34PRES_MASK (31 << 4) /**< ADC34 clock source mask. */
-#define STM32_ADC34PRES_NOCLOCK (0 << 4) /**< ADC34 clock is disabled. */
-#define STM32_ADC34PRES_DIV1 (16 << 4) /**< ADC34 clock is PLL/1. */
-#define STM32_ADC34PRES_DIV2 (17 << 4) /**< ADC34 clock is PLL/2. */
-#define STM32_ADC34PRES_DIV4 (18 << 4) /**< ADC34 clock is PLL/4. */
-#define STM32_ADC34PRES_DIV6 (19 << 4) /**< ADC34 clock is PLL/6. */
-#define STM32_ADC34PRES_DIV8 (20 << 4) /**< ADC34 clock is PLL/8. */
-#define STM32_ADC34PRES_DIV10 (21 << 4) /**< ADC34 clock is PLL/10. */
-#define STM32_ADC34PRES_DIV12 (22 << 4) /**< ADC34 clock is PLL/12. */
-#define STM32_ADC34PRES_DIV16 (23 << 4) /**< ADC34 clock is PLL/16. */
-#define STM32_ADC34PRES_DIV32 (24 << 4) /**< ADC34 clock is PLL/32. */
-#define STM32_ADC34PRES_DIV64 (25 << 4) /**< ADC34 clock is PLL/64. */
-#define STM32_ADC34PRES_DIV128 (26 << 4) /**< ADC34 clock is PLL/128. */
-#define STM32_ADC34PRES_DIV256 (27 << 4) /**< ADC34 clock is PLL/256. */
+#define STM32_ADC34PRES_MASK (31 << 9) /**< ADC34 clock source mask. */
+#define STM32_ADC34PRES_NOCLOCK (0 << 9) /**< ADC34 clock is disabled. */
+#define STM32_ADC34PRES_DIV1 (16 << 9) /**< ADC34 clock is PLL/1. */
+#define STM32_ADC34PRES_DIV2 (17 << 9) /**< ADC34 clock is PLL/2. */
+#define STM32_ADC34PRES_DIV4 (18 << 9) /**< ADC34 clock is PLL/4. */
+#define STM32_ADC34PRES_DIV6 (19 << 9) /**< ADC34 clock is PLL/6. */
+#define STM32_ADC34PRES_DIV8 (20 << 9) /**< ADC34 clock is PLL/8. */
+#define STM32_ADC34PRES_DIV10 (21 << 9) /**< ADC34 clock is PLL/10. */
+#define STM32_ADC34PRES_DIV12 (22 << 9) /**< ADC34 clock is PLL/12. */
+#define STM32_ADC34PRES_DIV16 (23 << 9) /**< ADC34 clock is PLL/16. */
+#define STM32_ADC34PRES_DIV32 (24 << 9) /**< ADC34 clock is PLL/32. */
+#define STM32_ADC34PRES_DIV64 (25 << 9) /**< ADC34 clock is PLL/64. */
+#define STM32_ADC34PRES_DIV128 (26 << 9) /**< ADC34 clock is PLL/128. */
+#define STM32_ADC34PRES_DIV256 (27 << 9) /**< ADC34 clock is PLL/256. */
/** @} */
/**
diff --git a/readme.txt b/readme.txt index cea77c750..fef427a81 100644 --- a/readme.txt +++ b/readme.txt @@ -89,6 +89,8 @@ *****************************************************************************
*** 2.7.0 ***
+- FIX: Fixed wrong ADC34 macros in STM32F30x HAL driver (bug #474)
+ (backported to 2.6.4).
- FIX: Fixed wrong TIM1 and TIM8 macros in STM32F30x HAL driver (bug #473)
(backported to 2.6.4).
- FIX: Fixed STM32 SDC driver clock activation issue (bug #464)(backported to
|