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This was removed in commit
ae7a4d40b84d8afc999691577210696f16e682f6#diff-7ddaa5ecc31109f41b7801dea2660b47
But I think is still necessary as the underlying rccEnableAHB macros
take parameter 'lp'. It seems to work for the F0xx series, because its
rccEnableAHB ignores the 'lp'. It is required when I tried to use the
CRC driver on a family that does require the 'lp' parameter in the lower
level macros.
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* STM32 DMA can only handle 65535 bytes per transfer so larger data sets
have to split up to be correctly handled when using DMA
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This patch includes a high level and two low level drivers.
The high level driver is enabled with flag HAL_USE_CRC
The low level drivers include:
* Hardware CRC for the STM32 cortex processor lines.(when supported)
* Enabled with flag STM32_CRC_USE_CRC1
* DMA is enabled with CRC_USE_DMA
* SYNC api will use DMA, but put calling thread to sleep
* ASYNC api enabled.
* DMA Disabled
* SYNC api spin while calculating CRC
* ASYNC api disabled
* Software CRC (3 modes)
* CRCSW_CRC32_TABLE - Enables crc32 with lookup table.
* CRCSW_CRC16_TABLE - Enables crc16 with lookup tables.
* CRCSW_PROGRAMMBLE - Enables any crc done with computation.
* Can calculate any crc configuration.
* CRC_USE_DMA obviously not support with software CRC
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