diff options
Diffstat (limited to 'demos/KINETIS/RT-MCHCK-K20-SPI')
| -rw-r--r-- | demos/KINETIS/RT-MCHCK-K20-SPI/Makefile | 9 | ||||
| -rw-r--r-- | demos/KINETIS/RT-MCHCK-K20-SPI/mcuconf.h | 17 |
2 files changed, 18 insertions, 8 deletions
diff --git a/demos/KINETIS/RT-MCHCK-K20-SPI/Makefile b/demos/KINETIS/RT-MCHCK-K20-SPI/Makefile index 34796ce..e38ba95 100644 --- a/demos/KINETIS/RT-MCHCK-K20-SPI/Makefile +++ b/demos/KINETIS/RT-MCHCK-K20-SPI/Makefile @@ -89,7 +89,7 @@ PROJECT = ch CHIBIOS = ../../../../ChibiOS-RT
CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
# Startup files.
-include $(CHIBIOS_CONTRIB)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_k20x.mk
+include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk
# HAL-OSAL files (optional).
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x/platform.mk
@@ -102,7 +102,8 @@ include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk include $(CHIBIOS)/test/rt/test.mk
# Define linker script file here
-LDSCRIPT= $(STARTUPLD)/MK20DX128.ld
+# Use BLDR4 for a 4k bootloader, BLDR3 for a 3k bootloader
+LDSCRIPT= $(STARTUPLD)/MK20DX128BLDR4.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
@@ -196,7 +197,9 @@ CPPWARN = -Wall -Wextra -Wundef #
# List all user C define here, like -D_DEBUG=1
-UDEFS =
+# VTOR moved to after the bootloader; use 0x1000 for a 4k bootloader,
+# 0xc00 for a 3k bootloader
+UDEFS = -DCORTEX_VTOR_INIT=0x00001000
# Define ASM defines here
UADEFS =
diff --git a/demos/KINETIS/RT-MCHCK-K20-SPI/mcuconf.h b/demos/KINETIS/RT-MCHCK-K20-SPI/mcuconf.h index 70b86cf..81cd6cc 100644 --- a/demos/KINETIS/RT-MCHCK-K20-SPI/mcuconf.h +++ b/demos/KINETIS/RT-MCHCK-K20-SPI/mcuconf.h @@ -32,27 +32,34 @@ #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
+#define KINETIS_CLKDIV1_OUTDIV1 1
+#define KINETIS_CLKDIV1_OUTDIV2 2
+#define KINETIS_CLKDIV1_OUTDIV4 2
+#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY/KINETIS_CLKDIV1_OUTDIV2)
+#define KINETIS_FLASHCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY/KINETIS_CLKDIV1_OUTDIV4)
/* FEE mode - 24 MHz with external 32.768 kHz crystal */
+/* not implemented */
#if 0
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */
-#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
-#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
#define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */
#define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */
#define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */
-#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4)
+#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
#endif /* 0 */
/* FEE mode - 48 MHz */
+/* not implemented */
#if 0
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
-#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
-#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
#endif /* 0 */
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