diff options
| -rw-r--r-- | os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c | 16 | ||||
| -rw-r--r-- | testhal/STM32/STM32F0xx/onewire/Makefile | 4 | ||||
| -rw-r--r-- | testhal/STM32/STM32F3xx/EEProm/halconf_community.h | 2 | ||||
| -rw-r--r-- | testhal/STM32/STM32F4xx/USB_HOST/mcuconf_community.h | 24 |
4 files changed, 23 insertions, 23 deletions
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c index ffc4992..6138481 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c @@ -194,24 +194,24 @@ void qei_lld_start(QEIDriver *qeip) { #endif
}
/* Timer configuration.*/
- qeip->tim->CR1 = 0; /* Initially stopped. */
+ qeip->tim->CR1 = 0; /* Initially stopped. */
qeip->tim->CR2 = 0;
qeip->tim->PSC = 0;
qeip->tim->DIER = 0;
- qeip->tim->ARR = 0xFFFF;
+ qeip->tim->ARR = 0xFFFF;
/* Set Capture Compare 1 and Capture Compare 2 as input. */
qeip->tim->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
if (qeip->config->mode == QEI_MODE_QUADRATURE) {
if (qeip->config->resolution == QEI_BOTH_EDGES)
- qeip->tim->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0;
+ qeip->tim->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0;
else
- qeip->tim->SMCR = TIM_SMCR_SMS_0;
+ qeip->tim->SMCR = TIM_SMCR_SMS_0;
} else {
/* Direction/Clock mode.
* Direction input on TI1, Clock input on TI2. */
- qeip->tim->SMCR = TIM_SMCR_SMS_0;
+ qeip->tim->SMCR = TIM_SMCR_SMS_0;
}
if (qeip->config->dirinv == QEI_DIRINV_TRUE)
@@ -230,7 +230,7 @@ void qei_lld_start(QEIDriver *qeip) { void qei_lld_stop(QEIDriver *qeip) {
if (qeip->state == QEI_READY) {
- qeip->tim->CR1 = 0; /* Timer disabled. */
+ qeip->tim->CR1 = 0; /* Timer disabled. */
/* Clock deactivation.*/
#if STM32_QEI_USE_TIM1
@@ -275,7 +275,7 @@ void qei_lld_stop(QEIDriver *qeip) { */
void qei_lld_enable(QEIDriver *qeip) {
- qeip->tim->CR1 = TIM_CR1_CEN; /* Timer enabled. */
+ qeip->tim->CR1 = TIM_CR1_CEN; /* Timer enabled. */
}
/**
@@ -287,7 +287,7 @@ void qei_lld_enable(QEIDriver *qeip) { */
void qei_lld_disable(QEIDriver *qeip) {
- qeip->tim->CR1 = 0; /* Timer disabled. */
+ qeip->tim->CR1 = 0; /* Timer disabled. */
}
#endif /* HAL_USE_QEI */
diff --git a/testhal/STM32/STM32F0xx/onewire/Makefile b/testhal/STM32/STM32F0xx/onewire/Makefile index e478e3a..de965e3 100644 --- a/testhal/STM32/STM32F0xx/onewire/Makefile +++ b/testhal/STM32/STM32F0xx/onewire/Makefile @@ -75,7 +75,7 @@ endif PROJECT = ch
# Imported source files and paths
-CHIBIOS = ../../../../../ChibiOS-RT +CHIBIOS = ../../../../../ChibiOS-RT
CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
TESTHAL = $(CHIBIOS_CONTRIB)/testhal/common/onewire
# Startup files.
@@ -104,7 +104,7 @@ CSRC = $(STARTUPSRC) \ $(TESTSRC) \
main.c \
$(TESTHAL)/testhal_onewire.c
-
+
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CPPSRC =
diff --git a/testhal/STM32/STM32F3xx/EEProm/halconf_community.h b/testhal/STM32/STM32F3xx/EEProm/halconf_community.h index f310a90..f0814c6 100644 --- a/testhal/STM32/STM32F3xx/EEProm/halconf_community.h +++ b/testhal/STM32/STM32F3xx/EEProm/halconf_community.h @@ -109,7 +109,7 @@ * @note Disabling this option saves both code and data space.
*/
#define EEPROM_USE_EE24XX TRUE
- /**
+/**
* @brief Enables 25xx series SPI eeprom device driver.
* @note Disabling this option saves both code and data space.
*/
diff --git a/testhal/STM32/STM32F4xx/USB_HOST/mcuconf_community.h b/testhal/STM32/STM32F4xx/USB_HOST/mcuconf_community.h index 56775af..5cb823a 100644 --- a/testhal/STM32/STM32F4xx/USB_HOST/mcuconf_community.h +++ b/testhal/STM32/STM32F4xx/USB_HOST/mcuconf_community.h @@ -48,19 +48,19 @@ /* * USBH driver system settings. */ -#define STM32_OTG1_CHANNELS_NUMBER 8 -#define STM32_OTG2_CHANNELS_NUMBER 12 +#define STM32_OTG1_CHANNELS_NUMBER 8 +#define STM32_OTG2_CHANNELS_NUMBER 12 -#define STM32_USBH_USE_OTG1 1 -#define STM32_OTG1_RXFIFO_SIZE 1024 -#define STM32_OTG1_PTXFIFO_SIZE 128 -#define STM32_OTG1_NPTXFIFO_SIZE 128 +#define STM32_USBH_USE_OTG1 1 +#define STM32_OTG1_RXFIFO_SIZE 1024 +#define STM32_OTG1_PTXFIFO_SIZE 128 +#define STM32_OTG1_NPTXFIFO_SIZE 128 -#define STM32_USBH_USE_OTG2 0 -#define STM32_OTG2_RXFIFO_SIZE 2048 -#define STM32_OTG2_PTXFIFO_SIZE 1024 -#define STM32_OTG2_NPTXFIFO_SIZE 1024 +#define STM32_USBH_USE_OTG2 0 +#define STM32_OTG2_RXFIFO_SIZE 2048 +#define STM32_OTG2_PTXFIFO_SIZE 1024 +#define STM32_OTG2_NPTXFIFO_SIZE 1024 -#define STM32_USBH_MIN_QSPACE 4 -#define STM32_USBH_CHANNELS_NP 4 +#define STM32_USBH_MIN_QSPACE 4 +#define STM32_USBH_CHANNELS_NP 4 |