EICU. Testhal. Initial working code.

author: barthess <barthess@yandex.ru> 2015-07-07 01:04:55 +0000
committer: barthess <barthess@yandex.ru> 2015-07-07 01:04:55 +0000
commit: 4d1b35fca4d266a92cc09b3b6d733b822d0242f5 (patch)
tree: ca193c08c9e0db6a464f9d606eb1cb1ab1c37584 /testhal
parent: 95da8798dd924b6eceb60c41f26d262d83799acb (diff)
download: ChibiOS-Contrib-4d1b35fca4d266a92cc09b3b6d733b822d0242f5.tar.gz
ChibiOS-Contrib-4d1b35fca4d266a92cc09b3b6d733b822d0242f5.tar.bz2
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15 files changed, 6070 insertions, 0 deletions
diff --git a/testhal/STM32/STM32F4xx/EICU/EICU_F4x.config b/testhal/STM32/STM32F4xx/EICU/EICU_F4x.config
new file mode 100644
index 0000000..e0284f4
--- /dev/null
+++ b/testhal/STM32/STM32F4xx/EICU/EICU_F4x.config
@@ -0,0 +1,2 @@
+// Add predefined macros for your project here. For example:
+// #define THE_ANSWER 42
diff --git a/testhal/STM32/STM32F4xx/EICU/EICU_F4x.creator b/testhal/STM32/STM32F4xx/EICU/EICU_F4x.creator
new file mode 100644
index 0000000..e94cbbd
--- /dev/null
+++ b/testhal/STM32/STM32F4xx/EICU/EICU_F4x.creator
@@ -0,0 +1 @@
+[General]
diff --git a/testhal/STM32/STM32F4xx/EICU/EICU_F4x.creator.user b/testhal/STM32/STM32F4xx/EICU/EICU_F4x.creator.user
new file mode 100644
index 0000000..80d783a
--- /dev/null
+++ b/testhal/STM32/STM32F4xx/EICU/EICU_F4x.creator.user
@@ -0,0 +1,156 @@
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diff --git a/testhal/STM32/STM32F4xx/EICU/EICU_F4x.files b/testhal/STM32/STM32F4xx/EICU/EICU_F4x.files
new file mode 100644
index 0000000..f154876
--- /dev/null
+++ b/testhal/STM32/STM32F4xx/EICU/EICU_F4x.files
@@ -0,0 +1,3443 @@
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+os/hal/ports/STM32/LLD/DACv1/dac_lld.h
+os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c
+os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h
+os/hal/ports/STM32/LLD/GPIOv1/pal_lld.c
+os/hal/ports/STM32/LLD/GPIOv1/pal_lld.h
+os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c
+os/hal/ports/STM32/LLD/GPIOv2/pal_lld.h
+os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c
+os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.h
+os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c
+os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.h
+os/hal/ports/STM32/LLD/OTGv1/stm32_otg.h
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+os/hal/ports/STM32/LLD/OTGv1/usb_lld.h
+os/hal/ports/STM32/LLD/RTCv1/rtc_lld.c
+os/hal/ports/STM32/LLD/RTCv1/rtc_lld.h
+os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c
+os/hal/ports/STM32/LLD/RTCv2/rtc_lld.h
+os/hal/ports/STM32/LLD/SPIv1/i2s_lld.c
+os/hal/ports/STM32/LLD/SPIv1/i2s_lld.h
+os/hal/ports/STM32/LLD/SPIv1/spi_lld.c
+os/hal/ports/STM32/LLD/SPIv1/spi_lld.h
+os/hal/ports/STM32/LLD/SPIv2/spi_lld.c
+os/hal/ports/STM32/LLD/SPIv2/spi_lld.h
+os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c
+os/hal/ports/STM32/LLD/TIMv1/gpt_lld.h
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+os/hal/ports/STM32/LLD/TIMv1/icu_lld.h
+os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c
+os/hal/ports/STM32/LLD/TIMv1/pwm_lld.h
+os/hal/ports/STM32/LLD/TIMv1/st_lld.c
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+os/hal/ports/STM32/LLD/TIMv1/stm32_tim.h
+os/hal/ports/STM32/LLD/USARTv1/serial_lld.c
+os/hal/ports/STM32/LLD/USARTv1/serial_lld.h
+os/hal/ports/STM32/LLD/USARTv1/uart_lld.c
+os/hal/ports/STM32/LLD/USARTv1/uart_lld.h
+os/hal/ports/STM32/LLD/USARTv2/serial_lld.c
+os/hal/ports/STM32/LLD/USARTv2/serial_lld.h
+os/hal/ports/STM32/LLD/USARTv2/uart_lld.c
+os/hal/ports/STM32/LLD/USARTv2/uart_lld.h
+os/hal/ports/STM32/LLD/USBv1/stm32_usb.h
+os/hal/ports/STM32/LLD/USBv1/usb_lld.c
+os/hal/ports/STM32/LLD/USBv1/usb_lld.h
+os/hal/ports/STM32/LLD/can_lld.c
+os/hal/ports/STM32/LLD/can_lld.h
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+os/hal/ports/STM32/LLD/mac_lld.h
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+os/hal/ports/STM32/STM32F0xx/ext_lld_isr.h
+os/hal/ports/STM32/STM32F0xx/hal_lld.c
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+os/hal/ports/STM32/STM32F1xx/adc_lld.h
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+os/hal/ports/STM32/STM32F1xx/ext_lld_isr.h
+os/hal/ports/STM32/STM32F1xx/hal_lld.c
+os/hal/ports/STM32/STM32F1xx/hal_lld.h
+os/hal/ports/STM32/STM32F1xx/hal_lld_f100.h
+os/hal/ports/STM32/STM32F1xx/hal_lld_f103.h
+os/hal/ports/STM32/STM32F1xx/hal_lld_f105_f107.h
+os/hal/ports/STM32/STM32F1xx/stm32_dma.c
+os/hal/ports/STM32/STM32F1xx/stm32_dma.h
+os/hal/ports/STM32/STM32F1xx/stm32_isr.h
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+os/hal/ports/STM32/STM32F1xx/stm32_registry.h
+os/hal/ports/STM32/STM32F37x/adc_lld.c
+os/hal/ports/STM32/STM32F37x/adc_lld.h
+os/hal/ports/STM32/STM32F37x/ext_lld_isr.c
+os/hal/ports/STM32/STM32F37x/ext_lld_isr.h
+os/hal/ports/STM32/STM32F37x/hal_lld.c
+os/hal/ports/STM32/STM32F37x/hal_lld.h
+os/hal/ports/STM32/STM32F37x/stm32_dma.c
+os/hal/ports/STM32/STM32F37x/stm32_dma.h
+os/hal/ports/STM32/STM32F37x/stm32_isr.h
+os/hal/ports/STM32/STM32F37x/stm32_rcc.h
+os/hal/ports/STM32/STM32F37x/stm32_registry.h
+os/hal/ports/STM32/STM32F3xx/adc_lld.c
+os/hal/ports/STM32/STM32F3xx/adc_lld.h
+os/hal/ports/STM32/STM32F3xx/ext_lld_isr.c
+os/hal/ports/STM32/STM32F3xx/ext_lld_isr.h
+os/hal/ports/STM32/STM32F3xx/hal_lld.c
+os/hal/ports/STM32/STM32F3xx/hal_lld.h
+os/hal/ports/STM32/STM32F3xx/stm32_dma.c
+os/hal/ports/STM32/STM32F3xx/stm32_dma.h
+os/hal/ports/STM32/STM32F3xx/stm32_isr.h
+os/hal/ports/STM32/STM32F3xx/stm32_rcc.h
+os/hal/ports/STM32/STM32F3xx/stm32_registry.h
+os/hal/ports/STM32/STM32F4xx/adc_lld.c
+os/hal/ports/STM32/STM32F4xx/adc_lld.h
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+os/hal/ports/STM32/STM32F4xx/ext_lld_isr.h
+os/hal/ports/STM32/STM32F4xx/hal_lld.c
+os/hal/ports/STM32/STM32F4xx/hal_lld.h
+os/hal/ports/STM32/STM32F4xx/stm32_dma.c
+os/hal/ports/STM32/STM32F4xx/stm32_dma.h
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+os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
+os/hal/ports/STM32/STM32F4xx/stm32_registry.h
+os/hal/ports/STM32/STM32L1xx/adc_lld.c
+os/hal/ports/STM32/STM32L1xx/adc_lld.h
+os/hal/ports/STM32/STM32L1xx/ext_lld_isr.c
+os/hal/ports/STM32/STM32L1xx/ext_lld_isr.h
+os/hal/ports/STM32/STM32L1xx/hal_lld.c
+os/hal/ports/STM32/STM32L1xx/hal_lld.h
+os/hal/ports/STM32/STM32L1xx/stm32_dma.c
+os/hal/ports/STM32/STM32L1xx/stm32_dma.h
+os/hal/ports/STM32/STM32L1xx/stm32_isr.h
+os/hal/ports/STM32/STM32L1xx/stm32_rcc.h
+os/hal/ports/STM32/STM32L1xx/stm32_registry.h
+os/hal/src/adc.c
+os/hal/src/can.c
+os/hal/src/dac.c
+os/hal/src/ext.c
+os/hal/src/gpt.c
+os/hal/src/hal.c
+os/hal/src/hal_mmcsd.c
+os/hal/src/hal_queues.c
+os/hal/src/i2c.c
+os/hal/src/i2s.c
+os/hal/src/icu.c
+os/hal/src/mac.c
+os/hal/src/mmc_spi.c
+os/hal/src/pal.c
+os/hal/src/pwm.c
+os/hal/src/rtc.c
+os/hal/src/sdc.c
+os/hal/src/serial.c
+os/hal/src/serial_usb.c
+os/hal/src/spi.c
+os/hal/src/st.c
+os/hal/src/uart.c
+os/hal/src/usb.c
+os/hal/templates/osal/osal.c
+os/hal/templates/osal/osal.h
+os/hal/templates/adc_lld.c
+os/hal/templates/adc_lld.h
+os/hal/templates/can_lld.c
+os/hal/templates/can_lld.h
+os/hal/templates/dac_lld.c
+os/hal/templates/dac_lld.h
+os/hal/templates/ext_lld.c
+os/hal/templates/ext_lld.h
+os/hal/templates/gpt_lld.c
+os/hal/templates/gpt_lld.h
+os/hal/templates/hal_lld.c
+os/hal/templates/hal_lld.h
+os/hal/templates/halconf.h
+os/hal/templates/i2c_lld.c
+os/hal/templates/i2c_lld.h
+os/hal/templates/i2s_lld.c
+os/hal/templates/i2s_lld.h
+os/hal/templates/icu_lld.c
+os/hal/templates/icu_lld.h
+os/hal/templates/mac_lld.c
+os/hal/templates/mac_lld.h
+os/hal/templates/mcuconf.h
+os/hal/templates/pal_lld.c
+os/hal/templates/pal_lld.h
+os/hal/templates/pwm_lld.c
+os/hal/templates/pwm_lld.h
+os/hal/templates/rtc_lld.c
+os/hal/templates/rtc_lld.h
+os/hal/templates/sdc_lld.c
+os/hal/templates/sdc_lld.h
+os/hal/templates/serial_lld.c
+os/hal/templates/serial_lld.h
+os/hal/templates/spi_lld.c
+os/hal/templates/spi_lld.h
+os/hal/templates/st_lld.c
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+os/hal/templates/uart_lld.c
+os/hal/templates/uart_lld.h
+os/hal/templates/usb_lld.c
+os/hal/templates/usb_lld.h
+os/nil/include/nil.h
+os/nil/ports/ARMCMx/compilers/GCC/niltypes.h
+os/nil/ports/ARMCMx/nilcore.c
+os/nil/ports/ARMCMx/nilcore.h
+os/nil/ports/ARMCMx/nilcore_timer.h
+os/nil/ports/ARMCMx/nilcore_v6m.c
+os/nil/ports/ARMCMx/nilcore_v6m.h
+os/nil/ports/ARMCMx/nilcore_v7m.c
+os/nil/ports/ARMCMx/nilcore_v7m.h
+os/nil/ports/AVR/compilers/GCC/niltypes.h
+os/nil/ports/AVR/nilcore.c
+os/nil/ports/AVR/nilcore.h
+os/nil/ports/AVR/nilcore_timer.h
+os/nil/ports/e200/compilers/GCC/niltypes.h
+os/nil/ports/e200/nilcore.c
+os/nil/ports/e200/nilcore.h
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+os/nil/templates/nilcore.c
+os/nil/templates/nilcore.h
+os/nil/templates/nilcore_timer.h
+os/nil/templates/niltypes.h
+os/rt/include/ch.h
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+os/rt/include/chcond.h
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+os/rt/include/chmemcore.h
+os/rt/include/chmempools.h
+os/rt/include/chmsg.h
+os/rt/include/chmtx.h
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+os/rt/include/chregistry.h
+os/rt/include/chschd.h
+os/rt/include/chsem.h
+os/rt/include/chstats.h
+os/rt/include/chstreams.h
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+os/rt/ports/ARM/compilers/GCC/chtypes.h
+os/rt/ports/ARM/chcore.c
+os/rt/ports/ARM/chcore.h
+os/rt/ports/ARM/chcore_timer.h
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+os/rt/ports/ARMCMx/cmsis_os/cmsis_os.h
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+os/rt/ports/ARMCMx/compilers/RVCT/chtypes.h
+os/rt/ports/ARMCMx/chcore.c
+os/rt/ports/ARMCMx/chcore.h
+os/rt/ports/ARMCMx/chcore_timer.h
+os/rt/ports/ARMCMx/chcore_v6m.c
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+os/rt/ports/ARMCMx/chcore_v7m.c
+os/rt/ports/ARMCMx/chcore_v7m.h
+os/rt/ports/AVR/compilers/GCC/chtypes.h
+os/rt/ports/AVR/chcore.c
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+os/rt/ports/e200/chcore.c
+os/rt/ports/e200/chcore.h
+os/rt/ports/SIMIA32/compilers/GCC/chtypes.h
+os/rt/ports/SIMIA32/chcore.c
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+os/rt/src/chcond.c
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+os/rt/src/chmemcore.c
+os/rt/src/chmempools.c
+os/rt/src/chmsg.c
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+os/rt/src/chregistry.c
+os/rt/src/chschd.c
+os/rt/src/chsem.c
+os/rt/src/chstats.c
+os/rt/src/chsys.c
+os/rt/src/chthreads.c
+os/rt/src/chtm.c
+os/rt/src/chvt.c
+os/rt/templates/meta/module.c
+os/rt/templates/meta/module.h
+os/rt/templates/chconf.h
+os/rt/templates/chcore.c
+os/rt/templates/chcore.h
+os/rt/templates/chtypes.h
+os/various/cpp_wrappers/ch.cpp
+os/various/cpp_wrappers/ch.hpp
+os/various/cpp_wrappers/syscalls_cpp.cpp
+os/various/cpp_wrappers/syscalls_cpp.hpp
+os/various/devices_lib/accel/lis302dl.c
+os/various/devices_lib/accel/lis302dl.h
+os/various/devices_lib/lcd/lcd3310.c
+os/various/devices_lib/lcd/lcd3310.h
+os/various/fatfs_bindings/fatfs_diskio.c
+os/various/fatfs_bindings/fatfs_syscall.c
+os/various/lwip_bindings/arch/cc.h
+os/various/lwip_bindings/arch/perf.h
+os/various/lwip_bindings/arch/sys_arch.c
+os/various/lwip_bindings/arch/sys_arch.h
+os/various/lwip_bindings/lwipthread.c
+os/various/lwip_bindings/lwipthread.h
+os/various/evtimer.c
+os/various/evtimer.h
+os/various/shell.c
+os/various/shell.h
+os/various/syscalls.c
+chconf.h
+halconf.h
+halconf_community.h
+main.c
+mcuconf.h
+mcuconf_community.h
+Makefile
diff --git a/testhal/STM32/STM32F4xx/EICU/EICU_F4x.includes b/testhal/STM32/STM32F4xx/EICU/EICU_F4x.includes
new file mode 100644
index 0000000..a5e7917
--- /dev/null
+++ b/testhal/STM32/STM32F4xx/EICU/EICU_F4x.includes
@@ -0,0 +1,769 @@
+.
+community/demos/NRF51/RT-WVSHARE_BLE400
+community/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D
+community/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res
+community/demos/TIVA/RT-TM4C123G-LAUNCHPAD
+community/demos/TIVA/RT-TM4C1294-LAUNCHPAD
+community/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP
+community/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/web
+community/os/common/ports/ARMCMx/devices/NRF51822
+community/os/common/ports/ARMCMx/devices/TM4C123x
+community/os/common/ports/ARMCMx/devices/TM4C129x
+community/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2
+community/os/hal/boards/ST_STM32F0308_DISCOVERY
+community/os/hal/boards/TI_TM4C123G_LAUNCHPAD
+community/os/hal/boards/TI_TM4C1294_LAUNCHPAD
+community/os/hal/boards/WVSHARE_BLE400
+community/os/hal/include
+community/os/hal/ports/NRF51/NRF51822
+community/os/hal/ports/STM32/LLD/DMA2Dv1
+community/os/hal/ports/STM32/LLD/FSMCv1
+community/os/hal/ports/STM32/LLD/LTDCv1
+community/os/hal/ports/STM32/LLD/TIMv1
+community/os/hal/ports/TIVA/LLD
+community/os/hal/ports/TIVA/TM4C123x
+community/os/hal/ports/TIVA/TM4C129x
+community/os/various
+community/os/various/devices_lib/lcd
+community/os/various/devices_lib/mems
+community/os/various/devices_lib/others
+community/os/various/devices_lib/rf
+community/testhal/STM32/STM32F0xx/onewire
+community/testhal/STM32/STM32F1xx/onewire
+community/testhal/STM32/STM32F4xx/EICU
+community/testhal/STM32/STM32F4xx/EICU/community/demos/NRF51/RT-WVSHARE_BLE400
+community/testhal/STM32/STM32F4xx/EICU/community/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D
+community/testhal/STM32/STM32F4xx/EICU/community/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res
+community/testhal/STM32/STM32F4xx/EICU/community/demos/TIVA/RT-TM4C123G-LAUNCHPAD
+community/testhal/STM32/STM32F4xx/EICU/community/demos/TIVA/RT-TM4C1294-LAUNCHPAD
+community/testhal/STM32/STM32F4xx/EICU/community/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP
+community/testhal/STM32/STM32F4xx/EICU/community/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/web
+community/testhal/STM32/STM32F4xx/EICU/community/os/common/ports/ARMCMx/devices/NRF51822
+community/testhal/STM32/STM32F4xx/EICU/community/os/common/ports/ARMCMx/devices/TM4C123x
+community/testhal/STM32/STM32F4xx/EICU/community/os/common/ports/ARMCMx/devices/TM4C129x
+community/testhal/STM32/STM32F4xx/EICU/community/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2
+community/testhal/STM32/STM32F4xx/EICU/community/os/hal/boards/ST_STM32F0308_DISCOVERY
+community/testhal/STM32/STM32F4xx/EICU/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD
+community/testhal/STM32/STM32F4xx/EICU/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD
+community/testhal/STM32/STM32F4xx/EICU/community/os/hal/boards/WVSHARE_BLE400
+community/testhal/STM32/STM32F4xx/EICU/community/os/hal/include
+community/testhal/STM32/STM32F4xx/EICU/community/os/hal/ports/NRF51/NRF51822
+community/testhal/STM32/STM32F4xx/EICU/community/os/hal/ports/STM32/LLD/DMA2Dv1
+community/testhal/STM32/STM32F4xx/EICU/community/os/hal/ports/STM32/LLD/FSMCv1
+community/testhal/STM32/STM32F4xx/EICU/community/os/hal/ports/STM32/LLD/LTDCv1
+community/testhal/STM32/STM32F4xx/EICU/community/os/hal/ports/STM32/LLD/TIMv1
+community/testhal/STM32/STM32F4xx/EICU/community/os/hal/ports/TIVA/LLD
+community/testhal/STM32/STM32F4xx/EICU/community/os/hal/ports/TIVA/TM4C123x
+community/testhal/STM32/STM32F4xx/EICU/community/os/hal/ports/TIVA/TM4C129x
+community/testhal/STM32/STM32F4xx/EICU/community/os/various
+community/testhal/STM32/STM32F4xx/EICU/community/os/various/devices_lib/lcd
+community/testhal/STM32/STM32F4xx/EICU/community/os/various/devices_lib/mems
+community/testhal/STM32/STM32F4xx/EICU/community/os/various/devices_lib/others
+community/testhal/STM32/STM32F4xx/EICU/community/os/various/devices_lib/rf
+community/testhal/STM32/STM32F4xx/EICU/community/testhal/STM32/STM32F0xx/onewire
+community/testhal/STM32/STM32F4xx/EICU/community/testhal/STM32/STM32F1xx/onewire
+community/testhal/STM32/STM32F4xx/EICU/community/testhal/STM32/STM32F4xx/EICU
+community/testhal/STM32/STM32F4xx/EICU/community/testhal/STM32/STM32F4xx/EICU/community/demos/NRF51/RT-WVSHARE_BLE400
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+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/EA_LPCXPRESSO_BB_11U14
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/EA_LPCXPRESSO_BB_1343
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/EA_LPCXPRESSO_LPC812
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/FREESCALE_FREEDOM_K20D50M
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/FREESCALE_FREEDOM_KL25Z
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/MAPLEMINI_STM32_F103
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/MCHCK_K20
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/NGX_BB_LPC11U14
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/OLIMEX_AVR_CAN
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/OLIMEX_AVR_MT_128
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/OLIMEX_LPC_P1227
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/OLIMEX_LPC_P1343
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/OLIMEX_LPC_P2148
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/OLIMEX_MSP430_P1611
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/OLIMEX_SAM7_EX256
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/OLIMEX_SAM7_P256
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/OLIMEX_STM32_103STK
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/OLIMEX_STM32_E407
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/OLIMEX_STM32_E407_REV_D
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/OLIMEX_STM32_H103
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/OLIMEX_STM32_H407
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/OLIMEX_STM32_LCD
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/OLIMEX_STM32_P103
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/OLIMEX_STM32_P107
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/OLIMEX_STM32_P407
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/PJRC_TEENSY_3
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/RAISONANCE_REVA_STM8S
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/simulator
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_EVB_SPC560B
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_EVB_SPC560BC
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_EVB_SPC560D
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_EVB_SPC560P
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_EVB_SPC563M
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_EVB_SPC564A
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_EVB_SPC56EC
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_EVB_SPC56EL
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_INEMO_M1_DISCOVERY
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_NUCLEO_F030R8
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_NUCLEO_F103RB
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_NUCLEO_F302R8
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_NUCLEO_F334R8
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_NUCLEO_F401RE
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_NUCLEO_F411RE
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_NUCLEO_L152RE
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_STM3210C_EVAL
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_STM3210E_EVAL
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_STM3220G_EVAL
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_STM32373C_EVAL
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_STM32F072B_DISCOVERY
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_STM32F0_DISCOVERY
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_STM32F3_DISCOVERY
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_STM32F401C_DISCOVERY
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_STM32F429I_DISCOVERY
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_STM32F4_DISCOVERY
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_STM32L_DISCOVERY
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_STM32VL_DISCOVERY
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_STM8L_DISCOVERY
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/ST_STM8S_DISCOVERY
+community/testhal/STM32/STM32F4xx/EICU/os/hal/boards/STUDIEL_AT91SAM7A3_EK
+community/testhal/STM32/STM32F4xx/EICU/os/hal/include
+community/testhal/STM32/STM32F4xx/EICU/os/hal/lib/streams
+community/testhal/STM32/STM32F4xx/EICU/os/hal/osal/nil
+community/testhal/STM32/STM32F4xx/EICU/os/hal/osal/os-less/ARMCMx
+community/testhal/STM32/STM32F4xx/EICU/os/hal/osal/rt
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/AVR
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/common/ARMCMx
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/KINETIS/K20x
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/KINETIS/KL2x
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/KINETIS/LLD
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/LPC/LPC214x
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/simulator
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/simulator/win32
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/STM32/LLD
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/STM32/LLD/DACv1
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/STM32/LLD/DMAv1
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/STM32/LLD/GPIOv1
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/STM32/LLD/GPIOv2
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/STM32/LLD/I2Cv1
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/STM32/LLD/I2Cv2
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/STM32/LLD/OTGv1
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/STM32/LLD/RTCv1
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/STM32/LLD/RTCv2
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/STM32/LLD/SPIv1
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/STM32/LLD/SPIv2
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/STM32/LLD/TIMv1
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/STM32/LLD/USARTv1
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/STM32/LLD/USARTv2
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/STM32/LLD/USBv1
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/STM32/STM32F0xx
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/STM32/STM32F1xx
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/STM32/STM32F37x
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/STM32/STM32F3xx
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/STM32/STM32F4xx
+community/testhal/STM32/STM32F4xx/EICU/os/hal/ports/STM32/STM32L1xx
+community/testhal/STM32/STM32F4xx/EICU/os/hal/templates
+community/testhal/STM32/STM32F4xx/EICU/os/hal/templates/osal
+community/testhal/STM32/STM32F4xx/EICU/os/nil/include
+community/testhal/STM32/STM32F4xx/EICU/os/nil/ports/ARMCMx
+community/testhal/STM32/STM32F4xx/EICU/os/nil/ports/ARMCMx/compilers/GCC
+community/testhal/STM32/STM32F4xx/EICU/os/nil/ports/AVR
+community/testhal/STM32/STM32F4xx/EICU/os/nil/ports/AVR/compilers/GCC
+community/testhal/STM32/STM32F4xx/EICU/os/nil/ports/e200
+community/testhal/STM32/STM32F4xx/EICU/os/nil/ports/e200/compilers/GCC
+community/testhal/STM32/STM32F4xx/EICU/os/nil/templates
+community/testhal/STM32/STM32F4xx/EICU/os/rt/include
+community/testhal/STM32/STM32F4xx/EICU/os/rt/ports/ARM
+community/testhal/STM32/STM32F4xx/EICU/os/rt/ports/ARM/compilers/GCC
+community/testhal/STM32/STM32F4xx/EICU/os/rt/ports/ARMCMx
+community/testhal/STM32/STM32F4xx/EICU/os/rt/ports/ARMCMx/cmsis_os
+community/testhal/STM32/STM32F4xx/EICU/os/rt/ports/ARMCMx/compilers/GCC
+community/testhal/STM32/STM32F4xx/EICU/os/rt/ports/ARMCMx/compilers/IAR
+community/testhal/STM32/STM32F4xx/EICU/os/rt/ports/ARMCMx/compilers/RVCT
+community/testhal/STM32/STM32F4xx/EICU/os/rt/ports/AVR
+community/testhal/STM32/STM32F4xx/EICU/os/rt/ports/AVR/compilers/GCC
+community/testhal/STM32/STM32F4xx/EICU/os/rt/ports/e200
+community/testhal/STM32/STM32F4xx/EICU/os/rt/ports/e200/compilers/GCC
+community/testhal/STM32/STM32F4xx/EICU/os/rt/ports/SIMIA32
+community/testhal/STM32/STM32F4xx/EICU/os/rt/ports/SIMIA32/compilers/GCC
+community/testhal/STM32/STM32F4xx/EICU/os/rt/templates
+community/testhal/STM32/STM32F4xx/EICU/os/rt/templates/meta
+community/testhal/STM32/STM32F4xx/EICU/os/various
+community/testhal/STM32/STM32F4xx/EICU/os/various/devices_lib/accel
+community/testhal/STM32/STM32F4xx/EICU/os/various/devices_lib/lcd
+community/testhal/STM32/STM32F4xx/EICU/os/various/lwip_bindings
+community/testhal/STM32/STM32F4xx/EICU/os/various/lwip_bindings/arch
+community/testhal/STM32/STM32F4xx/FSMC_NAND
+community/testhal/STM32/STM32F4xx/FSMC_SDRAM
+community/testhal/STM32/STM32F4xx/FSMC_SRAM
+community/testhal/STM32/STM32F4xx/onewire
+community/testhal/TIVA/TM4C123x/EXT
+community/testhal/TIVA/TM4C123x/GPT
+community/testhal/TIVA/TM4C123x/I2C
+community/testhal/TIVA/TM4C123x/PWM
+community/testhal/TIVA/TM4C123x/SPI
+os/common/ports/ARM/devices/LPC214x
+os/common/ports/ARMCMx/devices/K20x
+os/common/ports/ARMCMx/devices/KL2x
+os/common/ports/ARMCMx/devices/STM32F0xx
+os/common/ports/ARMCMx/devices/STM32F1xx
+os/common/ports/ARMCMx/devices/STM32F3xx
+os/common/ports/ARMCMx/devices/STM32F4xx
+os/common/ports/ARMCMx/devices/STM32L0xx
+os/common/ports/ARMCMx/devices/STM32L1xx
+os/common/ports/e200/compilers/GCC
+os/common/ports/e200/devices/SPC560BCxx
+os/common/ports/e200/devices/SPC560Bxx
+os/common/ports/e200/devices/SPC560Dxx
+os/common/ports/e200/devices/SPC560Pxx
+os/common/ports/e200/devices/SPC563Mxx
+os/common/ports/e200/devices/SPC564Axx
+os/common/ports/e200/devices/SPC56ECxx
+os/common/ports/e200/devices/SPC56ELxx
+os/common/ports/e200/devices/SPC57EMxx_HSM
+os/ext/CMSIS/include
+os/ext/CMSIS/KINETIS
+os/ext/CMSIS/ST
+os/hal/boards/ARDUINO_MEGA
+os/hal/boards/EA_LPCXPRESSO_11C24
+os/hal/boards/EA_LPCXPRESSO_BB_1114
+os/hal/boards/EA_LPCXPRESSO_BB_11U14
+os/hal/boards/EA_LPCXPRESSO_BB_1343
+os/hal/boards/EA_LPCXPRESSO_LPC812
+os/hal/boards/FREESCALE_FREEDOM_K20D50M
+os/hal/boards/FREESCALE_FREEDOM_KL25Z
+os/hal/boards/MAPLEMINI_STM32_F103
+os/hal/boards/MCHCK_K20
+os/hal/boards/NGX_BB_LPC11U14
+os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1
+os/hal/boards/OLIMEX_AVR_CAN
+os/hal/boards/OLIMEX_AVR_MT_128
+os/hal/boards/OLIMEX_LPC_P1227
+os/hal/boards/OLIMEX_LPC_P1343
+os/hal/boards/OLIMEX_LPC_P2148
+os/hal/boards/OLIMEX_MSP430_P1611
+os/hal/boards/OLIMEX_SAM7_EX256
+os/hal/boards/OLIMEX_SAM7_P256
+os/hal/boards/OLIMEX_STM32_103STK
+os/hal/boards/OLIMEX_STM32_E407
+os/hal/boards/OLIMEX_STM32_E407_REV_D
+os/hal/boards/OLIMEX_STM32_H103
+os/hal/boards/OLIMEX_STM32_H407
+os/hal/boards/OLIMEX_STM32_LCD
+os/hal/boards/OLIMEX_STM32_P103
+os/hal/boards/OLIMEX_STM32_P107
+os/hal/boards/OLIMEX_STM32_P407
+os/hal/boards/PJRC_TEENSY_3
+os/hal/boards/RAISONANCE_REVA_STM8S
+os/hal/boards/simulator
+os/hal/boards/ST_EVB_SPC560B
+os/hal/boards/ST_EVB_SPC560BC
+os/hal/boards/ST_EVB_SPC560D
+os/hal/boards/ST_EVB_SPC560P
+os/hal/boards/ST_EVB_SPC563M
+os/hal/boards/ST_EVB_SPC564A
+os/hal/boards/ST_EVB_SPC56EC
+os/hal/boards/ST_EVB_SPC56EL
+os/hal/boards/ST_INEMO_M1_DISCOVERY
+os/hal/boards/ST_NUCLEO_F030R8
+os/hal/boards/ST_NUCLEO_F103RB
+os/hal/boards/ST_NUCLEO_F302R8
+os/hal/boards/ST_NUCLEO_F334R8
+os/hal/boards/ST_NUCLEO_F401RE
+os/hal/boards/ST_NUCLEO_F411RE
+os/hal/boards/ST_NUCLEO_L152RE
+os/hal/boards/ST_STM3210C_EVAL
+os/hal/boards/ST_STM3210E_EVAL
+os/hal/boards/ST_STM3220G_EVAL
+os/hal/boards/ST_STM32373C_EVAL
+os/hal/boards/ST_STM32F072B_DISCOVERY
+os/hal/boards/ST_STM32F0_DISCOVERY
+os/hal/boards/ST_STM32F3_DISCOVERY
+os/hal/boards/ST_STM32F401C_DISCOVERY
+os/hal/boards/ST_STM32F429I_DISCOVERY
+os/hal/boards/ST_STM32F4_DISCOVERY
+os/hal/boards/ST_STM32L_DISCOVERY
+os/hal/boards/ST_STM32VL_DISCOVERY
+os/hal/boards/ST_STM8L_DISCOVERY
+os/hal/boards/ST_STM8S_DISCOVERY
+os/hal/boards/STUDIEL_AT91SAM7A3_EK
+os/hal/include
+os/hal/lib/streams
+os/hal/osal/nil
+os/hal/osal/os-less/ARMCMx
+os/hal/osal/rt
+os/hal/ports/AVR
+os/hal/ports/common/ARMCMx
+os/hal/ports/KINETIS/K20x
+os/hal/ports/KINETIS/KL2x
+os/hal/ports/KINETIS/LLD
+os/hal/ports/LPC/LPC214x
+os/hal/ports/simulator
+os/hal/ports/simulator/win32
+os/hal/ports/STM32/LLD
+os/hal/ports/STM32/LLD/DACv1
+os/hal/ports/STM32/LLD/DMAv1
+os/hal/ports/STM32/LLD/GPIOv1
+os/hal/ports/STM32/LLD/GPIOv2
+os/hal/ports/STM32/LLD/I2Cv1
+os/hal/ports/STM32/LLD/I2Cv2
+os/hal/ports/STM32/LLD/OTGv1
+os/hal/ports/STM32/LLD/RTCv1
+os/hal/ports/STM32/LLD/RTCv2
+os/hal/ports/STM32/LLD/SPIv1
+os/hal/ports/STM32/LLD/SPIv2
+os/hal/ports/STM32/LLD/TIMv1
+os/hal/ports/STM32/LLD/USARTv1
+os/hal/ports/STM32/LLD/USARTv2
+os/hal/ports/STM32/LLD/USBv1
+os/hal/ports/STM32/STM32F0xx
+os/hal/ports/STM32/STM32F1xx
+os/hal/ports/STM32/STM32F37x
+os/hal/ports/STM32/STM32F3xx
+os/hal/ports/STM32/STM32F4xx
+os/hal/ports/STM32/STM32L1xx
+os/hal/templates
+os/hal/templates/osal
+os/nil/include
+os/nil/ports/ARMCMx
+os/nil/ports/ARMCMx/compilers/GCC
+os/nil/ports/AVR
+os/nil/ports/AVR/compilers/GCC
+os/nil/ports/e200
+os/nil/ports/e200/compilers/GCC
+os/nil/templates
+os/rt/include
+os/rt/ports/ARM
+os/rt/ports/ARM/compilers/GCC
+os/rt/ports/ARMCMx
+os/rt/ports/ARMCMx/cmsis_os
+os/rt/ports/ARMCMx/compilers/GCC
+os/rt/ports/ARMCMx/compilers/IAR
+os/rt/ports/ARMCMx/compilers/RVCT
+os/rt/ports/AVR
+os/rt/ports/AVR/compilers/GCC
+os/rt/ports/e200
+os/rt/ports/e200/compilers/GCC
+os/rt/ports/SIMIA32
+os/rt/ports/SIMIA32/compilers/GCC
+os/rt/templates
+os/rt/templates/meta
+os/various
+os/various/devices_lib/accel
+os/various/devices_lib/lcd
+os/various/lwip_bindings
+os/various/lwip_bindings/arch
diff --git a/testhal/STM32/STM32F4xx/EICU/Makefile b/testhal/STM32/STM32F4xx/EICU/Makefile
new file mode 100644
index 0000000..45641c8
--- /dev/null
+++ b/testhal/STM32/STM32F4xx/EICU/Makefile
@@ -0,0 +1,209 @@
+##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+  USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+  USE_COPT = 
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+  USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+  USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+  USE_LDOPT = 
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+  USE_LTO = no
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+  USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+  USE_VERBOSE_COMPILE = no
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the Cortex-M process stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_PROCESS_STACKSIZE),)
+  USE_PROCESS_STACKSIZE = 0x400
+endif
+
+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
+# stack is used for processing interrupts and exceptions.
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+  USE_EXCEPTIONS_STACKSIZE = 0x400
+endif
+
+# Enables the use of FPU on Cortex-M4 (no, softfp, hard).
+ifeq ($(USE_FPU),)
+  USE_FPU = no
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../../../../..
+# Startup files.
+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk
+# HAL-OSAL files (optional).
+include $(CHIBIOS)/community/os/hal/hal.mk
+include $(CHIBIOS)/community/os/hal/ports/STM32/STM32F4xx/platform.mk
+include $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+# RTOS files (optional).
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
+
+# Define linker script file here
+LDSCRIPT= $(STARTUPLD)/STM32F407xG.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(STARTUPSRC) \
+       $(KERNSRC) \
+       $(PORTSRC) \
+       $(OSALSRC) \
+       $(HALSRC) \
+       $(PLATFORMSRC) \
+       $(BOARDSRC) \
+       $(TESTSRC) \
+       main.c
+       
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+#       option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+#       option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+#       option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+#       option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
+
+INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
+         $(HALINC) $(PLATFORMINC) $(BOARDINC) \
+         $(CHIBIOS)/os/various
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU  = cortex-m4
+
+#TRGT = arm-elf-
+TRGT = arm-none-eabi-
+CC   = ccache $(TRGT)gcc
+CPPC = ccache $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+#       runtime support makes code size explode.
+LD   = $(TRGT)gcc
+#LD   = $(TRGT)g++
+CP   = $(TRGT)objcopy
+AS   = $(TRGT)gcc -x assembler-with-cpp
+AR   = $(TRGT)ar
+OD   = $(TRGT)objdump
+SZ   = $(TRGT)size
+HEX  = $(CP) -O ihex
+BIN  = $(CP) -O binary
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wstrict-prototypes -Wundef
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra -Wundef
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC
+include $(RULESPATH)/rules.mk
+
diff --git a/testhal/STM32/STM32F4xx/EICU/chconf.h b/testhal/STM32/STM32F4xx/EICU/chconf.h
new file mode 100644
index 0000000..c8a8f19
--- /dev/null
+++ b/testhal/STM32/STM32F4xx/EICU/chconf.h
@@ -0,0 +1,498 @@
+/*
+    ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    templates/chconf.h
+ * @brief   Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ *          contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   System time counter resolution.
+ * @note    Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION                32
+
+/**
+ * @brief   System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ *          setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY                 100000
+
+/**
+ * @brief   Time delta constant for the tick-less mode.
+ * @note    If this value is zero then the system uses the classic
+ *          periodic tick. This value represents the minimum number
+ *          of ticks that is safe to specify in a timeout directive.
+ *          The value one is not valid, timeouts are rounded up to
+ *          this value.
+ */
+#define CH_CFG_ST_TIMEDELTA                 2
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ *          threads before preemption occurs. Setting this value to zero
+ *          disables the preemption for threads with equal priority and the
+ *          round robin becomes cooperative. Note that higher priority
+ *          threads can still preempt, the kernel is always preemptive.
+ * @note    Disabling the round robin preemption makes the kernel more compact
+ *          and generally faster.
+ * @note    The round robin preemption is not supported in tickless mode and
+ *          must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM                 0
+
+/**
+ * @brief   Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ *          then the whole available RAM is used. The core memory is made
+ *          available to the heap allocator and/or can be used directly through
+ *          the simplified core memory allocator.
+ *
+ * @note    In order to let the OS manage the whole RAM the linker script must
+ *          provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note    Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE                 0
+
+/**
+ * @brief   Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ *          does not spawn the idle thread. The application @p main()
+ *          function becomes the idle thread and must implement an
+ *          infinite loop. */
+#define CH_CFG_NO_IDLE_THREAD               FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ *          is used when two possible implementations exist.
+ *
+ * @note    This is not related to the compiler optimization options.
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED               TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ *          the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM                       false
+
+/**
+ * @brief   Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY                 TRUE
+
+/**
+ * @brief   Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ *          the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT                 TRUE
+
+/**
+ * @brief   Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES               FALSE
+
+/**
+ * @brief   Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ *          priority rather than in FIFO order.
+ *
+ * @note    The default is @p FALSE. Enable this if you have special
+ *          requirements.
+ * @note    Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY      FALSE
+
+/**
+ * @brief   Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES                  FALSE
+
+/**
+ * @brief   Enables recursive behavior on mutexes.
+ * @note    Recursive mutexes are heavier and have an increased
+ *          memory footprint.
+ *
+ * @note    The default is @p FALSE.
+ * @note    Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE        FALSE
+
+/**
+ * @brief   Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS                 FALSE
+
+/**
+ * @brief   Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ *          specification are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT         FALSE
+
+/**
+ * @brief   Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS                   FALSE
+
+/**
+ * @brief   Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ *          are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT           FALSE
+
+/**
+ * @brief   Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES                 FALSE
+
+/**
+ * @brief   Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ *          FIFO order.
+ *
+ * @note    The default is @p FALSE. Enable this if you have special
+ *          requirements.
+ * @note    Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY        FALSE
+
+/**
+ * @brief   Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ *          included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES                FALSE
+
+/**
+ * @brief   I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_QUEUES                   FALSE
+
+/**
+ * @brief   Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE                  FALSE
+
+/**
+ * @brief   Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ *          @p CH_CFG_USE_SEMAPHORES.
+ * @note    Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP                     FALSE
+
+/**
+ * @brief   Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS                 FALSE
+
+/**
+ * @brief   Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_CFG_USE_WAITEXIT.
+ * @note    Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC                  FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Debug option, kernel statistics.
+ *
+ * @note    The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS                   FALSE
+
+/**
+ * @brief   Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ *          at runtime.
+ *
+ * @note    The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK           FALSE
+
+/**
+ * @brief   Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ *          parameters are activated.
+ *
+ * @note    The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS                FALSE
+
+/**
+ * @brief   Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ *          activated. This includes consistency checks inside the kernel,
+ *          runtime anomalies and port-defined checks.
+ *
+ * @note    The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS               FALSE
+
+/**
+ * @brief   Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ *          activated.
+ *
+ * @note    The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE                 FALSE
+
+/**
+ * @brief   Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note    The default is @p FALSE.
+ * @note    The stack check is performed in a architecture/port dependent way.
+ *          It may not be implemented or some ports.
+ * @note    The default failure mode is to halt the system with the global
+ *          @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK           FALSE
+
+/**
+ * @brief   Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ *          value when a thread is created. This can be useful for the
+ *          runtime measurement of the used stack.
+ *
+ * @note    The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS                 TRUE
+
+/**
+ * @brief   Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ *          counts the system ticks occurred while executing the thread.
+ *
+ * @note    The default is @p FALSE.
+ * @note    This debug option is not currently compatible with the
+ *          tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING            FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS                                          \
+  /* Add threads custom fields here.*/
+
+/**
+ * @brief   Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note    It is invoked from within @p chThdInit() and implicitly from all
+ *          the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) {                                       \
+  /* Add threads initialization code here.*/                                \
+}
+
+/**
+ * @brief   Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note    It is inserted into lock zone.
+ * @note    It is also invoked when the threads simply return in order to
+ *          terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) {                                       \
+  /* Add threads finalization code here.*/                                  \
+}
+
+/**
+ * @brief   Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) {                              \
+  /* System halt code here.*/                                               \
+}
+
+/**
+ * @brief   Idle thread enter hook.
+ * @note    This hook is invoked within a critical zone, no OS functions
+ *          should be invoked from here.
+ * @note    This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() {                                         \
+}
+
+/**
+ * @brief   Idle thread leave hook.
+ * @note    This hook is invoked within a critical zone, no OS functions
+ *          should be invoked from here.
+ * @note    This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() {                                         \
+}
+
+/**
+ * @brief   Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() {                                           \
+  /* Idle loop code here.*/                                                 \
+}
+
+/**
+ * @brief   System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ *          after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() {                                         \
+  /* System tick event code here.*/                                         \
+}
+
+/**
+ * @brief   System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ *          the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) {                                   \
+  /* System halt code here.*/                                               \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h).    */
+/*===========================================================================*/
+
+#endif  /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/STM32/STM32F4xx/EICU/community b/testhal/STM32/STM32F4xx/EICU/community
new file mode 120000
index 0000000..544599d
--- /dev/null
+++ b/testhal/STM32/STM32F4xx/EICU/community
@@ -0,0 +1 @@
+../../../../../community
+\ No newline at end of file
diff --git a/testhal/STM32/STM32F4xx/EICU/halconf.h b/testhal/STM32/STM32F4xx/EICU/halconf.h
new file mode 100644
index 0000000..c65fbb4
--- /dev/null
+++ b/testhal/STM32/STM32F4xx/EICU/halconf.h
@@ -0,0 +1,340 @@
+/*
+    ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    templates/halconf.h
+ * @brief   HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ *          various device drivers from your application. You may also use
+ *          this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief   Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL                 TRUE
+#endif
+
+/**
+ * @brief   Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN                 FALSE
+#endif
+
+/**
+ * @brief   Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT                 FALSE
+#endif
+
+/**
+ * @brief   Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT                 FALSE
+#endif
+
+/**
+ * @brief   Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C                 FALSE
+#endif
+
+/**
+ * @brief   Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S                 FALSE
+#endif
+
+/**
+ * @brief   Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU                 FALSE
+#endif
+
+/**
+ * @brief   Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI             FALSE
+#endif
+
+/**
+ * @brief   Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM                 FALSE
+#endif
+
+/**
+ * @brief   Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL              FALSE
+#endif
+
+/**
+ * @brief   Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB          FALSE
+#endif
+
+/**
+ * @brief   Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI                 FALSE
+#endif
+
+/**
+ * @brief   Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART                FALSE
+#endif
+
+/**
+ * @brief   Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB                 FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables synchronous APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT                TRUE
+#endif
+
+/**
+ * @brief   Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION    TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE          TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION    TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY           FALSE
+#endif
+
+/**
+ * @brief   Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS              TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings.                                          */
+/*===========================================================================*/
+
+/**
+ * @brief   Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ *          routines releasing some extra CPU time for the threads with
+ *          lower priority, this may slow down the driver a bit however.
+ *          This option is recommended also if the SPI driver does not
+ *          use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING            TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Number of initialization attempts before rejecting the card.
+ * @note    Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY              100
+#endif
+
+/**
+ * @brief   Include support for MMC cards.
+ * @note    MMC support is not yet implemented so this option must be kept
+ *          at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT             FALSE
+#endif
+
+/**
+ * @brief   Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ *          routines releasing some extra CPU time for the threads with
+ *          lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING            TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings.                                           */
+/*===========================================================================*/
+
+/**
+ * @brief   Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ *          default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE      38400
+#endif
+
+/**
+ * @brief   Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ *          buffers depending on the requirements of your application.
+ * @note    The default is 64 bytes for both the transmission and receive
+ *          buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE         16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting.                                        */
+/*===========================================================================*/
+
+/**
+ * @brief   Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ *          the USB data endpoint maximum packet size.
+ * @note    The default is 64 bytes for both the transmission and receive
+ *          buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE     256
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables synchronous APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT                TRUE
+#endif
+
+/**
+ * @brief   Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION    TRUE
+#endif
+
+/*===========================================================================*/
+/* Community drivers's includes                                              */
+/*===========================================================================*/
+
+#include "halconf_community.h"
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/STM32/STM32F4xx/EICU/halconf_community.h b/testhal/STM32/STM32F4xx/EICU/halconf_community.h
new file mode 100644
index 0000000..70856e8
--- /dev/null
+++ b/testhal/STM32/STM32F4xx/EICU/halconf_community.h
@@ -0,0 +1,77 @@
+/*
+    ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _HALCONF_COMMUNITY_H_
+#define _HALCONF_COMMUNITY_H_
+
+/**
+ * @brief   Enables the community overlay.
+ */
+#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__)
+#define HAL_USE_COMMUNITY           TRUE
+#endif
+
+/**
+ * @brief   Enables the NAND subsystem.
+ */
+#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__)
+#define HAL_USE_NAND                FALSE
+#endif
+
+/**
+ * @brief   Enables the 1-wire subsystem.
+ */
+#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__)
+#define HAL_USE_ONEWIRE             FALSE
+#endif
+
+/**
+ * @brief   Enables the EICU subsystem.
+ */
+#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__)
+#define HAL_USE_EICU                TRUE
+#endif
+
+/*===========================================================================*/
+/* FSMCNAND driver related settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define NAND_USE_MUTUAL_EXCLUSION   TRUE
+#endif
+
+/*===========================================================================*/
+/* 1-wire driver related settings.                                           */
+/*===========================================================================*/
+/**
+ * @brief   Enables strong pull up feature.
+ * @note    Disabling this option saves both code and data space.
+ */
+#define ONEWIRE_USE_STRONG_PULLUP   FALSE
+
+/**
+ * @brief   Enables search ROM feature.
+ * @note    Disabling this option saves both code and data space.
+ */
+#define ONEWIRE_USE_SEARCH_ROM      FALSE
+
+#endif /* _HALCONF_COMMUNITY_H_ */
+
+/** @} */
diff --git a/testhal/STM32/STM32F4xx/EICU/main.c b/testhal/STM32/STM32F4xx/EICU/main.c
new file mode 100644
index 0000000..4b3d72c
--- /dev/null
+++ b/testhal/STM32/STM32F4xx/EICU/main.c
@@ -0,0 +1,152 @@
+/*
+    ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * Make following connections on your discovery board:
+ * PD13-PB4
+ * PD12-PB5
+ * PD14-PB0
+ * PD15-PB1
+ */
+
+#include "ch.h"
+#include "hal.h"
+#include "stdlib.h"
+
+typedef struct {
+  systime_t high;
+  systime_t low;
+  uint32_t pad;
+} pulse_t;
+
+/*
+ * Chose values suitable for measurement using 16-bit timer on 1MHz
+ */
+static pulse_t pulse_led3 = {MS2ST(2), MS2ST(59), GPIOD_LED3};
+static pulse_t pulse_led4 = {MS2ST(3), MS2ST(53), GPIOD_LED4};
+static pulse_t pulse_led5 = {MS2ST(5), MS2ST(47), GPIOD_LED5};
+static pulse_t pulse_led6 = {MS2ST(7), MS2ST(43), GPIOD_LED6};
+
+/*
+ *
+ */
+static THD_WORKING_AREA(PulseThreadWA_LED3, 128);
+static THD_WORKING_AREA(PulseThreadWA_LED4, 128);
+static THD_WORKING_AREA(PulseThreadWA_LED5, 128);
+static THD_WORKING_AREA(PulseThreadWA_LED6, 128);
+
+static THD_FUNCTION(PulseThread, arg) {
+  chRegSetThreadName("Pulse");
+  pulse_t *pulse = arg;
+
+  systime_t t = chVTGetSystemTimeX();
+
+  while (!chThdShouldTerminateX()) {
+    t += pulse->high;
+    palSetPad(GPIOD, pulse->pad);
+    chThdSleepUntil(t);
+    palClearPad(GPIOD, pulse->pad);
+    t+= pulse->low;
+    chThdSleepUntil(t);
+  }
+
+  chThdExit(MSG_OK);
+}
+
+static const int32_t tolerance = 20; // uS
+void eicu_cb(EICUDriver *eicup, eicuchannel_t channel, uint32_t w, uint32_t p) {
+  (void)eicup;
+  (void)p;
+  switch (channel) {
+  case EICU_CHANNEL_1:
+    if (abs((int32_t)w - (int32_t)ST2US(pulse_led3.high)) > tolerance)
+      osalSysHalt("ch1");
+    break;
+  case EICU_CHANNEL_2:
+    if (abs((int32_t)w - (int32_t)ST2US(pulse_led4.high)) > tolerance)
+      osalSysHalt("ch2");
+    break;
+  case EICU_CHANNEL_3:
+    if (abs((int32_t)w - (int32_t)ST2US(pulse_led5.high)) > tolerance)
+      osalSysHalt("ch3");
+    break;
+  case EICU_CHANNEL_4:
+    if (abs((int32_t)w - (int32_t)ST2US(pulse_led6.high)) > tolerance)
+      osalSysHalt("ch4");
+    break;
+  default:
+    osalSysHalt("unhandled case");
+    break;
+  }
+}
+
+static const EICUChannelConfig led3cfg = {
+    EICU_INPUT_ACTIVE_HIGH,
+    EICU_INPUT_PULSE,
+    eicu_cb
+};
+
+static const EICUConfig eicucfg = {
+    1000000,    /* EICU clock frequency in Hz.*/
+    {
+        &led3cfg,
+        &led3cfg,
+        &led3cfg,
+        &led3cfg
+    },
+    0
+};
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+  /*
+   * System initializations.
+   * - HAL initialization, this also initializes the configured device drivers
+   *   and performs the board-specific initializations.
+   * - Kernel initialization, the main() function becomes a thread and the
+   *   RTOS is active.
+   */
+  halInit();
+  chSysInit();
+
+  palSetPadMode(GPIOB, GPIOB_PIN0, PAL_MODE_ALTERNATE(2) | PAL_STM32_PUDR_FLOATING);
+  palSetPadMode(GPIOB, GPIOB_PIN1, PAL_MODE_ALTERNATE(2) | PAL_STM32_PUDR_FLOATING);
+  palSetPadMode(GPIOB, GPIOB_PIN4, PAL_MODE_ALTERNATE(2) | PAL_STM32_PUDR_FLOATING);
+  palSetPadMode(GPIOB, GPIOB_PIN5, PAL_MODE_ALTERNATE(2) | PAL_STM32_PUDR_FLOATING);
+
+  eicuStart(&EICUD3, &eicucfg);
+  eicuEnable(&EICUD3);
+
+  osalThreadSleepMicroseconds(10); // need to stabilize input puns
+
+  chThdCreateStatic(PulseThreadWA_LED3, sizeof(PulseThreadWA_LED3),
+                    NORMALPRIO+1, PulseThread, &pulse_led3);
+  chThdCreateStatic(PulseThreadWA_LED4, sizeof(PulseThreadWA_LED4),
+                    NORMALPRIO+1, PulseThread, &pulse_led4);
+  chThdCreateStatic(PulseThreadWA_LED5, sizeof(PulseThreadWA_LED5),
+                    NORMALPRIO+1, PulseThread, &pulse_led5);
+  chThdCreateStatic(PulseThreadWA_LED6, sizeof(PulseThreadWA_LED6),
+                    NORMALPRIO+1, PulseThread, &pulse_led6);
+
+  while (true) {
+    osalThreadSleepMilliseconds(500);
+  }
+
+  return 0;
+}
diff --git a/testhal/STM32/STM32F4xx/EICU/mcuconf.h b/testhal/STM32/STM32F4xx/EICU/mcuconf.h
new file mode 100644
index 0000000..e67608f
--- /dev/null
+++ b/testhal/STM32/STM32F4xx/EICU/mcuconf.h
@@ -0,0 +1,310 @@
+/*
+    ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * STM32F4xx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 15...0       Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3        Lowest...Highest.
+ */
+
+#define STM32F4xx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define STM32_NO_INIT                       FALSE
+#define STM32_HSI_ENABLED                   TRUE
+#define STM32_LSI_ENABLED                   TRUE
+#define STM32_HSE_ENABLED                   TRUE
+#define STM32_LSE_ENABLED                   FALSE
+#define STM32_CLOCK48_REQUIRED              TRUE
+#define STM32_SW                            STM32_SW_PLL
+#define STM32_PLLSRC                        STM32_PLLSRC_HSE
+#define STM32_PLLM_VALUE                    8
+#define STM32_PLLN_VALUE                    336
+#define STM32_PLLP_VALUE                    2
+#define STM32_PLLQ_VALUE                    7
+#define STM32_HPRE                          STM32_HPRE_DIV1
+#define STM32_PPRE1                         STM32_PPRE1_DIV4
+#define STM32_PPRE2                         STM32_PPRE2_DIV2
+#define STM32_RTCSEL                        STM32_RTCSEL_LSI
+#define STM32_RTCPRE_VALUE                  8
+#define STM32_MCO1SEL                       STM32_MCO1SEL_HSI
+#define STM32_MCO1PRE                       STM32_MCO1PRE_DIV1
+#define STM32_MCO2SEL                       STM32_MCO2SEL_SYSCLK
+#define STM32_MCO2PRE                       STM32_MCO2PRE_DIV5
+#define STM32_I2SSRC                        STM32_I2SSRC_CKIN
+#define STM32_PLLI2SN_VALUE                 192
+#define STM32_PLLI2SR_VALUE                 5
+#define STM32_PVD_ENABLE                    FALSE
+#define STM32_PLS                           STM32_PLS_LEV0
+#define STM32_BKPRAM_ENABLE                 FALSE
+
+/*
+ * ADC driver system settings.
+ */
+#define STM32_ADC_ADCPRE                    ADC_CCR_ADCPRE_DIV4
+#define STM32_ADC_USE_ADC1                  FALSE
+#define STM32_ADC_USE_ADC2                  FALSE
+#define STM32_ADC_USE_ADC3                  FALSE
+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(2, 4)
+#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC1_DMA_PRIORITY         2
+#define STM32_ADC_ADC2_DMA_PRIORITY         2
+#define STM32_ADC_ADC3_DMA_PRIORITY         2
+#define STM32_ADC_IRQ_PRIORITY              6
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     6
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     6
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     6
+
+/*
+ * CAN driver system settings.
+ */
+#define STM32_CAN_USE_CAN1                  FALSE
+#define STM32_CAN_USE_CAN2                  FALSE
+#define STM32_CAN_CAN1_IRQ_PRIORITY         11
+#define STM32_CAN_CAN2_IRQ_PRIORITY         11
+
+/*
+ * EXT driver system settings.
+ */
+#define STM32_EXT_EXTI0_IRQ_PRIORITY        6
+#define STM32_EXT_EXTI1_IRQ_PRIORITY        6
+#define STM32_EXT_EXTI2_IRQ_PRIORITY        6
+#define STM32_EXT_EXTI3_IRQ_PRIORITY        6
+#define STM32_EXT_EXTI4_IRQ_PRIORITY        6
+#define STM32_EXT_EXTI5_9_IRQ_PRIORITY      6
+#define STM32_EXT_EXTI10_15_IRQ_PRIORITY    6
+#define STM32_EXT_EXTI16_IRQ_PRIORITY       6
+#define STM32_EXT_EXTI17_IRQ_PRIORITY       15
+#define STM32_EXT_EXTI18_IRQ_PRIORITY       6
+#define STM32_EXT_EXTI19_IRQ_PRIORITY       6
+#define STM32_EXT_EXTI20_IRQ_PRIORITY       6
+#define STM32_EXT_EXTI21_IRQ_PRIORITY       15
+#define STM32_EXT_EXTI22_IRQ_PRIORITY       15
+
+/*
+ * GPT driver system settings.
+ */
+#define STM32_GPT_USE_TIM1                  FALSE
+#define STM32_GPT_USE_TIM2                  FALSE
+#define STM32_GPT_USE_TIM3                  FALSE
+#define STM32_GPT_USE_TIM4                  FALSE
+#define STM32_GPT_USE_TIM5                  FALSE
+#define STM32_GPT_USE_TIM6                  FALSE
+#define STM32_GPT_USE_TIM7                  FALSE
+#define STM32_GPT_USE_TIM8                  FALSE
+#define STM32_GPT_USE_TIM9                  FALSE
+#define STM32_GPT_USE_TIM11                 FALSE
+#define STM32_GPT_USE_TIM12                 FALSE
+#define STM32_GPT_USE_TIM14                 FALSE
+#define STM32_GPT_TIM1_IRQ_PRIORITY         7
+#define STM32_GPT_TIM2_IRQ_PRIORITY         7
+#define STM32_GPT_TIM3_IRQ_PRIORITY         7
+#define STM32_GPT_TIM4_IRQ_PRIORITY         7
+#define STM32_GPT_TIM5_IRQ_PRIORITY         7
+#define STM32_GPT_TIM6_IRQ_PRIORITY         7
+#define STM32_GPT_TIM7_IRQ_PRIORITY         7
+#define STM32_GPT_TIM8_IRQ_PRIORITY         7
+#define STM32_GPT_TIM9_IRQ_PRIORITY         7
+#define STM32_GPT_TIM11_IRQ_PRIORITY        7
+#define STM32_GPT_TIM12_IRQ_PRIORITY        7
+#define STM32_GPT_TIM14_IRQ_PRIORITY        7
+
+/*
+ * I2C driver system settings.
+ */
+#define STM32_I2C_USE_I2C1                  FALSE
+#define STM32_I2C_USE_I2C2                  FALSE
+#define STM32_I2C_USE_I2C3                  FALSE
+#define STM32_I2C_BUSY_TIMEOUT              50
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2C_I2C1_IRQ_PRIORITY         5
+#define STM32_I2C_I2C2_IRQ_PRIORITY         5
+#define STM32_I2C_I2C3_IRQ_PRIORITY         5
+#define STM32_I2C_I2C1_DMA_PRIORITY         3
+#define STM32_I2C_I2C2_DMA_PRIORITY         3
+#define STM32_I2C_I2C3_DMA_PRIORITY         3
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")
+
+/*
+ * ICU driver system settings.
+ */
+#define STM32_ICU_USE_TIM1                  FALSE
+#define STM32_ICU_USE_TIM2                  FALSE
+#define STM32_ICU_USE_TIM3                  FALSE
+#define STM32_ICU_USE_TIM4                  FALSE
+#define STM32_ICU_USE_TIM5                  FALSE
+#define STM32_ICU_USE_TIM8                  FALSE
+#define STM32_ICU_USE_TIM9                  FALSE
+#define STM32_ICU_TIM1_IRQ_PRIORITY         7
+#define STM32_ICU_TIM2_IRQ_PRIORITY         7
+#define STM32_ICU_TIM3_IRQ_PRIORITY         7
+#define STM32_ICU_TIM4_IRQ_PRIORITY         7
+#define STM32_ICU_TIM5_IRQ_PRIORITY         7
+#define STM32_ICU_TIM8_IRQ_PRIORITY         7
+#define STM32_ICU_TIM9_IRQ_PRIORITY         7
+
+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS          2
+#define STM32_MAC_RECEIVE_BUFFERS           4
+#define STM32_MAC_BUFFERS_SIZE              1522
+#define STM32_MAC_PHY_TIMEOUT               100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY         13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
+
+/*
+ * PWM driver system settings.
+ */
+#define STM32_PWM_USE_ADVANCED              FALSE
+#define STM32_PWM_USE_TIM1                  FALSE
+#define STM32_PWM_USE_TIM2                  FALSE
+#define STM32_PWM_USE_TIM3                  FALSE
+#define STM32_PWM_USE_TIM4                  FALSE
+#define STM32_PWM_USE_TIM5                  FALSE
+#define STM32_PWM_USE_TIM8                  FALSE
+#define STM32_PWM_USE_TIM9                  FALSE
+#define STM32_PWM_TIM1_IRQ_PRIORITY         7
+#define STM32_PWM_TIM2_IRQ_PRIORITY         7
+#define STM32_PWM_TIM3_IRQ_PRIORITY         7
+#define STM32_PWM_TIM4_IRQ_PRIORITY         7
+#define STM32_PWM_TIM5_IRQ_PRIORITY         7
+#define STM32_PWM_TIM8_IRQ_PRIORITY         7
+#define STM32_PWM_TIM9_IRQ_PRIORITY         7
+
+/*
+ * SDC driver system settings.
+ */
+#define STM32_SDC_SDIO_DMA_PRIORITY         3
+#define STM32_SDC_SDIO_IRQ_PRIORITY         9
+#define STM32_SDC_WRITE_TIMEOUT_MS          250
+#define STM32_SDC_READ_TIMEOUT_MS           25
+#define STM32_SDC_CLOCK_ACTIVATION_DELAY    10
+#define STM32_SDC_SDIO_UNALIGNED_SUPPORT    TRUE
+#define STM32_SDC_SDIO_DMA_STREAM           STM32_DMA_STREAM_ID(2, 3)
+
+/*
+ * SERIAL driver system settings.
+ */
+#define STM32_SERIAL_USE_USART1             FALSE
+#define STM32_SERIAL_USE_USART2             TRUE
+#define STM32_SERIAL_USE_USART3             FALSE
+#define STM32_SERIAL_USE_UART4              FALSE
+#define STM32_SERIAL_USE_UART5              FALSE
+#define STM32_SERIAL_USE_USART6             FALSE
+#define STM32_SERIAL_USART1_PRIORITY        12
+#define STM32_SERIAL_USART2_PRIORITY        12
+#define STM32_SERIAL_USART3_PRIORITY        12
+#define STM32_SERIAL_UART4_PRIORITY         12
+#define STM32_SERIAL_UART5_PRIORITY         12
+#define STM32_SERIAL_USART6_PRIORITY        12
+
+/*
+ * SPI driver system settings.
+ */
+#define STM32_SPI_USE_SPI1                  FALSE
+#define STM32_SPI_USE_SPI2                  FALSE
+#define STM32_SPI_USE_SPI3                  FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 0)
+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 3)
+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_SPI_SPI1_DMA_PRIORITY         1
+#define STM32_SPI_SPI2_DMA_PRIORITY         1
+#define STM32_SPI_SPI3_DMA_PRIORITY         1
+#define STM32_SPI_SPI1_IRQ_PRIORITY         10
+#define STM32_SPI_SPI2_IRQ_PRIORITY         10
+#define STM32_SPI_SPI3_IRQ_PRIORITY         10
+#define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")
+
+/*
+ * ST driver system settings.
+ */
+#define STM32_ST_IRQ_PRIORITY               8
+#define STM32_ST_USE_TIMER                  2
+
+/*
+ * UART driver system settings.
+ */
+#define STM32_UART_USE_USART1               FALSE
+#define STM32_UART_USE_USART2               FALSE
+#define STM32_UART_USE_USART3               FALSE
+#define STM32_UART_USE_UART4                FALSE
+#define STM32_UART_USE_UART5                FALSE
+#define STM32_UART_USE_USART6               FALSE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 1)
+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 2)
+#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 4)
+#define STM32_UART_UART5_RX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 0)
+#define STM32_UART_UART5_TX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 7)
+#define STM32_UART_USART6_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 2)
+#define STM32_UART_USART6_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART1_IRQ_PRIORITY      12
+#define STM32_UART_USART2_IRQ_PRIORITY      12
+#define STM32_UART_USART3_IRQ_PRIORITY      12
+#define STM32_UART_UART4_IRQ_PRIORITY       12
+#define STM32_UART_UART5_IRQ_PRIORITY       12
+#define STM32_UART_USART6_IRQ_PRIORITY      12
+#define STM32_UART_USART1_DMA_PRIORITY      0
+#define STM32_UART_USART2_DMA_PRIORITY      0
+#define STM32_UART_USART3_DMA_PRIORITY      0
+#define STM32_UART_UART4_DMA_PRIORITY       0
+#define STM32_UART_UART5_DMA_PRIORITY       0
+#define STM32_UART_USART6_DMA_PRIORITY      0
+#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")
+
+/*
+ * USB driver system settings.
+ */
+#define STM32_USB_USE_OTG1                  FALSE
+#define STM32_USB_USE_OTG2                  FALSE
+#define STM32_USB_OTG1_IRQ_PRIORITY         14
+#define STM32_USB_OTG2_IRQ_PRIORITY         14
+#define STM32_USB_OTG1_RX_FIFO_SIZE         512
+#define STM32_USB_OTG2_RX_FIFO_SIZE         1024
+#define STM32_USB_OTG_THREAD_PRIO           LOWPRIO
+#define STM32_USB_OTG_THREAD_STACK_SIZE     128
+#define STM32_USB_OTGFIFO_FILL_BASEPRI      0
+
+/*
+ * header for community drivers.
+ */
+#include "mcuconf_community.h"
+
diff --git a/testhal/STM32/STM32F4xx/EICU/mcuconf_community.h b/testhal/STM32/STM32F4xx/EICU/mcuconf_community.h
new file mode 100644
index 0000000..adc9d92
--- /dev/null
+++ b/testhal/STM32/STM32F4xx/EICU/mcuconf_community.h
@@ -0,0 +1,79 @@
+/*
+    ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * FSMC driver system settings.
+ */
+#define STM32_FSMC_USE_FSMC1                FALSE
+#define STM32_FSMC_FSMC1_IRQ_PRIORITY       10
+
+/*
+ * FSMC NAND driver system settings.
+ */
+#define STM32_NAND_USE_FSMC_NAND1           FALSE
+#define STM32_NAND_USE_FSMC_NAND2           FALSE
+#define STM32_NAND_USE_EXT_INT              FALSE
+#define STM32_NAND_DMA_STREAM               STM32_DMA_STREAM_ID(2, 7)
+#define STM32_NAND_DMA_PRIORITY             0
+#define STM32_NAND_DMA_ERROR_HOOK(nandp)    osalSysHalt("DMA failure")
+
+/*
+ * FSMC SRAM driver system settings.
+ */
+#define STM32_USE_FSMC_SRAM                 FALSE
+#define STM32_SRAM_USE_FSMC_SRAM1           FALSE
+#define STM32_SRAM_USE_FSMC_SRAM2           FALSE
+#define STM32_SRAM_USE_FSMC_SRAM3           FLASE
+#define STM32_SRAM_USE_FSMC_SRAM4           FALSE
+
+/*
+ * FSMC PC card driver system settings.
+ */
+#define STM32_USE_FSMC_PCARD                FALSE
+
+/*
+ * FSMC SDRAM driver system settings.
+ */
+#define STM32_USE_FSMC_SDRAM                FALSE
+
+/*
+ * EICU driver system settings.
+ */
+#define STM32_EICU_USE_TIM1                 FALSE
+#define STM32_EICU_USE_TIM2                 FALSE
+#define STM32_EICU_USE_TIM3                 TRUE
+#define STM32_EICU_USE_TIM4                 FALSE
+#define STM32_EICU_USE_TIM5                 FALSE
+#define STM32_EICU_USE_TIM8                 FALSE
+#define STM32_EICU_USE_TIM9                 FALSE
+#define STM32_EICU_USE_TIM10                FALSE
+#define STM32_EICU_USE_TIM11                FALSE
+#define STM32_EICU_USE_TIM12                FALSE
+#define STM32_EICU_USE_TIM13                FALSE
+#define STM32_EICU_USE_TIM14                FALSE
+#define STM32_EICU_TIM1_IRQ_PRIORITY        7
+#define STM32_EICU_TIM2_IRQ_PRIORITY        7
+#define STM32_EICU_TIM3_IRQ_PRIORITY        7
+#define STM32_EICU_TIM4_IRQ_PRIORITY        7
+#define STM32_EICU_TIM5_IRQ_PRIORITY        7
+#define STM32_EICU_TIM8_IRQ_PRIORITY        7
+#define STM32_EICU_TIM9_IRQ_PRIORITY        7
+#define STM32_EICU_TIM10_IRQ_PRIORITY       7
+#define STM32_EICU_TIM11_IRQ_PRIORITY       7
+#define STM32_EICU_TIM12_IRQ_PRIORITY       7
+#define STM32_EICU_TIM13_IRQ_PRIORITY       7
+#define STM32_EICU_TIM14_IRQ_PRIORITY       7
+
diff --git a/testhal/STM32/STM32F4xx/EICU/os b/testhal/STM32/STM32F4xx/EICU/os
new file mode 120000
index 0000000..18fd3d9
--- /dev/null
+++ b/testhal/STM32/STM32F4xx/EICU/os
@@ -0,0 +1 @@
+../../../../../os
+\ No newline at end of file
diff --git a/testhal/STM32/STM32F4xx/EICU/readme.txt b/testhal/STM32/STM32F4xx/EICU/readme.txt
new file mode 100644
index 0000000..2f45f99
--- /dev/null
+++ b/testhal/STM32/STM32F4xx/EICU/readme.txt
@@ -0,0 +1,32 @@
+*****************************************************************************
+** ChibiOS/RT HAL - 1-Wire driver demo for STM32F4xx.                      **
+*****************************************************************************
+
+** TARGET **
+
+The demo will on an STMicroelectronics STM32F4-Discovery board.
+
+** The Demo **
+
+The application demonstrates the use of the STM32F4xx 1-Wire driver.
+
+** Board Setup **
+
+To use demo you have to power your 1-wire device from 5V bus on board
+and connect DQ line to PB0 pin. Do not forget about external pullup
+resistor to 5V (4k7 recommended).
+
+** Build Procedure **
+
+The demo has been tested using the free Codesourcery GCC-based toolchain
+and YAGARTO.
+Just modify the TRGT line in the makefile in order to use different GCC ports.
+
+** Notes **
+
+Some files used by the demo are not part of ChibiOS/RT but are copyright of
+ST Microelectronics and are licensed under a different license.
+Also note that not all the files present in the ST library are distributed
+with ChibiOS/RT, you can find the whole library on the ST web site:
+
+                             http://www.st.com
author	barthess <barthess@yandex.ru>	2015-07-07 01:04:55 +0000
committer	barthess <barthess@yandex.ru>	2015-07-07 01:04:55 +0000
commit	4d1b35fca4d266a92cc09b3b6d733b822d0242f5 (patch)
tree	ca193c08c9e0db6a464f9d606eb1cb1ab1c37584 /testhal
parent	95da8798dd924b6eceb60c41f26d262d83799acb (diff)
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