Organized Tiva LLD folder.

4 files changed, 2711 insertions, 0 deletions

diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c b/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c
new file mode 100644
index 0000000..efe6421
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c
@@ -0,0 +1,981 @@
+/*
+    Copyright (C) 2014..2016 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    Tiva/ext_lld.c
+ * @brief   Tiva EXT subsystem low level driver source.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/**
+ * @brief   Generic interrupt serving code for multiple pins per interrupt
+ *          handler.
+ */
+#define ext_lld_serve_port_interrupt(gpiop, start)                            \
+  do {                                                                        \
+    uint32_t mis = gpiop->MIS;                                                \
+                                                                              \
+    gpiop->ICR = mis;                                                         \
+                                                                              \
+    if (mis & (1 << 0)) {                                                     \
+      EXTD1.config->channels[start + 0].cb(&EXTD1, start + 0);                \
+    }                                                                         \
+    if (mis & (1 << 1)) {                                                     \
+      EXTD1.config->channels[start + 1].cb(&EXTD1, start + 1);                \
+    }                                                                         \
+    if (mis & (1 << 2)) {                                                     \
+      EXTD1.config->channels[start + 2].cb(&EXTD1, start + 2);                \
+    }                                                                         \
+    if (mis & (1 << 3)) {                                                     \
+      EXTD1.config->channels[start + 3].cb(&EXTD1, start + 3);                \
+    }                                                                         \
+    if (mis & (1 << 4)) {                                                     \
+      EXTD1.config->channels[start + 4].cb(&EXTD1, start + 4);                \
+    }                                                                         \
+    if (mis & (1 << 5)) {                                                     \
+      EXTD1.config->channels[start + 5].cb(&EXTD1, start + 5);                \
+    }                                                                         \
+    if (mis & (1 << 6)) {                                                     \
+      EXTD1.config->channels[start + 6].cb(&EXTD1, start + 6);                \
+    }                                                                         \
+    if (mis & (1 << 7)) {                                                     \
+      EXTD1.config->channels[start + 7].cb(&EXTD1, start + 7);                \
+    }                                                                         \
+  } while (0);
+
+/**
+ * @brief   Generic interrupt serving code for single pin per interrupt
+ *          handler.
+ */
+#define ext_lld_serve_pin_interrupt(gpiop, start, pin)                        \
+  do {                                                                        \
+    gpiop->ICR = (1 << pin);                                                  \
+    EXTD1.config->channels[start].cb(&EXTD1, start);                          \
+  } while (0);
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   EXTD1 driver identifier.
+ */
+EXTDriver EXTD1;
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+const ioportid_t gpio[] =
+{
+#if TIVA_HAS_GPIOA
+  GPIOA,
+#endif
+#if TIVA_HAS_GPIOB
+  GPIOB,
+#endif
+#if TIVA_HAS_GPIOC
+  GPIOC,
+#endif
+#if TIVA_HAS_GPIOD
+  GPIOD,
+#endif
+#if TIVA_HAS_GPIOE
+  GPIOE,
+#endif
+#if TIVA_HAS_GPIOF
+  GPIOF,
+#endif
+#if TIVA_HAS_GPIOG
+  GPIOG,
+#endif
+#if TIVA_HAS_GPIOH
+  GPIOH,
+#endif
+#if TIVA_HAS_GPIOJ
+  GPIOJ,
+#endif
+#if TIVA_HAS_GPIOK
+  GPIOK,
+#endif
+#if TIVA_HAS_GPIOL
+  GPIOL,
+#endif
+#if TIVA_HAS_GPIOM
+  GPIOM,
+#endif
+#if TIVA_HAS_GPION
+  GPION,
+#endif
+#if TIVA_HAS_GPIOP
+  GPIOP,
+#endif
+#if TIVA_HAS_GPIOQ
+  GPIOQ,
+#endif
+#if TIVA_HAS_GPIOR
+  GPIOR,
+#endif
+#if TIVA_HAS_GPIOS
+  GPIOS,
+#endif
+#if TIVA_HAS_GPIOT
+  GPIOT,
+#endif
+};
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables GPIO IRQ sources.
+ *
+ * @notapi
+ */
+static void ext_lld_irq_enable(void)
+{
+#if TIVA_HAS_GPIOA
+  nvicEnableVector(TIVA_GPIOA_NUMBER, TIVA_EXT_GPIOA_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOB
+  nvicEnableVector(TIVA_GPIOB_NUMBER, TIVA_EXT_GPIOB_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOC
+  nvicEnableVector(TIVA_GPIOC_NUMBER, TIVA_EXT_GPIOC_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOD
+  nvicEnableVector(TIVA_GPIOD_NUMBER, TIVA_EXT_GPIOD_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOE
+  nvicEnableVector(TIVA_GPIOE_NUMBER, TIVA_EXT_GPIOE_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOF
+  nvicEnableVector(TIVA_GPIOF_NUMBER, TIVA_EXT_GPIOF_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOG
+  nvicEnableVector(TIVA_GPIOG_NUMBER, TIVA_EXT_GPIOG_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOH
+  nvicEnableVector(TIVA_GPIOH_NUMBER, TIVA_EXT_GPIOH_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOJ
+  nvicEnableVector(TIVA_GPIOJ_NUMBER, TIVA_EXT_GPIOJ_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOK
+  nvicEnableVector(TIVA_GPIOK_NUMBER, TIVA_EXT_GPIOK_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOL
+  nvicEnableVector(TIVA_GPIOL_NUMBER, TIVA_EXT_GPIOL_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOM
+  nvicEnableVector(TIVA_GPIOM_NUMBER, TIVA_EXT_GPIOM_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPION
+  nvicEnableVector(TIVA_GPION_NUMBER, TIVA_EXT_GPION_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOP
+  nvicEnableVector(TIVA_GPIOP0_NUMBER, TIVA_EXT_GPIOP0_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP1_NUMBER, TIVA_EXT_GPIOP1_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP2_NUMBER, TIVA_EXT_GPIOP2_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP3_NUMBER, TIVA_EXT_GPIOP3_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP4_NUMBER, TIVA_EXT_GPIOP4_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP5_NUMBER, TIVA_EXT_GPIOP5_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP6_NUMBER, TIVA_EXT_GPIOP6_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP7_NUMBER, TIVA_EXT_GPIOP7_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOQ
+  nvicEnableVector(TIVA_GPIOQ0_NUMBER, TIVA_EXT_GPIOQ0_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ1_NUMBER, TIVA_EXT_GPIOQ1_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ2_NUMBER, TIVA_EXT_GPIOQ2_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ3_NUMBER, TIVA_EXT_GPIOQ3_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ4_NUMBER, TIVA_EXT_GPIOQ4_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ5_NUMBER, TIVA_EXT_GPIOQ5_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ6_NUMBER, TIVA_EXT_GPIOQ6_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ7_NUMBER, TIVA_EXT_GPIOQ7_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOR
+  nvicEnableVector(TIVA_GPIOR_NUMBER, TIVA_EXT_GPIOR_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOS
+  nvicEnableVector(TIVA_GPIOS_NUMBER, TIVA_EXT_GPIOS_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOT
+  nvicEnableVector(TIVA_GPIOT_NUMBER, TIVA_EXT_GPIOT_IRQ_PRIORITY);
+#endif
+}
+
+/**
+ * @brief   Disables GPIO IRQ sources.
+ *
+ * @notapi
+ */
+static void ext_lld_irq_disable(void)
+{
+#if TIVA_HAS_GPIOA
+  nvicDisableVector(TIVA_GPIOA_NUMBER);
+#endif
+#if TIVA_HAS_GPIOB
+  nvicDisableVector(TIVA_GPIOB_NUMBER);
+#endif
+#if TIVA_HAS_GPIOC
+  nvicDisableVector(TIVA_GPIOC_NUMBER);
+#endif
+#if TIVA_HAS_GPIOD
+  nvicDisableVector(TIVA_GPIOD_NUMBER);
+#endif
+#if TIVA_HAS_GPIOE
+  nvicDisableVector(TIVA_GPIOE_NUMBER);
+#endif
+#if TIVA_HAS_GPIOF
+  nvicDisableVector(TIVA_GPIOF_NUMBER);
+#endif
+#if TIVA_HAS_GPIOG
+  nvicDisableVector(TIVA_GPIOG_NUMBER);
+#endif
+#if TIVA_HAS_GPIOH
+  nvicDisableVector(TIVA_GPIOH_NUMBER);
+#endif
+#if TIVA_HAS_GPIOJ
+  nvicDisableVector(TIVA_GPIOJ_NUMBER);
+#endif
+#if TIVA_HAS_GPIOK
+  nvicDisableVector(TIVA_GPIOK_NUMBER);
+#endif
+#if TIVA_HAS_GPIOL
+  nvicDisableVector(TIVA_GPIOL_NUMBER);
+#endif
+#if TIVA_HAS_GPIOM
+  nvicDisableVector(TIVA_GPIOM_NUMBER);
+#endif
+#if TIVA_HAS_GPION
+  nvicDisableVector(TIVA_GPION_NUMBER);
+#endif
+#if TIVA_HAS_GPIOP
+  nvicDisableVector(TIVA_GPIOP0_NUMBER);
+  nvicDisableVector(TIVA_GPIOP1_NUMBER);
+  nvicDisableVector(TIVA_GPIOP2_NUMBER);
+  nvicDisableVector(TIVA_GPIOP3_NUMBER);
+  nvicDisableVector(TIVA_GPIOP4_NUMBER);
+  nvicDisableVector(TIVA_GPIOP5_NUMBER);
+  nvicDisableVector(TIVA_GPIOP6_NUMBER);
+  nvicDisableVector(TIVA_GPIOP7_NUMBER);
+#endif
+#if TIVA_HAS_GPIOQ
+  nvicDisableVector(TIVA_GPIOQ0_NUMBER);
+  nvicDisableVector(TIVA_GPIOQ1_NUMBER);
+  nvicDisableVector(TIVA_GPIOQ2_NUMBER);
+  nvicDisableVector(TIVA_GPIOQ3_NUMBER);
+  nvicDisableVector(TIVA_GPIOQ4_NUMBER);
+  nvicDisableVector(TIVA_GPIOQ5_NUMBER);
+  nvicDisableVector(TIVA_GPIOQ6_NUMBER);
+  nvicDisableVector(TIVA_GPIOQ7_NUMBER);
+#endif
+#if TIVA_HAS_GPIOR
+  nvicDisableVector(TIVA_GPIOR_NUMBER);
+#endif
+#if TIVA_HAS_GPIOS
+  nvicDisableVector(TIVA_GPIOS_NUMBER);
+#endif
+#if TIVA_HAS_GPIOT
+  nvicDisableVector(TIVA_GPIOT_NUMBER);
+#endif
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if TIVA_HAS_GPIOA || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOA interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOA_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOA, 0);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOB || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOB interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOB_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOB, 8);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOC || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOC interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOC_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOC, 16);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOD || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOD interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOD_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOD, 24);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOE || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOE interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOE_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOE, 32);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOF || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOF interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOF_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOF, 40);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOG interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOG_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(&GPIOG, 48);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOH interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOH_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(&GPIOH, 56);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOJ interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOJ_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(&GPIOJ, 64);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOK interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOK_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(&GPIOK, 72);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOL interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOL_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(&GPIOL, 80);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOM interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOM_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(&GPIOM, 88);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPION || defined(__DOXYGEN__)
+/**
+ * @brief   GPION interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPION_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(&GPION, 96);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOP0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOP0_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(&GPIOP, 104, 0);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOP1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOP1_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(&GPIOP, 105, 1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOP2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOP2_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(&GPIOP, 106, 2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOP3 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOP3_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(&GPIOP, 107, 3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOP4 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOP4_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(&GPIOP, 108, 4);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOP5 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOP5_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(&GPIOP, 109, 5);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOP6 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOP6_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(&GPIOP, 110, 6);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOP7 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOP7_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(&GPIOP, 111, 7);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOQ0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOQ0_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(&GPIOQ, 112, 0);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOQ1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOQ1_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(&GPIOQ, 113, 1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOQ2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOQ2_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(&GPIOQ, 114, 2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOQ3 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOQ3_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(&GPIOQ, 115, 3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOQ4 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOQ4_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(&GPIOQ, 116, 4);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOQ5 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOQ5_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(&GPIOQ, 117, 5);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOQ6 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOQ6_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(&GPIOQ, 118, 6);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOQ7 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOQ7_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(&GPIOQ, 119, 7);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOR interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOR_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(&GPIOR, 120);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOS interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOS_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(&GPIOS, 128);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOT interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOT_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(&GPIOT, 132);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level EXT driver initialization.
+ *
+ * @notapi
+ */
+void ext_lld_init(void)
+{
+  extObjectInit(&EXTD1);
+}
+
+/**
+ * @brief   Configures and activates the EXT peripheral.
+ *
+ * @param[in] extp      pointer to the @p EXTDriver object
+ *
+ * @notapi
+ */
+void ext_lld_start(EXTDriver *extp)
+{
+  uint8_t i;
+
+  if (extp->state == EXT_STOP) {
+    ext_lld_irq_enable();
+  }
+
+  /* Configuration of automatic channels.*/
+  for (i = 0; i < EXT_MAX_CHANNELS; i++) {
+    if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART) {
+      ext_lld_channel_enable(extp, i);
+    }
+    else {
+      ext_lld_channel_disable(extp, i);
+    }
+  }
+}
+
+/**
+ * @brief   Deactivates the EXT peripheral.
+ *
+ * @param[in] extp      pointer to the @p EXTDriver object
+ *
+ * @notapi
+ */
+void ext_lld_stop(EXTDriver *extp)
+{
+  if (extp->state == EXT_ACTIVE) {
+    ext_lld_irq_disable();
+  }
+
+#if TIVA_HAS_GPIOA
+  GPIOA->IM = 0;
+#endif
+#if TIVA_HAS_GPIOB
+  GPIOB->IM = 0;
+#endif
+#if TIVA_HAS_GPIOC
+  GPIOC->IM = 0;
+#endif
+#if TIVA_HAS_GPIOD
+  GPIOD->IM = 0;
+#endif
+#if TIVA_HAS_GPIOE
+  GPIOE->IM = 0;
+#endif
+#if TIVA_HAS_GPIOF
+  GPIOF->IM = 0;
+#endif
+#if TIVA_HAS_GPIOG
+  GPIOG->IM = 0;
+#endif
+#if TIVA_HAS_GPIOH
+  GPIOH->IM = 0;
+#endif
+#if TIVA_HAS_GPIOJ
+  GPIOJ->IM = 0;
+#endif
+#if TIVA_HAS_GPIOK
+  GPIOK->IM = 0;
+#endif
+#if TIVA_HAS_GPIOL
+  GPIOL->IM = 0;
+#endif
+#if TIVA_HAS_GPIOM
+  GPIOM->IM = 0;
+#endif
+#if TIVA_HAS_GPION
+  GPION->IM = 0;
+#endif
+#if TIVA_HAS_GPIOP
+  GPIOP->IM = 0;
+#endif
+#if TIVA_HAS_GPIOQ
+  GPIOQ->IM = 0;
+#endif
+#if TIVA_HAS_GPIOR
+  GPIOR->IM = 0;
+#endif
+#if TIVA_HAS_GPIOS
+  GPIOS->IM = 0;
+#endif
+#if TIVA_HAS_GPIOT
+  GPIOT->IM = 0;
+#endif
+}
+
+/**
+ * @brief   Enables an EXT channel.
+ *
+ * @param[in] extp      pointer to the @p EXTDriver object
+ * @param[in] channel   channel to be enabled
+ *
+ * @notapi
+ */
+void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel)
+{
+  GPIO_TypeDef *gpiop;
+  uint8_t pin;
+  uint32_t im;
+
+  pin = channel & 0x07;
+  gpiop = gpio[channel >> 3];
+
+  /* Disable interrupts */
+  im = gpiop->IM;
+  gpiop->IM = 0;
+
+  /* Configure pin to be edge-sensitive.*/
+  gpiop->IS &= ~(1 << pin);
+
+  /* Programming edge registers.*/
+  if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) ==
+      EXT_CH_MODE_BOTH_EDGES) {
+    gpiop->IBE |= (1 << pin);
+  }
+  else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) ==
+      EXT_CH_MODE_FALLING_EDGE) {
+    gpiop->IBE &= ~(1 << pin);
+    gpiop->IEV &= ~(1 << pin);
+  }
+  else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) ==
+      EXT_CH_MODE_RISING_EDGE) {
+    gpiop->IBE &= ~(1 << pin);
+    gpiop->IEV |= (1 << pin);
+  }
+
+  /* Programming interrupt and event registers.*/
+  if ((extp->config->channels[channel].cb != NULL) &&
+      ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) !=
+          EXT_CH_MODE_DISABLED)) {
+    im |= (1 << pin);
+  }
+  else {
+    im &= ~(1 << pin);
+  }
+
+  /* Restore interrupts */
+  gpiop->IM = im;
+}
+
+/**
+ * @brief   Disables an EXT channel.
+ *
+ * @param[in] extp      pointer to the @p EXTDriver object
+ * @param[in] channel   channel to be disabled
+ *
+ * @notapi
+ */
+void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel)
+{
+  (void)extp;
+  GPIO_TypeDef *gpiop;
+  uint8_t pin;
+
+  pin = channel & 0x07;
+  gpiop = gpio[channel >> 3];
+
+  gpiop->IM &= ~(1 << pin);
+}
+
+#endif /* HAL_USE_EXT */
+
+/** @} */
diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.h b/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.h
new file mode 100644
index 0000000..08accb2
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.h
@@ -0,0 +1,523 @@
+/*
+    Copyright (C) 2014..2016 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    Tiva/ext_lld.h
+ * @brief   Tiva EXT subsystem low level driver header.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#ifndef HAL_EXT_LLD_H
+#define HAL_EXT_LLD_H
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Number of EXT per port.
+ */
+#define EXT_MAX_CHANNELS    TIVA_GPIO_PINS
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   GPIOA interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOA_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOB interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOB_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOB_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOC interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOC_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOC_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOD interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOD_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOD_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOE interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOE_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOE_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOF interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOF_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOF_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOG interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOG_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOG_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOH interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOH_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOH_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOJ interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOJ_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOJ_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOK interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOK_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOK_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOL interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOL_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOL_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOM interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOM_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOM_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPION interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPION_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPION_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOP0 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOP0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOP0_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOP1 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOP1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOP1_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOP2 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOP2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOP2_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOP3 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOP3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOP3_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOP4 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOP4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOP4_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOP5 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOP5_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOP5_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOP6 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOP6_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOP6_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOP7 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOP7_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOP7_IRQ_PRIORITY        3
+#endif
+/** @} */
+
+/**
+ * @brief   GPIOQ0 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOQ0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOQ0_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOQ1 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOQ1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOQ1_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOQ2 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOQ2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOQ2_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOQ3 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOQ3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOQ3_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOQ4 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOQ4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOQ4_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOQ5 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOQ5_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOQ5_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOQ6 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOQ6_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOQ6_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOQ7 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOQ7_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOQ7_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOR interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOR_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOR_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOS interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOS_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOS_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOT interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOT_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOT_IRQ_PRIORITY         3
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if TIVA_HAS_GPIOA &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOA"
+#endif
+
+#if TIVA_HAS_GPIOB &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOB_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOB"
+#endif
+
+#if TIVA_HAS_GPIOC &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOC_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOC"
+#endif
+
+#if TIVA_HAS_GPIOD &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOD_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOD"
+#endif
+
+#if TIVA_HAS_GPIOE &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOE_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOE"
+#endif
+
+#if TIVA_HAS_GPIOF &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOF_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOF"
+#endif
+
+#if TIVA_HAS_GPIOG &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOG_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOG"
+#endif
+
+#if TIVA_HAS_GPIOH &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOH_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOH"
+#endif
+
+#if TIVA_HAS_GPIOJ &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOJ_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOJ"
+#endif
+
+#if TIVA_HAS_GPIOK &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOK_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOK"
+#endif
+
+#if TIVA_HAS_GPIOL &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOL_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOL"
+#endif
+
+#if TIVA_HAS_GPIOM &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOM_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOM"
+#endif
+
+#if TIVA_HAS_GPION &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPION_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPION"
+#endif
+
+#if TIVA_HAS_GPIOP0 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOP0"
+#endif
+
+#if TIVA_HAS_GPIOP1 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOP1"
+#endif
+
+#if TIVA_HAS_GPIOP2 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOP2"
+#endif
+
+#if TIVA_HAS_GPIOP3 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOP3"
+#endif
+
+#if TIVA_HAS_GPIOP4 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP4_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOP4"
+#endif
+
+#if TIVA_HAS_GPIOP5 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP5_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOP5"
+#endif
+
+#if TIVA_HAS_GPIOP6 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP6_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOP6"
+#endif
+
+#if TIVA_HAS_GPIOP7 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP7_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOP7"
+#endif
+
+#if TIVA_HAS_GPIOQ0 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOQ0"
+#endif
+
+#if TIVA_HAS_GPIOQ1 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOQ1"
+#endif
+
+#if TIVA_HAS_GPIOQ2 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOQ2"
+#endif
+
+#if TIVA_HAS_GPIOQ3 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOQ3"
+#endif
+
+#if TIVA_HAS_GPIOQ4 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ4_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOQ4"
+#endif
+
+#if TIVA_HAS_GPIOQ5 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ5_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOQ5"
+#endif
+
+#if TIVA_HAS_GPIOQ6 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ6_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOQ6"
+#endif
+
+#if TIVA_HAS_GPIOQ7 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ7_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOQ7"
+#endif
+
+#if TIVA_HAS_GPIOR &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOR_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOR"
+#endif
+
+#if TIVA_HAS_GPIOS &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOS_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOS"
+#endif
+
+#if TIVA_HAS_GPIOT &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOT_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOT"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   EXT channel identifier.
+ */
+typedef uint32_t expchannel_t;
+
+/**
+ * @brief   Type of an EXT generic notification callback.
+ *
+ * @param[in] extp      pointer to the @p EXPDriver object triggering the
+ *                      callback
+ */
+typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel);
+
+/**
+ * @brief   Channel configuration structure.
+ */
+typedef struct {
+  /**
+   * @brief Channel mode.
+   */
+  uint32_t              mode;
+  /**
+   * @brief Channel callback.
+   */
+  extcallback_t         cb;
+} EXTChannelConfig;
+
+/**
+ * @brief   Driver configuration structure.
+ * @note    It could be empty on some architectures.
+ */
+typedef struct {
+  /**
+   * @brief Channel configurations.
+   */
+  EXTChannelConfig      channels[EXT_MAX_CHANNELS];
+  /* End of the mandatory fields.*/
+} EXTConfig;
+
+/**
+ * @brief   Structure representing an EXT driver.
+ */
+struct EXTDriver {
+  /**
+   * @brief Driver state.
+   */
+  extstate_t                state;
+  /**
+   * @brief Current configuration data.
+   */
+  const EXTConfig           *config;
+  /* End of the mandatory fields.*/
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern EXTDriver EXTD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void ext_lld_init(void);
+  void ext_lld_start(EXTDriver *extp);
+  void ext_lld_stop(EXTDriver *extp);
+  void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel);
+  void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_EXT */
+
+#endif /* HAL_EXT_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c
new file mode 100644
index 0000000..5460fd4
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c
@@ -0,0 +1,445 @@
+/*
+    Copyright (C) 2014..2016 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    TIVA/LLD/pal_lld.c
+ * @brief   TM4C123x/TM4C129x PAL subsystem low level driver.
+ *
+ * @addtogroup PAL
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#if TIVA_HAS_GPIOA || defined(__DOXYGEN__)
+#define GPIOA_BIT       (1 << 0)
+#if TIVA_GPIO_GPIOA_USE_AHB && defined(TM4C123x)
+#define GPIOA_AHB_BIT   (1 << 0)
+#else
+#define GPIOA_AHB_BIT   0
+#endif
+#else
+#define GPIOA_BIT       0
+#define GPIOA_AHB_BIT   0
+#endif
+
+#if TIVA_HAS_GPIOB || defined(__DOXYGEN__)
+#define GPIOB_BIT       (1 << 1)
+#if TIVA_GPIO_GPIOB_USE_AHB && defined(TM4C123x)
+#define GPIOB_AHB_BIT   (1 << 1)
+#else
+#define GPIOB_AHB_BIT   0
+#endif
+#else
+#define GPIOB_BIT       0
+#define GPIOB_AHB_BIT   0
+#endif
+
+#if TIVA_HAS_GPIOC || defined(__DOXYGEN__)
+#define GPIOC_BIT       (1 << 2)
+#if TIVA_GPIO_GPIOC_USE_AHB && defined(TM4C123x)
+#define GPIOC_AHB_BIT   (1 << 2)
+#else
+#define GPIOC_AHB_BIT   0
+#endif
+#else
+#define GPIOC_BIT       0
+#define GPIOC_AHB_BIT   0
+#endif
+
+#if TIVA_HAS_GPIOD || defined(__DOXYGEN__)
+#define GPIOD_BIT       (1 << 3)
+#if TIVA_GPIO_GPIOD_USE_AHB && defined(TM4C123x)
+#define GPIOD_AHB_BIT   (1 << 3)
+#else
+#define GPIOD_AHB_BIT   0
+#endif
+#else
+#define GPIOD_BIT       0
+#define GPIOD_AHB_BIT   0
+#endif
+
+#if TIVA_HAS_GPIOE || defined(__DOXYGEN__)
+#define GPIOE_BIT       (1 << 4)
+#if TIVA_GPIO_GPIOE_USE_AHB && defined(TM4C123x)
+#define GPIOE_AHB_BIT   (1 << 4)
+#else
+#define GPIOE_AHB_BIT   0
+#endif
+#else
+#define GPIOE_BIT       0
+#define GPIOE_AHB_BIT   0
+#endif
+
+#if TIVA_HAS_GPIOF || defined(__DOXYGEN__)
+#define GPIOF_BIT       (1 << 5)
+#if TIVA_GPIO_GPIOF_USE_AHB && defined(TM4C123x)
+#define GPIOF_AHB_BIT   (1 << 5)
+#else
+#define GPIOF_AHB_BIT   0
+#endif
+#else
+#define GPIOF_BIT       0
+#define GPIOF_AHB_BIT   0
+#endif
+
+#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
+#define GPIOG_BIT       (1 << 6)
+#if TIVA_GPIO_GPIOG_USE_AHB && defined(TM4C123x)
+#define GPIOG_AHB_BIT   (1 << 6)
+#else
+#define GPIOG_AHB_BIT   0
+#endif
+#else
+#define GPIOG_BIT       0
+#define GPIOG_AHB_BIT   0
+#endif
+
+#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
+#define GPIOH_BIT       (1 << 7)
+#if TIVA_GPIO_GPIOH_USE_AHB && defined(TM4C123x)
+#define GPIOH_AHB_BIT   (1 << 7)
+#else
+#define GPIOH_AHB_BIT   0
+#endif
+#else
+#define GPIOH_BIT       0
+#define GPIOH_AHB_BIT   0
+#endif
+
+#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
+#define GPIOJ_BIT       (1 << 8)
+#if TIVA_GPIO_GPIOJ_USE_AHB && defined(TM4C123x)
+#define GPIOJ_AHB_BIT   (1 << 8)
+#else
+#define GPIOJ_AHB_BIT   0
+#endif
+#else
+#define GPIOJ_BIT       0
+#define GPIOJ_AHB_BIT   0
+#endif
+
+#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
+#define GPIOK_BIT       (1 << 9)
+#define GPIOK_AHB_BIT   (1 << 9)
+#else
+#define GPIOK_BIT       0
+#define GPIOK_AHB_BIT   0
+#endif
+
+#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
+#define GPIOL_BIT       (1 << 10)
+#define GPIOL_AHB_BIT   (1 << 10)
+#else
+#define GPIOL_BIT       0
+#define GPIOL_AHB_BIT   0
+#endif
+
+#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
+#define GPIOM_BIT       (1 << 11)
+#define GPIOM_AHB_BIT   (1 << 11)
+#else
+#define GPIOM_BIT       0
+#define GPIOM_AHB_BIT   0
+#endif
+
+#if TIVA_HAS_GPION || defined(__DOXYGEN__)
+#define GPION_BIT       (1 << 12)
+#define GPION_AHB_BIT   (1 << 12)
+#else
+#define GPION_BIT       0
+#define GPION_AHB_BIT   0
+#endif
+
+#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
+#define GPIOP_BIT       (1 << 13)
+#define GPIOP_AHB_BIT   (1 << 13)
+#else
+#define GPIOP_BIT       0
+#define GPIOP_AHB_BIT   0
+#endif
+
+#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
+#define GPIOQ_BIT       (1 << 14)
+#define GPIOQ_AHB_BIT   (1 << 14)
+#else
+#define GPIOQ_BIT       0
+#define GPIOQ_AHB_BIT   0
+#endif
+
+#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
+#define GPIOR_BIT       (1 << 15)
+#define GPIOR_AHB_BIT   (1 << 15)
+#else
+#define GPIOR_BIT       0
+#define GPIOR_AHB_BIT   0
+#endif
+
+#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
+#define GPIOS_BIT       (1 << 16)
+#define GPIOS_AHB_BIT   (1 << 16)
+#else
+#define GPIOS_BIT       0
+#define GPIOS_AHB_BIT   0
+#endif
+
+#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
+#define GPIOT_BIT       (1 << 17)
+#define GPIOT_AHB_BIT   (1 << 17)
+#else
+#define GPIOT_BIT       0
+#define GPIOT_AHB_BIT   0
+#endif
+
+#define RCGCGPIO_MASK   (GPIOA_BIT | GPIOB_BIT | GPIOC_BIT | GPIOD_BIT |      \
+                         GPIOE_BIT | GPIOF_BIT | GPIOG_BIT | GPIOH_BIT |      \
+                         GPIOJ_BIT | GPIOK_BIT | GPIOL_BIT | GPIOM_BIT |      \
+                         GPION_BIT | GPIOP_BIT | GPIOQ_BIT | GPIOR_BIT |      \
+                         GPIOS_BIT | GPIOR_BIT)
+
+#define GPIOHBCTL_MASK  (GPIOA_AHB_BIT | GPIOB_AHB_BIT | GPIOC_AHB_BIT |      \
+                         GPIOD_AHB_BIT | GPIOE_AHB_BIT | GPIOF_AHB_BIT |      \
+                         GPIOG_AHB_BIT | GPIOH_AHB_BIT | GPIOJ_AHB_BIT |      \
+                         GPIOK_AHB_BIT | GPIOL_AHB_BIT | GPIOM_AHB_BIT |      \
+                         GPION_AHB_BIT | GPIOP_AHB_BIT | GPIOQ_AHB_BIT |      \
+                         GPIOR_AHB_BIT | GPIOS_AHB_BIT | GPIOT_AHB_BIT)
+
+/* GPIO lock password.*/
+#define TIVA_GPIO_LOCK_PWD                  0x4C4F434B
+
+#define GPIOC_JTAG_MASK     (0x0F)
+#define GPIOD_NMI_MASK      (0x80)
+#define GPIOF_NMI_MASK      (0x01)
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Initializes the port with the port configuration.
+ *
+ * @param[in] port      the port identifier
+ * @param[in] config    the port configuration
+ */
+static void gpio_init(ioportid_t port, const tiva_gpio_setup_t *config)
+{
+  port->DATA   = config->data;
+  port->DIR    = config->dir;
+  port->AFSEL  = config->afsel;
+  port->DR2R   = config->dr2r;
+  port->DR4R   = config->dr4r;
+  port->DR8R   = config->dr8r;
+  port->ODR    = config->odr;
+  port->PUR    = config->pur;
+  port->PDR    = config->pdr;
+  port->SLR    = config->slr;
+  port->DEN    = config->den;
+  port->AMSEL  = config->amsel;
+  port->PCTL   = config->pctl;
+}
+
+/**
+ * @brief   Unlocks the masked pins of the GPIO peripheral.
+ * @note    This function is only useful for PORTC0-3, PORTD7 and PORTF0.
+ *
+ * @param[in] port      the port identifier
+ * @param[in] mask      the pin mask
+ */
+static void gpio_unlock(ioportid_t port, ioportmask_t mask)
+{
+  port->LOCK = TIVA_GPIO_LOCK_PWD;
+  port->CR = mask;
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Tiva I/O ports configuration.
+ * @details Ports A-F (G, H, J, K, L, M, N, P, Q, R, S, T) clocks enabled.
+ *
+ * @param[in] config    the Tiva ports configuration
+ *
+ * @notapi
+ */
+void _pal_lld_init(const PALConfig *config)
+{
+  /*
+   * Enables all GPIO clocks.
+   */
+  SYSCTL->RCGCGPIO = RCGCGPIO_MASK;
+#if defined(TM4C123x)
+  SYSCTL->GPIOHBCTL = GPIOHBCTL_MASK;
+#endif
+
+  /* Wait until all GPIO modules are ready */
+  while (!((SYSCTL->PRGPIO & RCGCGPIO_MASK) == RCGCGPIO_MASK))
+    ;
+  
+#if TIVA_HAS_GPIOA
+  gpio_init(GPIOA, &config->PAData);
+#endif
+#if TIVA_HAS_GPIOB
+  gpio_init(GPIOB, &config->PBData);
+#endif
+#if TIVA_HAS_GPIOC
+  /* Unlock JTAG pins.*/
+  gpio_unlock(GPIOC, GPIOC_JTAG_MASK);
+  gpio_init(GPIOC, &config->PCData);
+#endif
+#if TIVA_HAS_GPIOD
+  /* Unlock NMI pin.*/
+  gpio_unlock(GPIOD, GPIOD_NMI_MASK);
+  gpio_init(GPIOD, &config->PDData);
+#endif
+#if TIVA_HAS_GPIOE
+  gpio_init(GPIOE, &config->PEData);
+#endif
+#if TIVA_HAS_GPIOF
+  /* Unlock NMI pin.*/
+  gpio_unlock(GPIOF, GPIOF_NMI_MASK);
+  gpio_init(GPIOF, &config->PFData);
+#endif
+#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
+  gpio_init(GPIOG, &config->PGData);
+#endif
+#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
+  gpio_init(GPIOH, &config->PHData);
+#endif
+#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
+  gpio_init(GPIOJ, &config->PJData);
+#endif
+#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
+  gpio_init(GPIOK, &config->PKData);
+#endif
+#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
+  gpio_init(GPIOL, &config->PLData);
+#endif
+#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
+  gpio_init(GPIOM, &config->PMData);
+#endif
+#if TIVA_HAS_GPION || defined(__DOXYGEN__)
+  gpio_init(GPION, &config->PNData);
+#endif
+#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
+  gpio_init(GPIOP, &config->PPData);
+#endif
+#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
+  gpio_init(GPIOQ, &config->PQData);
+#endif
+#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
+  gpio_init(GPIOR, &config->PRData);
+#endif
+#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
+  gpio_init(GPIOS, &config->PSData);
+#endif
+#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
+  gpio_init(GPIOT, &config->PTData);
+#endif
+}
+
+/**
+ * @brief   Pads mode setup.
+ * @details This function programs a pads group belonging to the same port
+ *          with the specified mode.
+ *
+ * @param[in] port      the port identifier
+ * @param[in] mask      the group mask
+ * @param[in] mode      the mode
+ *
+ * @notapi
+ */
+void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode)
+{
+  uint32_t dir   = (mode & PAL_TIVA_DIR_MASK)   >> 0;
+  uint32_t afsel = (mode & PAL_TIVA_AFSEL_MASK) >> 1;
+  uint32_t dr2r  = (mode & PAL_TIVA_DR2R_MASK)  >> 2;
+  uint32_t dr4r  = (mode & PAL_TIVA_DR4R_MASK)  >> 3;
+  uint32_t dr8r  = (mode & PAL_TIVA_DR8R_MASK)  >> 4;
+  uint32_t odr   = (mode & PAL_TIVA_ODR_MASK)   >> 5;
+  uint32_t pur   = (mode & PAL_TIVA_PUR_MASK)   >> 6;
+  uint32_t pdr   = (mode & PAL_TIVA_PDR_MASK)   >> 7;
+  uint32_t slr   = (mode & PAL_TIVA_SLR_MASK)   >> 8;
+  uint32_t den   = (mode & PAL_TIVA_DEN_MASK)   >> 9;
+  uint32_t amsel = (mode & PAL_TIVA_AMSEL_MASK) >> 10;
+  uint32_t pctl  = (mode & PAL_TIVA_PCTL_MASK)  >> 11;
+  uint32_t bit   = 0;
+
+  while(TRUE) {
+    uint32_t pctl_mask = (7 << (4 * bit));
+    uint32_t bit_mask = (1 << bit);
+
+    if ((mask & 1) != 0) {
+      port->DIR   = (port->DIR   & ~bit_mask)  | dir;
+      port->AFSEL = (port->AFSEL & ~bit_mask)  | afsel;
+      port->DR2R  = (port->DR2R  & ~bit_mask)  | dr2r;
+      port->DR4R  = (port->DR4R  & ~bit_mask)  | dr4r;
+      port->DR8R  = (port->DR8R  & ~bit_mask)  | dr8r;
+      port->ODR   = (port->ODR   & ~bit_mask)  | odr;
+      port->PUR   = (port->PUR   & ~bit_mask)  | pur;
+      port->PDR   = (port->PDR   & ~bit_mask)  | pdr;
+      port->SLR   = (port->SLR   & ~bit_mask)  | slr;
+      port->DEN   = (port->DEN   & ~bit_mask)  | den;
+      port->AMSEL = (port->AMSEL & ~bit_mask)  | amsel;
+      port->PCTL  = (port->PCTL  & ~pctl_mask) | pctl;
+    }
+
+    mask >>= 1;
+    if (!mask) {
+      return;
+    }
+
+    dir   <<= 1;
+    afsel <<= 1;
+    dr2r  <<= 1;
+    dr4r  <<= 1;
+    dr8r  <<= 1;
+    odr   <<= 1;
+    pur   <<= 1;
+    pdr   <<= 1;
+    slr   <<= 1;
+    den   <<= 1;
+    amsel <<= 1;
+    pctl  <<= 4;
+
+    bit++;
+  }
+}
+
+#endif /* HAL_USE_PAL */
+
+/**
+ * @}
+ */
diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
new file mode 100644
index 0000000..c0cd82b
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
@@ -0,0 +1,762 @@
+/*
+    Copyright (C) 2014..2016 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    TIVA/LLD/pal_lld.h
+ * @brief   TM4C123x/TM4C129x PAL subsystem low level driver header.
+ *
+ * @addtogroup PAL
+ * @{
+ */
+
+#ifndef HAL_PAL_LLD_H
+#define HAL_PAL_LLD_H
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+#undef PAL_MODE_RESET
+#undef PAL_MODE_UNCONNECTED
+#undef PAL_MODE_INPUT
+#undef PAL_MODE_INPUT_PULLUP
+#undef PAL_MODE_INPUT_PULLDOWN
+#undef PAL_MODE_INPUT_ANALOG
+#undef PAL_MODE_OUTPUT_PUSHPULL
+#undef PAL_MODE_OUTPUT_OPENDRAIN
+
+/**
+ * @name    TIVA-specific I/O mode flags
+ * @{
+ */
+#define PAL_TIVA_DIR_MASK           (1 << 0)
+#define PAL_TIVA_DIR_INPUT          (0 << 0)
+#define PAL_TIVA_DIR_OUTPUT         (1 << 0)
+
+#define PAL_TIVA_AFSEL_MASK         (1 << 1)
+#define PAL_TIVA_AFSEL_GPIO         (0 << 1)
+#define PAL_TIVA_AFSEL_ALTERNATE    (1 << 1)
+
+#define PAL_TIVA_DR2R_MASK          (1 << 2)
+#define PAL_TIVA_DR2R_DISABLE       (0 << 2)
+#define PAL_TIVA_DR2R_ENABLE        (1 << 2)
+
+#define PAL_TIVA_DR4R_MASK          (1 << 3)
+#define PAL_TIVA_DR4R_DISABLE       (0 << 3)
+#define PAL_TIVA_DR4R_ENABLE        (1 << 3)
+
+#define PAL_TIVA_DR8R_MASK          (1 << 4)
+#define PAL_TIVA_DR8R_DISABLE       (0 << 4)
+#define PAL_TIVA_DR8R_ENABLE        (1 << 4)
+
+#define PAL_TIVA_ODR_MASK           (1 << 5)
+#define PAL_TIVA_ODR_PUSHPULL       (0 << 5)
+#define PAL_TIVA_ODR_OPENDRAIN      (1 << 5)
+
+#define PAL_TIVA_PUR_MASK           (1 << 6)
+#define PAL_TIVA_PUR_DISABLE        (0 << 6)
+#define PAL_TIVA_PUR_ENABLE         (1 << 6)
+
+#define PAL_TIVA_PDR_MASK           (1 << 7)
+#define PAL_TIVA_PDR_DISABLE        (0 << 7)
+#define PAL_TIVA_PDR_ENABLE         (1 << 7)
+
+#define PAL_TIVA_SLR_MASK           (1 << 8)
+#define PAL_TIVA_SLR_DISABLE        (0 << 8)
+#define PAL_TIVA_SLR_ENABLE         (1 << 8)
+
+#define PAL_TIVA_DEN_MASK           (1 << 9)
+#define PAL_TIVA_DEN_DISABLE        (0 << 9)
+#define PAL_TIVA_DEN_ENABLE         (1 << 9)
+
+#define PAL_TIVA_AMSEL_MASK         (1 << 10)
+#define PAL_TIVA_AMSEL_DISABLE      (0 << 10)
+#define PAL_TIVA_AMSEL_ENABLE       (1 << 10)
+
+#define PAL_TIVA_PCTL_MASK          (7 << 11)
+#define PAL_TIVA_PCTL(n)            ((n) << 11)
+
+/**
+ * @brief   Alternate function.
+ *
+ * @param[in] n         alternate function selector
+ */
+#define PAL_MODE_ALTERNATE(n)       (PAL_TIVA_AFSEL_ALTERNATE |               \
+                                     PAL_TIVA_PCTL(n))
+/**
+ * @}
+ */
+
+/**
+ * @name    Standard I/O mode flags
+ * @{
+ */
+/**
+ * @brief   This mode is implemented as input.
+ */
+#define PAL_MODE_RESET                  PAL_MODE_INPUT
+
+/**
+ * @brief   This mode is implemented as input with pull-up.
+ */
+#define PAL_MODE_UNCONNECTED            PAL_MODE_INPUT_PULLUP
+
+/**
+ * @brief   Regular input high-Z pad.
+ */
+#define PAL_MODE_INPUT                  (PAL_TIVA_DEN_ENABLE |                \
+                                         PAL_TIVA_DIR_INPUT)
+
+/**
+ * @brief   Input pad with weak pull up resistor.
+ */
+#define PAL_MODE_INPUT_PULLUP           (PAL_TIVA_DIR_INPUT |                 \
+                                         PAL_TIVA_PUR_ENABLE |                \
+                                         PAL_TIVA_DEN_ENABLE)
+
+/**
+ * @brief   Input pad with weak pull down resistor.
+ */
+#define PAL_MODE_INPUT_PULLDOWN         (PAL_TIVA_DIR_INPUT |                 \
+                                         PAL_TIVA_PDR_ENABLE |                \
+                                         PAL_TIVA_DEN_ENABLE)
+
+/**
+ * @brief   Analog input mode.
+ */
+#define PAL_MODE_INPUT_ANALOG           (PAL_TIVA_DEN_DISABLE |               \
+                                         PAL_TIVA_AMSEL_ENABLE)
+
+/**
+ * @brief   Push-pull output pad.
+ */
+#define PAL_MODE_OUTPUT_PUSHPULL        (PAL_TIVA_DIR_OUTPUT |                \
+                                         PAL_TIVA_DR2R_ENABLE |               \
+                                         PAL_TIVA_ODR_PUSHPULL |              \
+                                         PAL_TIVA_DEN_ENABLE)
+
+/**
+ * @brief   Open-drain output pad.
+ */
+#define PAL_MODE_OUTPUT_OPENDRAIN       (PAL_TIVA_DIR_OUTPUT |                \
+                                         PAL_TIVA_DR2R_ENABLE |               \
+                                         PAL_TIVA_ODR_OPENDRAIN |             \
+                                         PAL_TIVA_DEN_ENABLE)
+/**
+ * @}
+ */
+
+/** @brief   GPIOA port identifier.*/
+#define IOPORT1         GPIOA
+
+/** @brief   GPIOB port identifier.*/
+#define IOPORT2         GPIOB
+
+/** @brief   GPIOC port identifier.*/
+#define IOPORT3         GPIOC
+
+/** @brief   GPIOD port identifier.*/
+#define IOPORT4         GPIOD
+
+/** @brief   GPIOE port identifier.*/
+#define IOPORT5         GPIOE
+
+/** @brief   GPIOF port identifier.*/
+#define IOPORT6         GPIOF
+
+#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
+/** @brief Port G setup data.*/
+#define IOPORT7         GPIOG
+#endif /* TIVA_HAS_GPIOG.*/
+
+#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
+/** @brief Port H setup data.*/
+#define IOPORT8         GPIOH
+#endif /* TIVA_HAS_GPIOH.*/
+
+#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
+/** @brief Port J setup data.*/
+#define IOPORT9         GPIOJ
+#endif /* TIVA_HAS_GPIOJ.*/
+
+#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
+/** @brief Port K setup data.*/
+#define IOPORT10        GPIOK
+#endif /* TIVA_HAS_GPIOK.*/
+
+#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
+/** @brief Port L setup data.*/
+#define IOPORT11        GPIOL
+#endif /* TIVA_HAS_GPIOL.*/
+
+#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
+/** @brief Port M setup data.*/
+#define IOPORT12        GPIOM
+#endif /* TIVA_HAS_GPIOM.*/
+
+#if TIVA_HAS_GPION || defined(__DOXYGEN__)
+/** @brief Port N setup data.*/
+#define IOPORT13        GPION
+#endif /* TIVA_HAS_GPION.*/
+
+#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
+/** @brief Port P setup data.*/
+#define IOPORT14        GPIOP
+#endif /* TIVA_HAS_GPIOP.*/
+
+#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
+/** @brief Port Q setup data.*/
+#define IOPORT15        GPIOQ
+#endif /* TIVA_HAS_GPIOQ.*/
+
+#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
+/** @brief Port R setup data.*/
+#define IOPORT16        GPIOR
+#endif /* TIVA_HAS_GPIOR.*/
+
+#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
+/** @brief Port S setup data.*/
+#define IOPORT17        GPIOS
+#endif /* TIVA_HAS_GPIOS.*/
+
+#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
+/** @brief Port T setup data.*/
+#define IOPORT18        GPIOT
+#endif /* TIVA_HAS_GPIOT.*/
+
+/**
+ * @brief   Width, in bits, of an I/O port.
+ */
+#define PAL_IOPORTS_WIDTH 8
+
+/**
+ * @brief   Whole port mask.
+ * @brief   This macro specifies all the valid bits into a port.
+ */
+#define PAL_WHOLE_PORT ((ioportmask_t)0xFF)
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+#if defined(TM4C123x)
+
+/**
+ * @brief   GPIOA AHB enable switch.
+ * @details When set to @p TRUE the AHB bus is used to access GPIOA. When set
+ *          to @p FALSE the APB bus is used to access GPIOA.
+ * @note    The default is TRUE.
+ */
+#if !defined(TIVA_GPIO_GPIOA_USE_AHB) || defined(__DOXYGEN__)
+#define TIVA_GPIO_GPIOA_USE_AHB             TRUE
+#endif
+
+/**
+ * @brief   GPIOB AHB enable switch.
+ * @details When set to @p TRUE the AHB bus is used to access GPIOB. When set
+ *          to @p FALSE the APB bus is used to access GPIOB.
+ * @note    The default is TRUE.
+ */
+#if !defined(TIVA_GPIO_GPIOB_USE_AHB) || defined(__DOXYGEN__)
+#define TIVA_GPIO_GPIOB_USE_AHB             TRUE
+#endif
+
+/**
+ * @brief   GPIOC AHB enable switch.
+ * @details When set to @p TRUE the AHB bus is used to access GPIOC. When set
+ *          to @p FALSE the APB bus is used to access GPIOC.
+ * @note    The default is TRUE.
+ */
+#if !defined(TIVA_GPIO_GPIOC_USE_AHB) || defined(__DOXYGEN__)
+#define TIVA_GPIO_GPIOC_USE_AHB             TRUE
+#endif
+
+/**
+ * @brief   GPIOD AHB enable switch.
+ * @details When set to @p TRUE the AHB bus is used to access GPIOD. When set
+ *          to @p FALSE the APB bus is used to access GPIOD.
+ * @note    The default is TRUE.
+ */
+#if !defined(TIVA_GPIO_GPIOD_USE_AHB) || defined(__DOXYGEN__)
+#define TIVA_GPIO_GPIOD_USE_AHB             TRUE
+#endif
+
+/**
+ * @brief   GPIOE AHB enable switch.
+ * @details When set to @p TRUE the AHB bus is used to access GPIOE. When set
+ *          to @p FALSE the APB bus is used to access GPIOE.
+ * @note    The default is TRUE.
+ */
+#if !defined(TIVA_GPIO_GPIOE_USE_AHB) || defined(__DOXYGEN__)
+#define TIVA_GPIO_GPIOE_USE_AHB             TRUE
+#endif
+
+/**
+ * @brief   GPIOF AHB enable switch.
+ * @details When set to @p TRUE the AHB bus is used to access GPIOF. When set
+ *          to @p FALSE the APB bus is used to access GPIOF.
+ * @note    The default is TRUE.
+ */
+#if !defined(TIVA_GPIO_GPIOF_USE_AHB) || defined(__DOXYGEN__)
+#define TIVA_GPIO_GPIOF_USE_AHB             TRUE
+#endif
+
+/**
+ * @brief   GPIOG AHB enable switch.
+ * @details When set to @p TRUE the AHB bus is used to access GPIOG. When set
+ *          to @p FALSE the APB bus is used to access GPIOG.
+ * @note    The default is TRUE.
+ */
+#if !defined(TIVA_GPIO_GPIOG_USE_AHB) || defined(__DOXYGEN__)
+#define TIVA_GPIO_GPIOG_USE_AHB             TRUE
+#endif
+
+/**
+ * @brief   GPIOH AHB enable switch.
+ * @details When set to @p TRUE the AHB bus is used to access GPIOH. When set
+ *          to @p FALSE the APB bus is used to access GPIOH.
+ * @note    The default is TRUE.
+ */
+#if !defined(TIVA_GPIO_GPIOH_USE_AHB) || defined(__DOXYGEN__)
+#define TIVA_GPIO_GPIOH_USE_AHB             TRUE
+#endif
+
+/**
+ * @brief   GPIOJ AHB enable switch.
+ * @details When set to @p TRUE the AHB bus is used to access GPIOJ. When set
+ *          to @p FALSE the APB bus is used to access GPIOJ.
+ * @note    The default is TRUE.
+ */
+#if !defined(TIVA_GPIO_GPIOJ_USE_AHB) || defined(__DOXYGEN__)
+#define TIVA_GPIO_GPIOJ_USE_AHB             TRUE
+#endif
+
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if defined(TM4C123x)
+
+#if TIVA_GPIO_GPIOA_USE_AHB
+#define GPIOA                               GPIOA_AHB
+#else
+#define GPIOA                               GPIOA_APB
+#endif
+
+#if TIVA_GPIO_GPIOB_USE_AHB
+#define GPIOB                               GPIOB_AHB
+#else
+#define GPIOB                               GPIOB_APB
+#endif
+
+#if TIVA_GPIO_GPIOC_USE_AHB
+#define GPIOC                               GPIOC_AHB
+#else
+#define GPIOC                               GPIOC_APB
+#endif
+
+#if TIVA_GPIO_GPIOD_USE_AHB
+#define GPIOD                               GPIOD_AHB
+#else
+#define GPIOD                               GPIOD_APB
+#endif
+
+#if TIVA_GPIO_GPIOE_USE_AHB
+#define GPIOE                               GPIOE_AHB
+#else
+#define GPIOE                               GPIOE_APB
+#endif
+
+#if TIVA_GPIO_GPIOF_USE_AHB
+#define GPIOF                               GPIOF_AHB
+#else
+#define GPIOF                               GPIOF_APB
+#endif
+
+#if TIVA_GPIO_GPIOG_USE_AHB
+#define GPIOG                               GPIOG_AHB
+#else
+#define GPIOG                               GPIOG_APB
+#endif
+
+#if TIVA_GPIO_GPIOH_USE_AHB
+#define GPIOH                               GPIOH_AHB
+#else
+#define GPIOH                               GPIOH_APB
+#endif
+
+#if TIVA_GPIO_GPIOJ_USE_AHB
+#define GPIOJ                               GPIOJ_AHB
+#else
+#define GPIOJ                               GPIOJ_APB
+#endif
+
+#define GPIOK                               GPIOK_AHB
+#define GPIOL                               GPIOL_AHB
+#define GPIOM                               GPIOM_AHB
+#define GPION                               GPION_AHB
+#define GPIOP                               GPIOP_AHB
+#define GPIOQ                               GPIOQ_AHB
+
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   GPIO port setup info.
+ */
+typedef struct 
+{
+  /** @brief Initial value for DATA register.*/
+  uint32_t data;
+  /** @brief Initial value for DIR register.*/
+  uint32_t dir;
+  /** @brief Initial value for AFSEL register.*/
+  uint32_t afsel;
+  /** @brief Initial value for DR2R register.*/
+  uint32_t dr2r;
+  /** @brief Initial value for DR4R register.*/
+  uint32_t dr4r;
+  /** @brief Initial value for DR8R register.*/
+  uint32_t dr8r;
+  /** @brief Initial value for ODR register.*/
+  uint32_t odr;
+  /** @brief Initial value for PUR register.*/
+  uint32_t pur;
+  /** @brief Initial value for PDR register.*/
+  uint32_t pdr;
+  /** @brief Initial value for SLR register.*/
+  uint32_t slr;
+  /** @brief Initial value for DEN register.*/
+  uint32_t den;
+  /** @brief Initial value for AMSEL register.*/
+  uint32_t amsel;
+  /** @brief Initial value for PCTL register.*/
+  uint32_t pctl;
+} tiva_gpio_setup_t;
+
+/**
+ * @brief   Tiva GPIO static initializer.
+ * @details An instance of this structure must be passed to @p palInit() at
+ *          system startup time in order to initialized the digital I/O
+ *          subsystem. This represents only the initial setup, specific pads
+ *          or whole ports can be reprogrammed at later time.
+ */
+typedef struct
+{
+  /** @brief Port A setup data.*/
+  tiva_gpio_setup_t     PAData;
+  /** @brief Port B setup data.*/
+  tiva_gpio_setup_t     PBData;
+  /** @brief Port C setup data.*/
+  tiva_gpio_setup_t     PCData;
+  /** @brief Port D setup data.*/
+  tiva_gpio_setup_t     PDData;
+  /** @brief Port E setup data.*/
+  tiva_gpio_setup_t     PEData;
+  /** @brief Port F setup data.*/
+  tiva_gpio_setup_t     PFData;
+
+#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
+  /** @brief Port G setup data.*/
+  tiva_gpio_setup_t     PGData;
+#endif /* TIVA_HAS_GPIOG.*/
+
+#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
+  /** @brief Port H setup data.*/
+  tiva_gpio_setup_t     PHData;
+#endif /* TIVA_HAS_GPIOH.*/
+
+#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
+  /** @brief Port J setup data.*/
+  tiva_gpio_setup_t     PJData;
+#endif /* TIVA_HAS_GPIOJ.*/
+
+#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
+  /** @brief Port K setup data.*/
+  tiva_gpio_setup_t     PKData;
+#endif /* TIVA_HAS_GPIOK.*/
+
+#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
+  /** @brief Port L setup data.*/
+  tiva_gpio_setup_t     PLData;
+#endif /* TIVA_HAS_GPIOL.*/
+
+#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
+  /** @brief Port M setup data.*/
+  tiva_gpio_setup_t     PMData;
+#endif /* TIVA_HAS_GPIOM.*/
+
+#if TIVA_HAS_GPION || defined(__DOXYGEN__)
+  /** @brief Port N setup data.*/
+  tiva_gpio_setup_t     PNData;
+#endif /* TIVA_HAS_GPION.*/
+
+#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
+  /** @brief Port P setup data.*/
+  tiva_gpio_setup_t     PPData;
+#endif /* TIVA_HAS_GPIOP.*/
+
+#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
+  /** @brief Port Q setup data.*/
+  tiva_gpio_setup_t     PQData;
+#endif /* TIVA_HAS_GPIOQ.*/
+
+#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
+  /** @brief Port R setup data.*/
+  tiva_gpio_setup_t     PRData;
+#endif /* TIVA_HAS_GPIOR.*/
+
+#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
+  /** @brief Port S setup data.*/
+  tiva_gpio_setup_t     PSData;
+#endif /* TIVA_HAS_GPIOS.*/
+
+#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
+  /** @brief Port T setup data.*/
+  tiva_gpio_setup_t     PTData;
+#endif /* TIVA_HAS_GPIOT.*/
+} PALConfig;
+
+/**
+ * @brief   Digital I/O port sized unsigned type.
+ */
+typedef uint32_t ioportmask_t;
+
+/**
+ * @brief   Digital I/O modes.
+ */
+typedef uint32_t iomode_t;
+
+/**
+ * @brief   Port Identifier.
+ */
+typedef GPIO_TypeDef *ioportid_t;
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level PAL subsystem initialization.
+ *
+ * @param[in] config    architecture-dependent ports configuration
+ *
+ * @notapi
+ */
+#define pal_lld_init(config) _pal_lld_init(config)
+
+/**
+ * @brief   Reads the physical I/O port states.
+ *
+ * @param[in] port      port identifier
+ * @return              The port bits.
+ *
+ * @notapi
+ */
+#define pal_lld_readport(port)  ((port)->DATA)
+
+/**
+ * @brief   Reads the output latch.
+ * @details The purpose of this function is to read back the latched output
+ *          value.
+ *
+ * @param[in] port      port identifier
+ * @return              The latched logical states.
+ *
+ * @notapi
+ */
+#define pal_lld_readlatch(port) ((port)->DATA)
+
+/**
+ * @brief   Writes a bits mask on a I/O port.
+ *
+ * @param[in] port      port identifier
+ * @param[in] bits      bits to be written on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_writeport(port, bits)   ((port)->DATA = (bits))
+
+/**
+ * @brief   Sets a bits mask on a I/O port.
+ * @note    The @ref PAL provides a default software implementation of this
+ *          functionality, implement this function if can optimize it by using
+ *          special hardware functionalities or special coding.
+ *
+ * @param[in] port      port identifier
+ * @param[in] bits      bits to be ORed on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_setport(port, bits) ((port)->MASKED_ACCESS[bits] = 0xFF)
+
+/**
+ * @brief   Clears a bits mask on a I/O port.
+ * @note    The @ref PAL provides a default software implementation of this
+ *          functionality, implement this function if can optimize it by using
+ *          special hardware functionalities or special coding.
+ *
+ * @param[in] port      port identifier
+ * @param[in] bits      bits to be cleared on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_clearport(port, bits)   ((port)->MASKED_ACCESS[bits] = 0)
+
+/**
+ * @brief   Reads a group of bits.
+ * @note    The @ref PAL provides a default software implementation of this
+ *          functionality, implement this function if can optimize it by using
+ *          special hardware functionalities or special coding.
+ *
+ * @param[in] port      port identifier
+ * @param[in] mask      group mask
+ * @param[in] offset    group bit offset within the port
+ * @return              The group logical states.
+ *
+ * @notapi
+ */
+#define pal_lld_readgroup(port, mask, offset)   \
+  ((port)->MASKED_ACCESS[(mask) << (offset)])
+
+/**
+ * @brief   Writes a group of bits.
+ * @note    The @ref PAL provides a default software implementation of this
+ *          functionality, implement this function if can optimize it by using
+ *          special hardware functionalities or special coding.
+ *
+ * @param[in] port      port identifier
+ * @param[in] mask      group mask
+ * @param[in] offset    group bit offset within the port
+ * @param[in] bits      bits to be written. Values exceeding the group width
+ *                      are masked.
+ *
+ * @notapi
+ */
+#define pal_lld_writegroup(port, mask, offset, bits)    \
+  ((port)->MASKED_ACCESS[(mask) << (offset)] = (bits))
+
+/**
+ * @brief   Pads group mode setup.
+ * @details This function programs a pads group belonging to the same port
+ *          with the specified mode.
+ * @note    Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port      port identifier
+ * @param[in] mask      group mask
+ * @param[in] offset    group bit offset within the port
+ * @param[in] mode      group mode
+ *
+ * @notapi
+ */
+#define pal_lld_setgroupmode(port, mask, offset, mode)                      \
+  _pal_lld_setgroupmode(port, mask << offset, mode)
+
+/**
+ * @brief   Reads a logical state from an I/O pad.
+ * @note    The @ref PAL provides a default software implementation of this
+ *          functionality, implement this function if can optimize it by using
+ *          special hardware functionalities or special coding.
+ *
+ * @param[in] port      port identifier
+ * @param[in] pad       pad number within the port
+ * @return              The logical state.
+ * @retval PAL_LOW      low logical state.
+ * @retval PAL_HIGH     high logical state.
+ *
+ * @notapi
+ */
+#define pal_lld_readpad(port, pad) ((port)->MASKED_ACCESS[1 << (pad)])
+
+/**
+ * @brief   Writes a logical state on an output pad.
+ * @note    This function is not meant to be invoked directly by the
+ *          application  code.
+ * @note    The @ref PAL provides a default software implementation of this
+ *          functionality, implement this function if can optimize it by using
+ *          special hardware functionalities or special coding.
+ *
+ * @param[in] port      port identifier
+ * @param[in] pad       pad number within the port
+ * @param[in] bit       logical value, the value must be @p PAL_LOW or
+ *                      @p PAL_HIGH
+ *
+ * @notapi
+ */
+#define pal_lld_writepad(port, pad, bit)    \
+  ((port)->MASKED_ACCESS[1 << (pad)] = (bit))
+
+/**
+ * @brief   Sets a pad logical state to @p PAL_HIGH.
+ * @note    The @ref PAL provides a default software implementation of this
+ *          functionality, implement this function if can optimize it by using
+ *          special hardware functionalities or special coding.
+ *
+ * @param[in] port      port identifier
+ * @param[in] pad       pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_setpad(port, pad)   \
+  ((port)->MASKED_ACCESS[1 << (pad)] = 1 << (pad))
+
+/**
+ * @brief   Clears a pad logical state to @p PAL_LOW.
+ * @note    The @ref PAL provides a default software implementation of this
+ *          functionality, implement this function if can optimize it by using
+ *          special hardware functionalities or special coding.
+ *
+ * @param[in] port      port identifier
+ * @param[in] pad       pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_clearpad(port, pad) \
+  ((port)->MASKED_ACCESS[1 << (pad)] = 0)
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern const PALConfig pal_default_config;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void _pal_lld_init(const PALConfig *config);
+  void _pal_lld_setgroupmode(ioportid_t port,
+                             ioportmask_t mask,
+                             iomode_t mode);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_PAL */
+
+#endif /* HAL_PAL_LLD_H */
+
+/**
+ * @}
+ */