1-wire. STM32F1xx code tested

9 files changed, 155 insertions, 432 deletions

diff --git a/os/hal/include/onewire.h b/os/hal/include/onewire.h
index b2c6462..dc82a67 100644
--- a/os/hal/include/onewire.h
+++ b/os/hal/include/onewire.h
@@ -80,13 +80,6 @@ typedef void (*onewire_pullup_release_t)(void);
 #endif /* ONEWIRE_USE_STRONG_PULLUP */
 
 /**
- * @brief   1-wire read bit callback type.
- *
- * @return  Bit acquired directly from pin (0 or 1)
- */
-typedef uint_fast8_t (*onewire_read_bit_t)(void);
-
-/**
  * @brief   Driver state machine possible states.
  */
 typedef enum {
@@ -134,10 +127,29 @@ typedef struct {
    */
   size_t                    sample_channel;
   /**
-   * @brief Pointer to function performing read of single bit.
-   * @note  It must be callable from any context.
+   * @brief   Port Identifier.
+   * @details This type can be a scalar or some kind of pointer, do not make
+   *          any assumption about it, use the provided macros when populating
+   *          variables of this type.
+   */
+  ioportid_t                port;
+  /**
+   * @brief Digital I/O port pad.
+   */
+  ioportmask_t              pad;
+#if defined(STM32F1XX)
+  /**
+   * @brief   Digital I/O mode for idle bus.
+   * @details This is a kind of workaround against F1x realization of alternate
+   *          function. Alternate function mode will be activated only
+   *          when you starts appropriate peripheral.
+   */
+  iomode_t                  pad_mode_idle;
+#endif
+  /**
+   * @brief   Digital I/O mode for active bus.
    */
-  onewire_read_bit_t        readBitX;
+  iomode_t                  pad_mode_active;
 #if ONEWIRE_USE_STRONG_PULLUP
   /**
    * @brief Pointer to function asserting of strong pull up.
diff --git a/os/hal/src/onewire.c b/os/hal/src/onewire.c
index 724ff2f..c94cbac 100644
--- a/os/hal/src/onewire.c
+++ b/os/hal/src/onewire.c
@@ -18,14 +18,14 @@
 /* Main ideas:                                                               */
 /*===========================================================================
 
-1) switch PWM output pin it open drain mode.
+1) switch PWM output pin to open drain mode.
 2) start 2 channels _simultaneously_. First (master channel) generates
    pulses (read time slots) second (sample channel) generates interrupts
-   from where read pin function calls.
+   from where read pin function will be called.
 
 -      --------------------------------------- master channel generates pulses
- |   /
-  --
+ |   /                            .
+  --.............................  <---------- slave (not)pulls down bus here
 -                ----------------------------- sample channel reads pad state
  |               |
   ----------------
@@ -40,8 +40,8 @@ on every timer overflow event.
 /* General recommendations for strong pull usage                             */
 /*===========================================================================
  * 1) Use separate power rail instead of strong pull up whenever possible.
- *    Driver's strong pull up feature is very interrupt jitter sensible.
- * 2) Use special 1-wire bus master (DS2484 for example) if you are
+ *    Driver's strong pull up feature is very sensible to interrupt jitter.
+ * 2) Use specialized 1-wire bus master (DS2484 for example) if you are
  *    forced to handle bus requiring strong pull up feature.
  */
 
@@ -76,7 +76,7 @@ on every timer overflow event.
 #define ONEWIRE_RESET_TOTAL_WIDTH     960
 
 /**
- * @brief     Forward declarations.
+ * @brief     Local function declarations.
  */
 static void ow_reset_cb(PWMDriver *pwmp, onewireDriver *owp);
 static void pwm_reset_cb(PWMDriver *pwmp);
@@ -101,17 +101,17 @@ onewireDriver OWD1;
 /* Driver local variables and types.                                         */
 /*===========================================================================*/
 /**
- * @brief     Config for fast initialization of all fields
+ * @brief     Config for fast initialization of all config's fields
  */
 static const PWMConfig pwm_default_cfg = {
   1000000,
   ONEWIRE_RESET_TOTAL_WIDTH,
   NULL,
   {
-   {PWM_OUTPUT_ACTIVE_LOW, NULL},
-   {PWM_OUTPUT_ACTIVE_LOW, NULL},
-   {PWM_OUTPUT_ACTIVE_LOW, NULL},
-   {PWM_OUTPUT_ACTIVE_LOW, NULL}
+   {PWM_OUTPUT_DISABLED, NULL},
+   {PWM_OUTPUT_DISABLED, NULL},
+   {PWM_OUTPUT_DISABLED, NULL},
+   {PWM_OUTPUT_DISABLED, NULL}
   },
   0,
   0
@@ -159,6 +159,41 @@ static const uint8_t onewire_crc_table[256] = {
 /* Driver local functions.                                                   */
 /*===========================================================================*/
 /**
+ * @brief     Put bus in idle mode.
+ */
+static void onewire_bus_idle(onewireDriver *owp) {
+#if defined(STM32F1XX)
+  palSetPadMode(owp->config->port, owp->config->pad,
+      owp->config->pad_mode_idle);
+#endif
+  pwmStop(owp->config->pwmd);
+}
+
+/**
+ * @brief     Put bus in active mode.
+ */
+static void onewire_bus_active(onewireDriver *owp) {
+  pwmStart(owp->config->pwmd, &owp->pwmcfg);
+#if defined(STM32F1XX)
+  palSetPadMode(owp->config->port, owp->config->pad,
+      owp->config->pad_mode_active);
+#endif
+}
+
+/**
+ * @brief     Function performing read of single bit.
+ * @note      It must be callable from any context.
+ */
+static uint_fast8_t readBitX(onewireDriver *owp) {
+#if ONEWIRE_SYNTH_SEARCH_TEST
+  (void)owp;
+  return _synth_ow_read_bit();
+#else
+  return palReadPad(owp->config->port, owp->config->pad);
+#endif
+}
+
+/**
  * @brief     PWM adapter
  */
 static void pwm_reset_cb(PWMDriver *pwmp) {
@@ -226,7 +261,7 @@ static void ow_write_bit_I(onewireDriver *owp, uint_fast8_t bit) {
  */
 static void ow_reset_cb(PWMDriver *pwmp, onewireDriver *owp) {
 
-  owp->reg.slave_present = (PAL_LOW == owp->config->readBitX());
+  owp->reg.slave_present = (PAL_LOW == readBitX(owp));
 
   osalSysLockFromISR();
   pwmDisableChannelI(pwmp, owp->config->sample_channel);
@@ -253,7 +288,7 @@ static void ow_read_bit_cb(PWMDriver *pwmp, onewireDriver *owp) {
     return;
   }
   else {
-    *owp->buf |= owp->config->readBitX() << owp->reg.bit;
+    *owp->buf |= readBitX(owp) << owp->reg.bit;
     owp->reg.bit++;
     if (8 == owp->reg.bit) {
       owp->reg.bit = 0;
@@ -414,11 +449,11 @@ static void ow_search_rom_cb(PWMDriver *pwmp, onewireDriver *owp) {
   onewire_search_rom_t *sr = &owp->search_rom;
 
   if (0 == sr->reg.bit_step) {                    /* read direct bit */
-    sr->reg.bit_buf |= owp->config->readBitX();
+    sr->reg.bit_buf |= readBitX(owp);
     sr->reg.bit_step++;
   }
   else if (1 == sr->reg.bit_step) {               /* read complement bit */
-    sr->reg.bit_buf |= owp->config->readBitX() << 1;
+    sr->reg.bit_buf |= readBitX(owp) << 1;
     sr->reg.bit_step++;
     switch(sr->reg.bit_buf){
     case 0b11:
@@ -572,7 +607,6 @@ void onewireObjectInit(onewireDriver *owp) {
 void onewireStart(onewireDriver *owp, const onewireConfig *config) {
 
   osalDbgCheck((NULL != owp) && (NULL != config));
-  osalDbgCheck(NULL != config->readBitX);
   osalDbgAssert(PWM_STOP == config->pwmd->state,
       "PWM will be started by onewire driver internally");
   osalDbgAssert(ONEWIRE_STOP == owp->reg.state, "Invalid state");
@@ -582,7 +616,11 @@ void onewireStart(onewireDriver *owp, const onewireConfig *config) {
 #endif
 
   owp->config = config;
-  pwmStart(owp->config->pwmd, &pwm_default_cfg);
+#if !defined(STM32F1XX)
+  palSetPadMode(owp->config->port, owp->config->pad,
+      owp->config->pad_mode_active);
+#endif
+  onewire_bus_idle(owp);
   owp->reg.state = ONEWIRE_READY;
 }
 
@@ -598,6 +636,7 @@ void onewireStop(onewireDriver *owp) {
 #if ONEWIRE_USE_STRONG_PULLUP
   owp->config->pullup_release();
 #endif
+  onewire_bus_idle(owp);
   pwmStop(owp->config->pwmd);
   owp->config = NULL;
   owp->reg.state = ONEWIRE_STOP;
@@ -613,41 +652,40 @@ void onewireStop(onewireDriver *owp) {
  */
 bool onewireReset(onewireDriver *owp) {
   PWMDriver *pwmd;
+  size_t mch, sch;
 
   osalDbgCheck(NULL != owp);
   osalDbgAssert(owp->reg.state == ONEWIRE_READY, "Invalid state");
 
   /* short circuit on bus or any other device transmit data */
-  if (PAL_LOW == owp->config->readBitX())
+  if (PAL_LOW == readBitX(owp))
     return false;
 
-  palSetPad(GPIOC, GPIOC_LED);
-
   pwmd = owp->config->pwmd;
+  mch = owp->config->master_channel;
+  sch = owp->config->sample_channel;
 
   owp->pwmcfg.period = ONEWIRE_RESET_LOW_WIDTH + ONEWIRE_RESET_SAMPLE_WIDTH;
   owp->pwmcfg.callback = NULL;
-  owp->pwmcfg.channels[owp->config->master_channel].callback = NULL;
-  owp->pwmcfg.channels[owp->config->master_channel].mode = PWM_OUTPUT_ACTIVE_LOW;
-  owp->pwmcfg.channels[owp->config->sample_channel].callback = pwm_reset_cb;
-  owp->pwmcfg.channels[owp->config->sample_channel].mode = PWM_OUTPUT_ACTIVE_LOW;
+  owp->pwmcfg.channels[mch].callback = NULL;
+  owp->pwmcfg.channels[mch].mode = PWM_OUTPUT_ACTIVE_LOW;
+  owp->pwmcfg.channels[sch].callback = pwm_reset_cb;
+  owp->pwmcfg.channels[sch].mode = PWM_OUTPUT_ACTIVE_LOW;
 
-  pwmStart(pwmd, &owp->pwmcfg);
-  palSetPadMode(GPIOB, 8, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
-  pwmEnableChannel(pwmd, owp->config->master_channel, ONEWIRE_RESET_LOW_WIDTH);
-  pwmEnableChannel(pwmd, owp->config->sample_channel, ONEWIRE_RESET_SAMPLE_WIDTH);
-  pwmEnableChannelNotification(pwmd, owp->config->sample_channel);
+  onewire_bus_active(owp);
+  pwmEnableChannel(pwmd, mch, ONEWIRE_RESET_LOW_WIDTH);
+  pwmEnableChannel(pwmd, sch, ONEWIRE_RESET_SAMPLE_WIDTH);
+  pwmEnableChannelNotification(pwmd, sch);
 
   osalSysLock();
   osalThreadSuspendS(&owp->thread);
   osalSysUnlock();
 
-  palSetPadMode(GPIOB, 8, PAL_MODE_INPUT);
-  pwmStop(pwmd);
+  onewire_bus_idle(owp);
 
   /* wait until slave release bus to discriminate short circuit condition */
   osalThreadSleepMicroseconds(500);
-  return (PAL_HIGH == owp->config->readBitX()) && (true == owp->reg.slave_present);
+  return (PAL_HIGH == readBitX(owp)) && (true == owp->reg.slave_present);
 }
 
 /**
@@ -659,6 +697,7 @@ bool onewireReset(onewireDriver *owp) {
  */
 void onewireRead(onewireDriver *owp, uint8_t *rxbuf, size_t rxbytes) {
   PWMDriver *pwmd;
+  size_t mch, sch;
 
   osalDbgCheck((NULL != owp) && (NULL != rxbuf));
   osalDbgCheck((rxbytes > 0) && (rxbytes < 65536));
@@ -669,6 +708,8 @@ void onewireRead(onewireDriver *owp, uint8_t *rxbuf, size_t rxbytes) {
   memset(rxbuf, 0, rxbytes);
 
   pwmd = owp->config->pwmd;
+  mch = owp->config->master_channel;
+  sch = owp->config->sample_channel;
 
   owp->reg.bit = 0;
   owp->reg.final_timeslot = false;
@@ -677,23 +718,21 @@ void onewireRead(onewireDriver *owp, uint8_t *rxbuf, size_t rxbytes) {
 
   owp->pwmcfg.period = ONEWIRE_ZERO_WIDTH + ONEWIRE_RECOVERY_WIDTH;
   owp->pwmcfg.callback = NULL;
-  owp->pwmcfg.channels[owp->config->master_channel].callback = NULL;
-  owp->pwmcfg.channels[owp->config->master_channel].mode = PWM_OUTPUT_ACTIVE_LOW;
-  owp->pwmcfg.channels[owp->config->sample_channel].callback = pwm_read_bit_cb;
-  owp->pwmcfg.channels[owp->config->sample_channel].mode = PWM_OUTPUT_ACTIVE_LOW;
+  owp->pwmcfg.channels[mch].callback = NULL;
+  owp->pwmcfg.channels[mch].mode = PWM_OUTPUT_ACTIVE_LOW;
+  owp->pwmcfg.channels[sch].callback = pwm_read_bit_cb;
+  owp->pwmcfg.channels[sch].mode = PWM_OUTPUT_ACTIVE_LOW;
 
-  pwmStart(pwmd, &owp->pwmcfg);
-  palSetPadMode(GPIOB, 8, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
-  pwmEnableChannel(pwmd, owp->config->master_channel, ONEWIRE_ONE_WIDTH);
-  pwmEnableChannel(pwmd, owp->config->sample_channel, ONEWIRE_SAMPLE_WIDTH);
-  pwmEnableChannelNotification(pwmd, owp->config->sample_channel);
+  onewire_bus_active(owp);
+  pwmEnableChannel(pwmd, mch, ONEWIRE_ONE_WIDTH);
+  pwmEnableChannel(pwmd, sch, ONEWIRE_SAMPLE_WIDTH);
+  pwmEnableChannelNotification(pwmd, sch);
 
   osalSysLock();
   osalThreadSuspendS(&owp->thread);
   osalSysUnlock();
 
-  palSetPadMode(GPIOB, 8, PAL_MODE_INPUT);
-  pwmStop(pwmd);
+  onewire_bus_idle(owp);
 }
 
 /**
@@ -708,6 +747,7 @@ void onewireRead(onewireDriver *owp, uint8_t *rxbuf, size_t rxbytes) {
 void onewireWrite(onewireDriver *owp, uint8_t *txbuf,
                   size_t txbytes, systime_t pullup_time) {
   PWMDriver *pwmd;
+  size_t mch, sch;
 
   osalDbgCheck((NULL != owp) && (NULL != txbuf));
   osalDbgCheck((txbytes > 0) && (txbytes < 65536));
@@ -718,6 +758,8 @@ void onewireWrite(onewireDriver *owp, uint8_t *txbuf,
 #endif
 
   pwmd = owp->config->pwmd;
+  mch = owp->config->master_channel;
+  sch = owp->config->sample_channel;
 
   owp->buf = txbuf;
   owp->reg.bit = 0;
@@ -726,10 +768,10 @@ void onewireWrite(onewireDriver *owp, uint8_t *txbuf,
 
   owp->pwmcfg.period = ONEWIRE_ZERO_WIDTH + ONEWIRE_RECOVERY_WIDTH;
   owp->pwmcfg.callback = pwm_write_bit_cb;
-  owp->pwmcfg.channels[owp->config->master_channel].callback = NULL;
-  owp->pwmcfg.channels[owp->config->master_channel].mode = PWM_OUTPUT_ACTIVE_LOW;
-  owp->pwmcfg.channels[owp->config->sample_channel].callback = NULL;
-  owp->pwmcfg.channels[owp->config->sample_channel].mode = PWM_OUTPUT_DISABLED;
+  owp->pwmcfg.channels[mch].callback = NULL;
+  owp->pwmcfg.channels[mch].mode = PWM_OUTPUT_ACTIVE_LOW;
+  owp->pwmcfg.channels[sch].callback = NULL;
+  owp->pwmcfg.channels[sch].mode = PWM_OUTPUT_DISABLED;
 
 #if ONEWIRE_USE_STRONG_PULLUP
   if (pullup_time > 0) {
@@ -738,8 +780,7 @@ void onewireWrite(onewireDriver *owp, uint8_t *txbuf,
   }
 #endif
 
-  pwmStart(pwmd, &owp->pwmcfg);
-  palSetPadMode(GPIOB, 8, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
+  onewire_bus_active(owp);
   pwmEnablePeriodicNotification(pwmd);
 
   osalSysLock();
@@ -747,8 +788,7 @@ void onewireWrite(onewireDriver *owp, uint8_t *txbuf,
   osalSysUnlock();
 
   pwmDisablePeriodicNotification(pwmd);
-  palSetPadMode(GPIOB, 8, PAL_MODE_INPUT);
-  pwmStop(pwmd);
+  onewire_bus_idle(owp);
 
 #if ONEWIRE_USE_STRONG_PULLUP
   if (pullup_time > 0) {
@@ -776,6 +816,7 @@ size_t onewireSearchRom(onewireDriver *owp, uint8_t *result,
                         size_t max_rom_cnt) {
   PWMDriver *pwmd;
   uint8_t cmd;
+  size_t mch, sch;
 
   osalDbgCheck(NULL != owp);
   osalDbgAssert(ONEWIRE_READY == owp->reg.state, "Invalid state");
@@ -783,6 +824,8 @@ size_t onewireSearchRom(onewireDriver *owp, uint8_t *result,
 
   pwmd = owp->config->pwmd;
   cmd = ONEWIRE_CMD_SEARCH_ROM;
+  mch = owp->config->master_channel;
+  sch = owp->config->sample_channel;
 
   search_clean_start(&owp->search_rom);
 
@@ -807,22 +850,21 @@ size_t onewireSearchRom(onewireDriver *owp, uint8_t *result,
     /* Reconfiguration always needed because of previous call onewireWrite.*/
     owp->pwmcfg.period = ONEWIRE_ZERO_WIDTH + ONEWIRE_RECOVERY_WIDTH;
     owp->pwmcfg.callback = NULL;
-    owp->pwmcfg.channels[owp->config->master_channel].callback = NULL;
-    owp->pwmcfg.channels[owp->config->master_channel].mode = PWM_OUTPUT_ACTIVE_LOW;
-    owp->pwmcfg.channels[owp->config->sample_channel].callback = pwm_search_rom_cb;
-    owp->pwmcfg.channels[owp->config->sample_channel].mode = PWM_OUTPUT_ACTIVE_LOW;
-    pwmStart(pwmd, &owp->pwmcfg);
-    palSetPadMode(GPIOB, 8, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
-    pwmEnableChannel(pwmd, owp->config->master_channel, ONEWIRE_ONE_WIDTH);
-    pwmEnableChannel(pwmd, owp->config->sample_channel, ONEWIRE_SAMPLE_WIDTH);
-    pwmEnableChannelNotification(pwmd, owp->config->sample_channel);
+    owp->pwmcfg.channels[mch].callback = NULL;
+    owp->pwmcfg.channels[mch].mode = PWM_OUTPUT_ACTIVE_LOW;
+    owp->pwmcfg.channels[sch].callback = pwm_search_rom_cb;
+    owp->pwmcfg.channels[sch].mode = PWM_OUTPUT_ACTIVE_LOW;
+
+    onewire_bus_active(owp);
+    pwmEnableChannel(pwmd, mch, ONEWIRE_ONE_WIDTH);
+    pwmEnableChannel(pwmd, sch, ONEWIRE_SAMPLE_WIDTH);
+    pwmEnableChannelNotification(pwmd, sch);
 
     osalSysLock();
     osalThreadSuspendS(&owp->thread);
     osalSysUnlock();
 
-    palSetPadMode(GPIOB, 8, PAL_MODE_INPUT);
-    pwmStop(pwmd);
+    onewire_bus_idle(owp);
 
     if (ONEWIRE_SEARCH_ROM_ERROR != owp->search_rom.reg.result) {
       /* check CRC and return 0 (error status) if mismatch */
diff --git a/testhal/STM32/STM32F1xx/onewire/Makefile b/testhal/STM32/STM32F1xx/onewire/Makefile
index dbaaca5..b079c47 100644
--- a/testhal/STM32/STM32F1xx/onewire/Makefile
+++ b/testhal/STM32/STM32F1xx/onewire/Makefile
@@ -5,7 +5,7 @@
 

 # Compiler options here.

 ifeq ($(USE_OPT),)

-  USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16

+  USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16

 endif

 

 # C specific options here (added to USE_OPT).

@@ -87,7 +87,6 @@ include $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/platform.mk
 include $(CHIBIOS)/os/hal/osal/rt/osal.mk

 include $(CHIBIOS)/os/rt/rt.mk

 include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f1xx.mk

-include $(CHIBIOS)/test/rt/test.mk

 

 # Define linker script file here

 LDSCRIPT= $(PORTLD)/STM32F103xB.ld

diff --git a/testhal/STM32/STM32F1xx/onewire/main.c b/testhal/STM32/STM32F1xx/onewire/main.c
index 5f9722d..793bffe 100644
--- a/testhal/STM32/STM32F1xx/onewire/main.c
+++ b/testhal/STM32/STM32F1xx/onewire/main.c
@@ -35,12 +35,6 @@ int main(void) {
   chSysInit();

 

   /*

-   * Connect PB8 to TIM4 channel 2, set open drain mode

-   * and enable internal pullup for slave absence detection.

-   */

-  palSetPadMode(GPIOB, 8, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);

-

-  /*

    * Executes infinite onewire test code.

    */

   onewireTest();

diff --git a/testhal/STM32/STM32F1xx/onewire/mcuconf_bak.h b/testhal/STM32/STM32F1xx/onewire/mcuconf_bak.h
deleted file mode 100644
index b5d0a86..0000000
--- a/testhal/STM32/STM32F1xx/onewire/mcuconf_bak.h
+++ /dev/null
@@ -1,310 +0,0 @@
-/*

-    ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio

-

-    Licensed under the Apache License, Version 2.0 (the "License");

-    you may not use this file except in compliance with the License.

-    You may obtain a copy of the License at

-

-        http://www.apache.org/licenses/LICENSE-2.0

-

-    Unless required by applicable law or agreed to in writing, software

-    distributed under the License is distributed on an "AS IS" BASIS,

-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

-    See the License for the specific language governing permissions and

-    limitations under the License.

-*/

-

-/*

- * STM32F4xx drivers configuration.

- * The following settings override the default settings present in

- * the various device driver implementation headers.

- * Note that the settings for each driver only have effect if the whole

- * driver is enabled in halconf.h.

- *

- * IRQ priorities:

- * 15...0       Lowest...Highest.

- *

- * DMA priorities:

- * 0...3        Lowest...Highest.

- */

-

-#define STM32F4xx_MCUCONF

-

-/*

- * HAL driver system settings.

- */

-#define STM32_NO_INIT                       FALSE

-#define STM32_HSI_ENABLED                   TRUE

-#define STM32_LSI_ENABLED                   TRUE

-#define STM32_HSE_ENABLED                   TRUE

-#define STM32_LSE_ENABLED                   FALSE

-#define STM32_CLOCK48_REQUIRED              TRUE

-#define STM32_SW                            STM32_SW_PLL

-#define STM32_PLLSRC                        STM32_PLLSRC_HSE

-#define STM32_PLLM_VALUE                    8

-#define STM32_PLLN_VALUE                    336

-#define STM32_PLLP_VALUE                    2

-#define STM32_PLLQ_VALUE                    7

-#define STM32_HPRE                          STM32_HPRE_DIV1

-#define STM32_PPRE1                         STM32_PPRE1_DIV4

-#define STM32_PPRE2                         STM32_PPRE2_DIV2

-#define STM32_RTCSEL                        STM32_RTCSEL_LSI

-#define STM32_RTCPRE_VALUE                  8

-#define STM32_MCO1SEL                       STM32_MCO1SEL_HSI

-#define STM32_MCO1PRE                       STM32_MCO1PRE_DIV1

-#define STM32_MCO2SEL                       STM32_MCO2SEL_SYSCLK

-#define STM32_MCO2PRE                       STM32_MCO2PRE_DIV5

-#define STM32_I2SSRC                        STM32_I2SSRC_CKIN

-#define STM32_PLLI2SN_VALUE                 192

-#define STM32_PLLI2SR_VALUE                 5

-#define STM32_PVD_ENABLE                    FALSE

-#define STM32_PLS                           STM32_PLS_LEV0

-#define STM32_BKPRAM_ENABLE                 FALSE

-

-/*

- * ADC driver system settings.

- */

-#define STM32_ADC_ADCPRE                    ADC_CCR_ADCPRE_DIV4

-#define STM32_ADC_USE_ADC1                  FALSE

-#define STM32_ADC_USE_ADC2                  FALSE

-#define STM32_ADC_USE_ADC3                  FALSE

-#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(2, 4)

-#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2)

-#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)

-#define STM32_ADC_ADC1_DMA_PRIORITY         2

-#define STM32_ADC_ADC2_DMA_PRIORITY         2

-#define STM32_ADC_ADC3_DMA_PRIORITY         2

-#define STM32_ADC_IRQ_PRIORITY              6

-#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     6

-#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     6

-#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     6

-

-/*

- * CAN driver system settings.

- */

-#define STM32_CAN_USE_CAN1                  FALSE

-#define STM32_CAN_USE_CAN2                  FALSE

-#define STM32_CAN_CAN1_IRQ_PRIORITY         11

-#define STM32_CAN_CAN2_IRQ_PRIORITY         11

-

-/*

- * EXT driver system settings.

- */

-#define STM32_EXT_EXTI0_IRQ_PRIORITY        6

-#define STM32_EXT_EXTI1_IRQ_PRIORITY        6

-#define STM32_EXT_EXTI2_IRQ_PRIORITY        6

-#define STM32_EXT_EXTI3_IRQ_PRIORITY        6

-#define STM32_EXT_EXTI4_IRQ_PRIORITY        6

-#define STM32_EXT_EXTI5_9_IRQ_PRIORITY      6

-#define STM32_EXT_EXTI10_15_IRQ_PRIORITY    6

-#define STM32_EXT_EXTI16_IRQ_PRIORITY       6

-#define STM32_EXT_EXTI17_IRQ_PRIORITY       15

-#define STM32_EXT_EXTI18_IRQ_PRIORITY       6

-#define STM32_EXT_EXTI19_IRQ_PRIORITY       6

-#define STM32_EXT_EXTI20_IRQ_PRIORITY       6

-#define STM32_EXT_EXTI21_IRQ_PRIORITY       15

-#define STM32_EXT_EXTI22_IRQ_PRIORITY       15

-

-/*

- * GPT driver system settings.

- */

-#define STM32_GPT_USE_TIM1                  FALSE

-#define STM32_GPT_USE_TIM2                  FALSE

-#define STM32_GPT_USE_TIM3                  FALSE

-#define STM32_GPT_USE_TIM4                  FALSE

-#define STM32_GPT_USE_TIM5                  FALSE

-#define STM32_GPT_USE_TIM6                  FALSE

-#define STM32_GPT_USE_TIM7                  FALSE

-#define STM32_GPT_USE_TIM8                  FALSE

-#define STM32_GPT_USE_TIM9                  FALSE

-#define STM32_GPT_USE_TIM11                 FALSE

-#define STM32_GPT_USE_TIM12                 FALSE

-#define STM32_GPT_USE_TIM14                 FALSE

-#define STM32_GPT_TIM1_IRQ_PRIORITY         7

-#define STM32_GPT_TIM2_IRQ_PRIORITY         7

-#define STM32_GPT_TIM3_IRQ_PRIORITY         7

-#define STM32_GPT_TIM4_IRQ_PRIORITY         7

-#define STM32_GPT_TIM5_IRQ_PRIORITY         7

-#define STM32_GPT_TIM6_IRQ_PRIORITY         7

-#define STM32_GPT_TIM7_IRQ_PRIORITY         7

-#define STM32_GPT_TIM8_IRQ_PRIORITY         7

-#define STM32_GPT_TIM9_IRQ_PRIORITY         7

-#define STM32_GPT_TIM11_IRQ_PRIORITY        7

-#define STM32_GPT_TIM12_IRQ_PRIORITY        7

-#define STM32_GPT_TIM14_IRQ_PRIORITY        7

-

-/*

- * I2C driver system settings.

- */

-#define STM32_I2C_USE_I2C1                  FALSE

-#define STM32_I2C_USE_I2C2                  FALSE

-#define STM32_I2C_USE_I2C3                  FALSE

-#define STM32_I2C_BUSY_TIMEOUT              50

-#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)

-#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)

-#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)

-#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)

-#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)

-#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)

-#define STM32_I2C_I2C1_IRQ_PRIORITY         5

-#define STM32_I2C_I2C2_IRQ_PRIORITY         5

-#define STM32_I2C_I2C3_IRQ_PRIORITY         5

-#define STM32_I2C_I2C1_DMA_PRIORITY         3

-#define STM32_I2C_I2C2_DMA_PRIORITY         3

-#define STM32_I2C_I2C3_DMA_PRIORITY         3

-#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")

-

-/*

- * ICU driver system settings.

- */

-#define STM32_ICU_USE_TIM1                  FALSE

-#define STM32_ICU_USE_TIM2                  FALSE

-#define STM32_ICU_USE_TIM3                  FALSE

-#define STM32_ICU_USE_TIM4                  FALSE

-#define STM32_ICU_USE_TIM5                  FALSE

-#define STM32_ICU_USE_TIM8                  FALSE

-#define STM32_ICU_USE_TIM9                  FALSE

-#define STM32_ICU_TIM1_IRQ_PRIORITY         7

-#define STM32_ICU_TIM2_IRQ_PRIORITY         7

-#define STM32_ICU_TIM3_IRQ_PRIORITY         7

-#define STM32_ICU_TIM4_IRQ_PRIORITY         7

-#define STM32_ICU_TIM5_IRQ_PRIORITY         7

-#define STM32_ICU_TIM8_IRQ_PRIORITY         7

-#define STM32_ICU_TIM9_IRQ_PRIORITY         7

-

-/*

- * MAC driver system settings.

- */

-#define STM32_MAC_TRANSMIT_BUFFERS          2

-#define STM32_MAC_RECEIVE_BUFFERS           4

-#define STM32_MAC_BUFFERS_SIZE              1522

-#define STM32_MAC_PHY_TIMEOUT               100

-#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE

-#define STM32_MAC_ETH1_IRQ_PRIORITY         13

-#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0

-

-/*

- * PWM driver system settings.

- */

-#define STM32_PWM_USE_ADVANCED              FALSE

-#define STM32_PWM_USE_TIM1                  FALSE

-#define STM32_PWM_USE_TIM2                  FALSE

-#define STM32_PWM_USE_TIM3                  FALSE

-#define STM32_PWM_USE_TIM4                  TRUE

-#define STM32_PWM_USE_TIM5                  FALSE

-#define STM32_PWM_USE_TIM8                  FALSE

-#define STM32_PWM_USE_TIM9                  FALSE

-#define STM32_PWM_TIM1_IRQ_PRIORITY         7

-#define STM32_PWM_TIM2_IRQ_PRIORITY         7

-#define STM32_PWM_TIM3_IRQ_PRIORITY         7

-#define STM32_PWM_TIM4_IRQ_PRIORITY         7

-#define STM32_PWM_TIM5_IRQ_PRIORITY         7

-#define STM32_PWM_TIM8_IRQ_PRIORITY         7

-#define STM32_PWM_TIM9_IRQ_PRIORITY         7

-

-/*

- * SDC driver system settings.

- */

-#define STM32_SDC_SDIO_DMA_PRIORITY         3

-#define STM32_SDC_SDIO_IRQ_PRIORITY         9

-#define STM32_SDC_WRITE_TIMEOUT_MS          250

-#define STM32_SDC_READ_TIMEOUT_MS           25

-#define STM32_SDC_CLOCK_ACTIVATION_DELAY    10

-#define STM32_SDC_SDIO_UNALIGNED_SUPPORT    TRUE

-#define STM32_SDC_SDIO_DMA_STREAM           STM32_DMA_STREAM_ID(2, 3)

-

-/*

- * SERIAL driver system settings.

- */

-#define STM32_SERIAL_USE_USART1             FALSE

-#define STM32_SERIAL_USE_USART2             TRUE

-#define STM32_SERIAL_USE_USART3             FALSE

-#define STM32_SERIAL_USE_UART4              FALSE

-#define STM32_SERIAL_USE_UART5              FALSE

-#define STM32_SERIAL_USE_USART6             FALSE

-#define STM32_SERIAL_USART1_PRIORITY        12

-#define STM32_SERIAL_USART2_PRIORITY        12

-#define STM32_SERIAL_USART3_PRIORITY        12

-#define STM32_SERIAL_UART4_PRIORITY         12

-#define STM32_SERIAL_UART5_PRIORITY         12

-#define STM32_SERIAL_USART6_PRIORITY        12

-

-/*

- * SPI driver system settings.

- */

-#define STM32_SPI_USE_SPI1                  FALSE

-#define STM32_SPI_USE_SPI2                  FALSE

-#define STM32_SPI_USE_SPI3                  FALSE

-#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 0)

-#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 3)

-#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)

-#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)

-#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)

-#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)

-#define STM32_SPI_SPI1_DMA_PRIORITY         1

-#define STM32_SPI_SPI2_DMA_PRIORITY         1

-#define STM32_SPI_SPI3_DMA_PRIORITY         1

-#define STM32_SPI_SPI1_IRQ_PRIORITY         10

-#define STM32_SPI_SPI2_IRQ_PRIORITY         10

-#define STM32_SPI_SPI3_IRQ_PRIORITY         10

-#define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")

-

-/*

- * ST driver system settings.

- */

-#define STM32_ST_IRQ_PRIORITY               8

-#define STM32_ST_USE_TIMER                  2

-

-/*

- * UART driver system settings.

- */

-#define STM32_UART_USE_USART1               FALSE

-#define STM32_UART_USE_USART2               FALSE

-#define STM32_UART_USE_USART3               FALSE

-#define STM32_UART_USE_UART4                FALSE

-#define STM32_UART_USE_UART5                FALSE

-#define STM32_UART_USE_USART6               FALSE

-#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 5)

-#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)

-#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)

-#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)

-#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 1)

-#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)

-#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 2)

-#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 4)

-#define STM32_UART_UART5_RX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 0)

-#define STM32_UART_UART5_TX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 7)

-#define STM32_UART_USART6_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 2)

-#define STM32_UART_USART6_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)

-#define STM32_UART_USART1_IRQ_PRIORITY      12

-#define STM32_UART_USART2_IRQ_PRIORITY      12

-#define STM32_UART_USART3_IRQ_PRIORITY      12

-#define STM32_UART_UART4_IRQ_PRIORITY       12

-#define STM32_UART_UART5_IRQ_PRIORITY       12

-#define STM32_UART_USART6_IRQ_PRIORITY      12

-#define STM32_UART_USART1_DMA_PRIORITY      0

-#define STM32_UART_USART2_DMA_PRIORITY      0

-#define STM32_UART_USART3_DMA_PRIORITY      0

-#define STM32_UART_UART4_DMA_PRIORITY       0

-#define STM32_UART_UART5_DMA_PRIORITY       0

-#define STM32_UART_USART6_DMA_PRIORITY      0

-#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")

-

-/*

- * USB driver system settings.

- */

-#define STM32_USB_USE_OTG1                  FALSE

-#define STM32_USB_USE_OTG2                  FALSE

-#define STM32_USB_OTG1_IRQ_PRIORITY         14

-#define STM32_USB_OTG2_IRQ_PRIORITY         14

-#define STM32_USB_OTG1_RX_FIFO_SIZE         512

-#define STM32_USB_OTG2_RX_FIFO_SIZE         1024

-#define STM32_USB_OTG_THREAD_PRIO           LOWPRIO

-#define STM32_USB_OTG_THREAD_STACK_SIZE     128

-#define STM32_USB_OTGFIFO_FILL_BASEPRI      0

-

-/*

- * header for community drivers.

- */

-#include "mcuconf_community.h"

-

diff --git a/testhal/STM32/STM32F1xx/onewire/onewire_test.c b/testhal/STM32/STM32F1xx/onewire/onewire_test.c
index 3ce31dc..7d0de69 100644
--- a/testhal/STM32/STM32F1xx/onewire/onewire_test.c
+++ b/testhal/STM32/STM32F1xx/onewire/onewire_test.c
@@ -32,19 +32,23 @@
 
 #if defined(BOARD_ST_STM32F4_DISCOVERY)
 #define GPIOB_ONEWIRE                 GPIOB_PIN8
+#define ONEWIRE_PAD_MODE_ACTIVE       (PAL_MODE_ALTERNATE(2) | PAL_STM32_OTYPE_OPENDRAIN | PAL_STM32_PUDR_PULLUP)
 #define search_led_off()              (palClearPad(GPIOD, GPIOD_LED4))
 #define search_led_on()               (palSetPad(GPIOD, GPIOD_LED4))
 #define ONEWIRE_MASTER_CHANNEL        2
 #define ONEWIRE_SAMPLE_CHANNEL        3
 #elif defined(BOARD_OLIMEX_STM32_103STK)
 #define GPIOB_ONEWIRE                 8
-#define search_led_off()              (palClearPad(GPIOC, GPIOC_LED))
-#define search_led_on()               (palSetPad(GPIOC, GPIOC_LED))
+#define ONEWIRE_PAD_MODE_IDLE         PAL_MODE_INPUT
+#define ONEWIRE_PAD_MODE_ACTIVE       PAL_MODE_STM32_ALTERNATE_OPENDRAIN
+#define search_led_on()               (palClearPad(GPIOC, GPIOC_LED))
+#define search_led_off()              (palSetPad(GPIOC, GPIOC_LED))
 #define ONEWIRE_MASTER_CHANNEL        2
 #define ONEWIRE_SAMPLE_CHANNEL        3
 #else
 #define GPIOB_ONEWIRE                 GPIOB_TACHOMETER
 #include "pads.h"
+#define ONEWIRE_PAD_MODE_ACTIVE       (PAL_MODE_ALTERNATE(2) | PAL_STM32_OTYPE_OPENDRAIN | PAL_STM32_PUDR_PULLUP)
 #define search_led_on                 red_led_on
 #define search_led_off                red_led_off
 #define ONEWIRE_MASTER_CHANNEL        2
@@ -65,7 +69,6 @@
 /*
  * Forward declarations
  */
-static uint_fast8_t onewire_read_bit_X(void);
 #if ONEWIRE_USE_STRONG_PULLUP
 static void strong_pullup_assert(void);
 static void strong_pullup_release(void);
@@ -88,7 +91,12 @@ static const onewireConfig ow_cfg = {
   &PWMD4,
   ONEWIRE_MASTER_CHANNEL,
   ONEWIRE_SAMPLE_CHANNEL,
-  onewire_read_bit_X,
+  GPIOB,
+  GPIOB_ONEWIRE,
+#if defined(STM32F1XX)
+  ONEWIRE_PAD_MODE_IDLE,
+#endif
+  ONEWIRE_PAD_MODE_ACTIVE,
 #if ONEWIRE_USE_STRONG_PULLUP
   strong_pullup_assert,
   strong_pullup_release
@@ -121,17 +129,6 @@ static void strong_pullup_release(void) {
 }
 #endif /* ONEWIRE_USE_STRONG_PULLUP */
 
-/**
- *
- */
-static uint_fast8_t onewire_read_bit_X(void) {
-#if ONEWIRE_SYNTH_SEARCH_TEST
-  return _synth_ow_read_bit();
-#else
-  return palReadPad(GPIOB, GPIOB_ONEWIRE);
-#endif
-}
-
 /*
  ******************************************************************************
  * EXPORTED FUNCTIONS
diff --git a/testhal/STM32/STM32F4xx/onewire/Makefile b/testhal/STM32/STM32F4xx/onewire/Makefile
index ad6e2a6..e82a879 100644
--- a/testhal/STM32/STM32F4xx/onewire/Makefile
+++ b/testhal/STM32/STM32F4xx/onewire/Makefile
@@ -65,7 +65,7 @@ endif
 

 # Enables the use of FPU on Cortex-M4 (no, softfp, hard).

 ifeq ($(USE_FPU),)

-  USE_FPU = hard

+  USE_FPU = softfp

 endif

 

 #

@@ -87,7 +87,6 @@ include $(CHIBIOS)/community/os/hal/ports/STM32/STM32F4xx/platform.mk
 include $(CHIBIOS)/os/hal/osal/rt/osal.mk

 include $(CHIBIOS)/os/rt/rt.mk

 include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f4xx.mk

-include $(CHIBIOS)/test/rt/test.mk

 

 # Define linker script file here

 LDSCRIPT= $(PORTLD)/STM32F407xG.ld

diff --git a/testhal/STM32/STM32F4xx/onewire/main.c b/testhal/STM32/STM32F4xx/onewire/main.c
index 5fdbfd9..793bffe 100644
--- a/testhal/STM32/STM32F4xx/onewire/main.c
+++ b/testhal/STM32/STM32F4xx/onewire/main.c
@@ -35,13 +35,6 @@ int main(void) {
   chSysInit();

 

   /*

-   * Connect PB8 to TIM4 channel 2, set open drain mode

-   * and enable internal pullup for slave absence detection.

-   */

-  palSetPadMode(GPIOB, GPIOB_PIN8,

-      PAL_MODE_ALTERNATE(2) | PAL_STM32_OTYPE_OPENDRAIN | PAL_STM32_PUDR_PULLUP);

-

-  /*

    * Executes infinite onewire test code.

    */

   onewireTest();

diff --git a/testhal/STM32/STM32F4xx/onewire/onewire_test.c b/testhal/STM32/STM32F4xx/onewire/onewire_test.c
index 139732d..7d0de69 100644
--- a/testhal/STM32/STM32F4xx/onewire/onewire_test.c
+++ b/testhal/STM32/STM32F4xx/onewire/onewire_test.c
@@ -32,19 +32,23 @@
 
 #if defined(BOARD_ST_STM32F4_DISCOVERY)
 #define GPIOB_ONEWIRE                 GPIOB_PIN8
+#define ONEWIRE_PAD_MODE_ACTIVE       (PAL_MODE_ALTERNATE(2) | PAL_STM32_OTYPE_OPENDRAIN | PAL_STM32_PUDR_PULLUP)
 #define search_led_off()              (palClearPad(GPIOD, GPIOD_LED4))
 #define search_led_on()               (palSetPad(GPIOD, GPIOD_LED4))
 #define ONEWIRE_MASTER_CHANNEL        2
 #define ONEWIRE_SAMPLE_CHANNEL        3
 #elif defined(BOARD_OLIMEX_STM32_103STK)
 #define GPIOB_ONEWIRE                 8
-#define search_led_off()              (palClearPad(GPIOC, GPIOC_LED))
-#define search_led_on()               (palSetPad(GPIOC, GPIOC_LED))
-#define ONEWIRE_MASTER_CHANNEL        3
-#define ONEWIRE_SAMPLE_CHANNEL        2
+#define ONEWIRE_PAD_MODE_IDLE         PAL_MODE_INPUT
+#define ONEWIRE_PAD_MODE_ACTIVE       PAL_MODE_STM32_ALTERNATE_OPENDRAIN
+#define search_led_on()               (palClearPad(GPIOC, GPIOC_LED))
+#define search_led_off()              (palSetPad(GPIOC, GPIOC_LED))
+#define ONEWIRE_MASTER_CHANNEL        2
+#define ONEWIRE_SAMPLE_CHANNEL        3
 #else
 #define GPIOB_ONEWIRE                 GPIOB_TACHOMETER
 #include "pads.h"
+#define ONEWIRE_PAD_MODE_ACTIVE       (PAL_MODE_ALTERNATE(2) | PAL_STM32_OTYPE_OPENDRAIN | PAL_STM32_PUDR_PULLUP)
 #define search_led_on                 red_led_on
 #define search_led_off                red_led_off
 #define ONEWIRE_MASTER_CHANNEL        2
@@ -65,7 +69,6 @@
 /*
  * Forward declarations
  */
-static uint_fast8_t onewire_read_bit_X(void);
 #if ONEWIRE_USE_STRONG_PULLUP
 static void strong_pullup_assert(void);
 static void strong_pullup_release(void);
@@ -88,7 +91,12 @@ static const onewireConfig ow_cfg = {
   &PWMD4,
   ONEWIRE_MASTER_CHANNEL,
   ONEWIRE_SAMPLE_CHANNEL,
-  onewire_read_bit_X,
+  GPIOB,
+  GPIOB_ONEWIRE,
+#if defined(STM32F1XX)
+  ONEWIRE_PAD_MODE_IDLE,
+#endif
+  ONEWIRE_PAD_MODE_ACTIVE,
 #if ONEWIRE_USE_STRONG_PULLUP
   strong_pullup_assert,
   strong_pullup_release
@@ -121,17 +129,6 @@ static void strong_pullup_release(void) {
 }
 #endif /* ONEWIRE_USE_STRONG_PULLUP */
 
-/**
- *
- */
-static uint_fast8_t onewire_read_bit_X(void) {
-#if ONEWIRE_SYNTH_SEARCH_TEST
-  return _synth_ow_read_bit();
-#else
-  return palReadPad(GPIOB, GPIOB_ONEWIRE);
-#endif
-}
-
 /*
  ******************************************************************************
  * EXPORTED FUNCTIONS