firmware: Added configuration folders

5 files changed, 390 insertions, 155 deletions

diff --git a/firmware/Makefile b/firmware/Makefile
index 122ee38..aec801d 100644
--- a/firmware/Makefile
+++ b/firmware/Makefile
@@ -6,141 +6,22 @@
 # Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
 # License: GNU GPL v2 (see License.txt)
 
+CONFIGURATION = t85_default
+#CONFIGURATION = t85_aggressive
+
 ###############################################################################
 # Configure the following variables according to your AVR.
 # Program the device with
 #     make fuse    			# to set the clock generator, boot section size etc.
 #     make flash   			# to load the boot loader into flash
-#     make lock    			# to protect the boot loader from overwriting
-#     make disablereset		# for ATtiny85 target - to use external reset line for IO (CAUTION: this is not easy to enable again, see README) 
-
-F_CPU = 16500000
-DEVICE = attiny85
-FUSEOPT = $(FUSEOPT_t85)
-LOCKOPT = -U lock:w:0x2f:m
+#     make disablereset		# use external reset line for IO (CAUTION: this is not easy to enable again, see README) 
 
-# hexadecimal address for bootloader section to begin. To calculate the best value:
-# - make clean; make main.hex; ### output will list data: 2124 (or something like that)
-# - for the size of your device (8kb = 1024 * 8 = 8192) subtract above value 2124... = 6068
-# - How many pages in is that? 6068 / 64 (tiny85 page size in bytes) = 94.8125
-# - round that down to 94 - our new bootloader address is 94 * 64 = 6016, in hex = 1780
-BOOTLOADER_ADDRESS = 19C0
+CONFIGPATH	  = configuration/$(CONFIGURATION)
+include $(CONFIGPATH)/Makefile.inc
 
 PROGRAMMER = -c USBasp
 # PROGRAMMER contains AVRDUDE options to address your programmer
 
-FUSEOPT_8 = -U hfuse:w:0xc0:m -U lfuse:w:0x9f:m
-FUSEOPT_88 = -U hfuse:w:0xd6:m -U lfuse:w:0xdf:m -U efuse:w:0x00:m
-FUSEOPT_168 = -U hfuse:w:0xd6:m -U lfuse:w:0xdf:m -U efuse:w:0x00:m
-FUSEOPT_328 = -U lfuse:w:0xf7:m -U hfuse:w:0xda:m -U efuse:w:0x03:m
-FUSEOPT_t85 = -U lfuse:w:0xe1:m -U hfuse:w:0xdd:m -U efuse:w:0xfe:m
-FUSEOPT_t85_DISABLERESET = -U lfuse:w:0xe1:m -U efuse:w:0xfe:m -U hfuse:w:0x5d:m
-# You may have to change the order of these -U commands.
-
-#---------------------------------------------------------------------
-# ATMega8
-#---------------------------------------------------------------------
-# Fuse high byte:
-# 0xc0 = 1 1 0 0   0 0 0 0 <-- BOOTRST (boot reset vector at 0x1800)
-#        ^ ^ ^ ^   ^ ^ ^------ BOOTSZ0
-#        | | | |   | +-------- BOOTSZ1
-#        | | | |   + --------- EESAVE (preserve EEPROM over chip erase)
-#        | | | +-------------- CKOPT (full output swing)
-#        | | +---------------- SPIEN (allow serial programming)
-#        | +------------------ WDTON (WDT not always on)
-#        +-------------------- RSTDISBL (reset pin is enabled)
-# Fuse low byte:
-# 0x9f = 1 0 0 1   1 1 1 1
-#        ^ ^ \ /   \--+--/
-#        | |  |       +------- CKSEL 3..0 (external >8M crystal)
-#        | |  +--------------- SUT 1..0 (crystal osc, BOD enabled)
-#        | +------------------ BODEN (BrownOut Detector enabled)
-#        +-------------------- BODLEVEL (2.7V)
-#---------------------------------------------------------------------
-# ATMega88, ATMega168
-#---------------------------------------------------------------------
-# Fuse extended byte:
-# 0x00 = 0 0 0 0   0 0 0 0 <-- BOOTRST (boot reset vector at 0x1800)
-#                    \+/
-#                     +------- BOOTSZ (00 = 2k bytes)
-# Fuse high byte:
-# 0xd6 = 1 1 0 1   0 1 1 0
-#        ^ ^ ^ ^   ^ \-+-/
-#        | | | |   |   +------ BODLEVEL 0..2 (110 = 1.8 V)
-#        | | | |   + --------- EESAVE (preserve EEPROM over chip erase)
-#        | | | +-------------- WDTON (if 0: watchdog always on)
-#        | | +---------------- SPIEN (allow serial programming)
-#        | +------------------ DWEN (debug wire enable)
-#        +-------------------- RSTDISBL (reset pin is enabled)
-# Fuse low byte:
-# 0xdf = 1 1 0 1   1 1 1 1
-#        ^ ^ \ /   \--+--/
-#        | |  |       +------- CKSEL 3..0 (external >8M crystal)
-#        | |  +--------------- SUT 1..0 (crystal osc, BOD enabled)
-#        | +------------------ CKOUT (if 0: Clock output enabled)
-#        +-------------------- CKDIV8 (if 0: divide by 8)
-#---------------------------------------------------------------------
-# ATMega328P
-#---------------------------------------------------------------------
-# Fuse extended byte:
-# 0x03 = - - - -   - 0 1 1
-#                    \-+-/
-#                      +------ BODLEVEL 0..2 (011 = 4.3V)
-# Fuse high byte:
-# 0xda = 1 1 0 1   1 0 1 0 <-- BOOTRST (0 = jump to bootloader at start)
-#        ^ ^ ^ ^   ^ \+/
-#        | | | |   |  +------- BOOTSZ 0..1 (01 = 2KB starting at 0x7800)
-#        | | | |   + --------- EESAVE (don't preserve EEPROM over chip erase)
-#        | | | +-------------- WDTON (1 = watchdog disabled at start)
-#        | | +---------------- SPIEN (0 = allow serial programming)
-#        | +------------------ DWEN (1 = debug wire disable)
-#        +-------------------- RSTDISBL (1 = reset pin is enabled)
-# Fuse low byte:
-# 0xf7 = 1 1 1 1   0 1 1 1
-#        ^ ^ \ /   \--+--/
-#        | |  |       +------- CKSEL 3..0 (0111 = external full-swing crystal)
-#        | |  +--------------- SUT 1..0 (11 = startup time 16K CK/14K + 65ms)
-#        | +------------------ CKOUT (1 = clock output disabled)
-#        +-------------------- CKDIV8 (1 = do not divide clock by 8)
-#---------------------------------------------------------------------
-# ATtiny85
-#---------------------------------------------------------------------
-# Fuse extended byte:
-# 0xFE = - - - -   - 1 1 0
-#                        ^
-#                        |
-#                        +---- SELFPRGEN (enable self programming flash)
-#
-# Fuse high byte:
-# 0xdd = 1 1 0 1   1 1 0 1
-#        ^ ^ ^ ^   ^ \-+-/ 
-#        | | | |   |   +------ BODLEVEL 2..0 (brownout trigger level -> 2.7V)
-#        | | | |   +---------- EESAVE (preserve EEPROM on Chip Erase -> not preserved)
-#        | | | +-------------- WDTON (watchdog timer always on -> disable)
-#        | | +---------------- SPIEN (enable serial programming -> enabled)
-#        | +------------------ DWEN (debug wire enable)
-#        +-------------------- RSTDISBL (disable external reset -> enabled)
-#
-# Fuse high byte ("no reset": external reset disabled, can't program through SPI anymore)
-# 0x5d = 0 1 0 1   1 1 0 1
-#        ^ ^ ^ ^   ^ \-+-/ 
-#        | | | |   |   +------ BODLEVEL 2..0 (brownout trigger level -> 2.7V)
-#        | | | |   +---------- EESAVE (preserve EEPROM on Chip Erase -> not preserved)
-#        | | | +-------------- WDTON (watchdog timer always on -> disable)
-#        | | +---------------- SPIEN (enable serial programming -> enabled)
-#        | +------------------ DWEN (debug wire enable)
-#        +-------------------- RSTDISBL (disable external reset -> disabled!)
-#
-# Fuse low byte:
-# 0xe1 = 1 1 1 0   0 0 0 1
-#        ^ ^ \+/   \--+--/
-#        | |  |       +------- CKSEL 3..0 (clock selection -> HF PLL)
-#        | |  +--------------- SUT 1..0 (BOD enabled, fast rising power)
-#        | +------------------ CKOUT (clock output on CKOUT pin -> disabled)
-#        +-------------------- CKDIV8 (divide clock by 8 -> don't divide)
-
-###############################################################################
-
 # Tools:
 AVRDUDE = avrdude $(PROGRAMMER) -p $(DEVICE)
 CC = avr-gcc
@@ -149,7 +30,10 @@ CC = avr-gcc
 DEFINES = -DBOOTLOADER_ADDRESS=0x$(BOOTLOADER_ADDRESS) #-DDEBUG_LEVEL=2
 # Remove the -fno-* options when you use gcc 3, it does not understand them
 # 
-CFLAGS = -g2 -nostartfiles -ffunction-sections -fdata-sections -fpack-struct -Wall -Os  -fno-inline-small-functions -fno-move-loop-invariants -fno-tree-scev-cprop  -I. -mmcu=$(DEVICE) -DF_CPU=$(F_CPU) $(DEFINES)
+CFLAGS  = -I. -I$(CONFIGPATH) -mmcu=$(DEVICE) -DF_CPU=$(F_CPU) $(DEFINES)
+CFLAGS += -g2  -Wall -Os
+CFLAGS += -nostartfiles -ffunction-sections -fdata-sections -fpack-struct -fno-inline-small-functions -fno-move-loop-invariants -fno-tree-scev-cprop
+
 LDFLAGS = -Wl,--relax,--section-start=.text=$(BOOTLOADER_ADDRESS),-Map=main.map
 
 
@@ -181,10 +65,7 @@ fuse:
 	$(AVRDUDE) $(FUSEOPT)
 	
 disablereset:
-	$(AVRDUDE) $(FUSEOPT_t85_DISABLERESET)
-
-lock:
-	$(AVRDUDE) $(LOCKOPT)
+	$(AVRDUDE) $(FUSEOPT_DISABLERESET)
 
 read_fuses:
 	$(UISP) --rd_fuses
@@ -214,26 +95,3 @@ upgrade: main.bin
 	
 disasm:	main.bin
 	@avr-objdump -d -S main.bin >main.lss
-
-cpp:
-	@$(CC) $(CFLAGS) -E main.c
-
-# Special rules for generating hex files for various devices and clock speeds
-ALLHEXFILES = hexfiles/mega8_12mhz.hex hexfiles/mega8_15mhz.hex hexfiles/mega8_16mhz.hex \
-	hexfiles/mega88_12mhz.hex hexfiles/mega88_15mhz.hex hexfiles/mega88_16mhz.hex hexfiles/mega88_20mhz.hex\
-	hexfiles/mega168_12mhz.hex hexfiles/mega168_15mhz.hex hexfiles/mega168_16mhz.hex hexfiles/mega168_20mhz.hex\
-	hexfiles/mega328p_12mhz.hex hexfiles/mega328p_15mhz.hex hexfiles/mega328p_16mhz.hex hexfiles/mega328p_20mhz.hex
-
-allhexfiles: $(ALLHEXFILES)
-	$(MAKE) clean
-	avr-size hexfiles/*.hex
-
-$(ALLHEXFILES):
-	@[ -d hexfiles ] || mkdir hexfiles
-	@device=`echo $@ | sed -e 's|.*/mega||g' -e 's|_.*||g'`; \
-	clock=`echo $@ | sed -e 's|.*_||g' -e 's|mhz.*||g'`; \
-	addr=`echo $$device | sed -e 's/\([0-9]\)8/\1/g' | awk '{printf("%x", ($$1 - 2) * 1024)}'`; \
-	echo "### Make with F_CPU=$${clock}000000 DEVICE=atmega$$device BOOTLOADER_ADDRESS=$$addr"; \
-	$(MAKE) clean; \
-	$(MAKE) main.hex F_CPU=$${clock}000000 DEVICE=atmega$$device BOOTLOADER_ADDRESS=$$addr DEFINES=-DUSE_AUTOCONFIG=1
-	mv main.hex $@
diff --git a/firmware/configuration/t85_aggressive/Makefile.inc b/firmware/configuration/t85_aggressive/Makefile.inc
new file mode 100644
index 0000000..016f848
--- /dev/null
+++ b/firmware/configuration/t85_aggressive/Makefile.inc
@@ -0,0 +1,62 @@
+# Name: Makefile
+# Project: Micronucleus
+# License: GNU GPL v2 (see License.txt)
+
+# Controller type: ATtiny 85
+# Configuration:   Size optimized. Uses 16 MHz V-USB implementation, which may be instable with some computers
+# Last Change:     Mar 16,2014
+ 
+
+F_CPU = 16000000
+DEVICE = attiny85
+FUSEOPT = $(FUSEOPT_t85)
+LOCKOPT = -U lock:w:0x2f:m
+
+# hexadecimal address for bootloader section to begin. To calculate the best value:
+# - make clean; make main.hex; ### output will list data: 2124 (or something like that)
+# - for the size of your device (8kb = 1024 * 8 = 8192) subtract above value 2124... = 6068
+# - How many pages in is that? 6068 / 64 (tiny85 page size in bytes) = 94.8125
+# - round that down to 94 - our new bootloader address is 94 * 64 = 6016, in hex = 1780
+BOOTLOADER_ADDRESS = 1A40
+
+FUSEOPT_t85 = -U lfuse:w:0xe1:m -U hfuse:w:0xdd:m -U efuse:w:0xfe:m
+FUSEOPT_t85_DISABLERESET = -U lfuse:w:0xe1:m -U efuse:w:0xfe:m -U hfuse:w:0x5d:m
+
+#---------------------------------------------------------------------
+# ATtiny85
+#---------------------------------------------------------------------
+# Fuse extended byte:
+# 0xFE = - - - -   - 1 1 0
+#                        ^
+#                        |
+#                        +---- SELFPRGEN (enable self programming flash)
+#
+# Fuse high byte:
+# 0xdd = 1 1 0 1   1 1 0 1
+#        ^ ^ ^ ^   ^ \-+-/ 
+#        | | | |   |   +------ BODLEVEL 2..0 (brownout trigger level -> 2.7V)
+#        | | | |   +---------- EESAVE (preserve EEPROM on Chip Erase -> not preserved)
+#        | | | +-------------- WDTON (watchdog timer always on -> disable)
+#        | | +---------------- SPIEN (enable serial programming -> enabled)
+#        | +------------------ DWEN (debug wire enable)
+#        +-------------------- RSTDISBL (disable external reset -> enabled)
+#
+# Fuse high byte ("no reset": external reset disabled, can't program through SPI anymore)
+# 0x5d = 0 1 0 1   1 1 0 1
+#        ^ ^ ^ ^   ^ \-+-/ 
+#        | | | |   |   +------ BODLEVEL 2..0 (brownout trigger level -> 2.7V)
+#        | | | |   +---------- EESAVE (preserve EEPROM on Chip Erase -> not preserved)
+#        | | | +-------------- WDTON (watchdog timer always on -> disable)
+#        | | +---------------- SPIEN (enable serial programming -> enabled)
+#        | +------------------ DWEN (debug wire enable)
+#        +-------------------- RSTDISBL (disable external reset -> disabled!)
+#
+# Fuse low byte:
+# 0xe1 = 1 1 1 0   0 0 0 1
+#        ^ ^ \+/   \--+--/
+#        | |  |       +------- CKSEL 3..0 (clock selection -> HF PLL)
+#        | |  +--------------- SUT 1..0 (BOD enabled, fast rising power)
+#        | +------------------ CKOUT (clock output on CKOUT pin -> disabled)
+#        +-------------------- CKDIV8 (divide clock by 8 -> don't divide)
+
+###############################################################################
diff --git a/firmware/configuration/t85_aggressive/bootloaderconfig.h b/firmware/configuration/t85_aggressive/bootloaderconfig.h
new file mode 100644
index 0000000..0613d79
--- /dev/null
+++ b/firmware/configuration/t85_aggressive/bootloaderconfig.h
@@ -0,0 +1,253 @@
+/* Name: bootloaderconfig.h
+ * Micronucleus configuration file. 
+ * This file (together with some settings in Makefile) configures the boot loader
+ * according to the hardware.
+ * 
+ * Controller type: ATtiny 85
+ * Configuration:   Size optimized. Uses 16 MHz V-USB implementation, which may be instable with some computers
+ * Last Change:     Mar 16,2014
+ *
+ * License: GNU GPL v2 (see License.txt
+ */
+
+#ifndef __bootloaderconfig_h_included__
+#define __bootloaderconfig_h_included__
+
+/* ------------------------------------------------------------------------- */
+/*                       Hardware configuration.                             */
+/*      Change this according to your CPU and USB configuration              */
+/* ------------------------------------------------------------------------- */
+
+#define USB_CFG_IOPORTNAME      B
+  /* This is the port where the USB bus is connected. When you configure it to
+   * "B", the registers PORTB, PINB and DDRB will be used.
+   */
+
+#define USB_CFG_DMINUS_BIT      3
+/* This is the bit number in USB_CFG_IOPORT where the USB D- line is connected.
+ * This may be any bit in the port.
+ */
+#define USB_CFG_DPLUS_BIT       4
+/* This is the bit number in USB_CFG_IOPORT where the USB D+ line is connected.
+ * This may be any bit in the port, but must be configured as a pin change interrupt.
+ */
+
+#define USB_CFG_CLOCK_KHZ       (F_CPU/1000)
+/* Clock rate of the AVR in kHz. Legal values are 12000, 12800, 15000, 16000,
+ * 16500, 18000 and 20000. The 12.8 MHz and 16.5 MHz versions of the code
+ * require no crystal, they tolerate +/- 1% deviation from the nominal
+ * frequency. All other rates require a precision of 2000 ppm and thus a
+ * crystal!
+ * Since F_CPU should be defined to your actual clock rate anyway, you should
+ * not need to modify this setting.
+ */
+
+/* ------------- Set up interrupt configuration (CPU specific) --------------   */
+/* The register names change quite a bit in the ATtiny family. Pay attention    */
+/* to the manual. Note that the interrupt flag system is still used even though */
+/* interrupts are disabled. So this has to be configured correctly.             */
+
+
+// setup interrupt for Pin Change for D+
+#define USB_INTR_CFG            PCMSK
+#define USB_INTR_CFG_SET        (1 << USB_CFG_DPLUS_BIT)
+#define USB_INTR_CFG_CLR        0
+#define USB_INTR_ENABLE         GIMSK
+#define USB_INTR_ENABLE_BIT     PCIE
+#define USB_INTR_PENDING        GIFR
+#define USB_INTR_PENDING_BIT    PCIF
+#define USB_INTR_VECTOR         PCINT0_vect
+
+/* ------------------------------------------------------------------------- */
+/*       Configuration relevant to the CPU the bootloader is running on      */
+/* ------------------------------------------------------------------------- */
+
+// how many milliseconds should host wait till it sends another erase or write?
+// needs to be above 4.5 (and a whole integer) as avr freezes for 4.5ms
+#define MICRONUCLEUS_WRITE_SLEEP 5
+
+
+/* ---------------------- feature / code size options ---------------------- */
+/*               Configure the behavior of the bootloader here               */
+/* ------------------------------------------------------------------------- */
+
+/*
+ *  Define Bootloader entry condition
+ * 
+ *  If the entry condition is not met, the bootloader will not be activated and the user program
+ *  is executed directly after a reset. If no user program has been loaded, the bootloader
+ *  is always active.
+ * 
+ *  ENTRY_ALWAYS        Always activate the bootloader after reset. Requires the least
+ *                      amount of code.
+ *
+ *  ENTRY_WATCHDOG      Activate the bootloader after a watchdog reset. This can be used
+ *                      to enter the bootloader from the user program.
+ *                      Adds 22 bytes.
+ *
+ *  ENTRY_EXT_RESET     Activate the bootloader after an external reset was issued by 
+ *                      pulling the reset pin low. It may be necessary to add an external
+ *                      pull-up resistor to the reset pin if this entry method appears to
+ *                      behave unreliably.
+ *                      Adds 22 bytes.
+ *
+ *  ENTRY_JUMPER        Activate the bootloader when a specific pin is pulled low by an 
+ *                      external jumper. 
+ *                      Adds 34 bytes.
+ *
+ *       JUMPER_PIN     Pin the jumper is connected to. (e.g. PB0)
+ *       JUMPER_PORT    Port out register for the jumper (e.g. PORTB)  
+ *       JUMPER_DDR     Port data direction register for the jumper (e.g. DDRB)  
+ *       JUMPER_INP     Port inout register for the jumper (e.g. PINB)  
+ * 
+ */
+
+#define ENTRYMODE ENTRY_ALWAYS
+
+#define JUMPER_PIN    PB0
+#define JUMPER_PORT   PORTB 
+#define JUMPER_DDR    DDRB 
+#define JUMPER_INP    PINB 
+ 
+/*
+  Internal implementation, don't change this unless you want to add an entrymode.
+*/ 
+ 
+#define ENTRY_ALWAYS    1
+#define ENTRY_WATCHDOG  2
+#define ENTRY_EXT_RESET 3
+#define ENTRY_JUMPER    4
+
+#if ENTRYMODE==ENTRY_ALWAYS
+  #define bootLoaderInit()
+  #define bootLoaderExit()
+  #define bootLoaderStartCondition() 1
+#elif ENTRYMODE==ENTRY_WATCHDOG
+  #define bootLoaderInit()
+  #define bootLoaderExit()
+  #define bootLoaderStartCondition() (MCUSR&_BV(WDRF))
+#elif ENTRYMODE==ENTRY_EXT_RESET
+  #define bootLoaderInit()
+  #define bootLoaderExit()
+  #define bootLoaderStartCondition() (MCUSR&_BV(EXTRF))
+#elif ENTRYMODE==ENTRY_JUMPER
+  // Enable pull up on jumper pin and delay to stabilize input    
+  #define bootLoaderInit()   {JUMPER_DDR&=~_BV(JUMPER_PIN);JUMPER_PORT|=_BV(JUMPER_PIN);_delay_ms(1);}
+  #define bootLoaderExit()   {JUMPER_PORT&=~_BV(JUMPER_PIN);}
+  #define bootLoaderStartCondition() (!(JUMPER_INP&_BV(JUMPER_PIN)))
+#else
+   #error "No entry mode defined"
+#endif
+
+/*
+ * Define bootloader timeout value. 
+ * 
+ *  The bootloader will only time out if a user program was loaded.
+ * 
+ *  AUTO_EXIT_NO_USB_MS        The bootloader will exit after this delay if no USB is connected.
+ *                             Set to 0 to disable
+ *                             Adds ~6 bytes.
+ *                             (This will wait for an USB SE0 reset from the host)
+ *
+ *  AUTO_EXIT_MS               The bootloader will exit after this delay if no USB communication
+ *                             from the host tool was received.
+ *                             Set to 0 to disable
+ *  
+ *  All values are approx. in milliseconds
+ */
+
+#define AUTO_EXIT_NO_USB_MS    0
+#define AUTO_EXIT_MS           6000
+
+ /*
+ *  Defines the setting of the RC-oscillator calibration after quitting the bootloader. (OSCCAL)
+ * 
+ *  OSCCAL_RESTORE            Set this to '1' to revert to factory calibration, which is 16.0 MHZ +/-10%
+ *                            Adds ~14 bytes.
+ *
+ *  OSCCAL_16.5MHz            Set this to '1' to use the same calibration as during program upload.
+ *                            This value is 16.5Mhz +/-1% as calibrated from the USB timing. Please note
+ *                            that only true if the ambient temperature does not change.
+ *                            This is the default behaviour of the original Digispark and is not recommended
+ *                            for use on devices other than the ATtiny85.
+ *                            Adds ~38 bytes.
+ *
+ *  OSCCAL_HAVE_XTAL          Set this to '1' if you have an external crystal oscillator. In this case no attempt
+ *                            will be made to calibrate the oscillator. You should deactivate both options above
+ *                            if you use this to avoid redundant code.
+ *
+ *  If both options are selected, OSCCAL_RESTORE takes precedence.
+ *
+ *  If no option is selected, OSCCAL will be left untouched and stays at either 16.0 Mhz or 16.5 Mhz depending
+ *  on whether the bootloader was activated. This will take the least memory. You can use this if your program
+ *  comes with its own OSCCAL calibration or an external clock source is used. 
+ */
+ 
+#define OSCCAL_RESTORE 0
+#define OSCCAL_16_5MHz 0
+#define OSCCAL_HAVE_XTAL 0
+  
+/*  
+ *  Defines handling of an indicator LED while the bootloader is active.  
+ * 
+ *  LED_MODE                  Define behavior of attached LED or suppress LED code.
+ *
+ *          NONE              Do not generate LED code (gains 18 bytes).
+ *          ACTIVE_HIGH       LED is on when output pin is high. This will toggle bettwen 1 and 0.
+ *          ACTIVE_LOW        LED is on when output pin is low.  This will toggle between Z and 0.
+ *
+ *  LED_DDR,LED_PORT,LED_PIN  Where is your LED connected?
+ *
+ */ 
+
+#define LED_MODE    NONE
+
+#define LED_DDR     DDRB
+#define LED_PORT    PORTB
+#define LED_PIN     PB1
+
+/*
+ *  This is the implementation of the LED code. Change the configuration above unless you want to 
+ *  change the led behavior
+ *
+ *  LED_INIT                  Called once after bootloader entry
+ *  LED_EXIT                  Called once during bootloader exit
+ *  LED_MACRO                 Called in the main loop with the idle counter as parameter.
+ *                            Use to define pattern.
+*/
+
+#define NONE        0
+#define ACTIVE_HIGH 1
+#define ACTIVE_LOW  2
+
+#if LED_MODE==ACTIVE_HIGH
+  #define LED_INIT(x)   LED_DDR   = _BV(LED_PIN); 
+  #define LED_EXIT(x)   {LED_DDR  &=~_BV(LED_PIN);LED_PORT  &=~_BV(LED_PIN);}
+  #define LED_MACRO(x)  if ( x & 0x4c ) {LED_PORT&=~_BV(LED_PIN);} else {LED_PORT|=_BV(LED_PIN);}
+#elif LED_MODE==ACTIVE_LOW
+  #define LED_INIT(x)   LED_PORT &=~_BV(LED_PIN);   
+  #define LED_EXIT(x)   LED_DDR  &=~_BV(LED_PIN);
+  #define LED_MACRO(x)  if ( x & 0x4c ) {LED_DDR&=~_BV(LED_PIN);} else {LED_DDR|=_BV(LED_PIN);}  
+#elif LED_MODE==NONE
+  #define LED_INIT(x)
+  #define LED_EXIT(x)
+  #define LED_MACRO(x)
+#endif
+
+/* --------------------------------------------------------------------------- */
+/* Micronucleus internal configuration. Do not change anything below this line */
+/* --------------------------------------------------------------------------- */
+
+// Microcontroller vectortable entries in the flash
+#define RESET_VECTOR_OFFSET         0
+
+// number of bytes before the boot loader vectors to store the tiny application vector table
+#define TINYVECTOR_RESET_OFFSET     4
+#define TINYVECTOR_OSCCAL_OFFSET    6
+
+/* ------------------------------------------------------------------------ */
+// postscript are the few bytes at the end of programmable memory which store tinyVectors
+#define POSTSCRIPT_SIZE 6
+#define PROGMEM_SIZE (BOOTLOADER_ADDRESS - POSTSCRIPT_SIZE) /* max size of user program */
+
+#endif /* __bootloader_h_included__ */
diff --git a/firmware/configuration/t85_default/Makefile.inc b/firmware/configuration/t85_default/Makefile.inc
new file mode 100644
index 0000000..8b856a3
--- /dev/null
+++ b/firmware/configuration/t85_default/Makefile.inc
@@ -0,0 +1,62 @@
+# Name: Makefile
+# Project: Micronucleus
+# License: GNU GPL v2 (see License.txt)
+#
+# Controller type: ATtiny 85
+# Configuration:   Digispark default configuration. 
+# Last Change:     Mar 16,2014
+ 
+
+F_CPU = 16500000
+DEVICE = attiny85
+FUSEOPT = $(FUSEOPT_t85)
+LOCKOPT = -U lock:w:0x2f:m
+
+# hexadecimal address for bootloader section to begin. To calculate the best value:
+# - make clean; make main.hex; ### output will list data: 2124 (or something like that)
+# - for the size of your device (8kb = 1024 * 8 = 8192) subtract above value 2124... = 6068
+# - How many pages in is that? 6068 / 64 (tiny85 page size in bytes) = 94.8125
+# - round that down to 94 - our new bootloader address is 94 * 64 = 6016, in hex = 1780
+BOOTLOADER_ADDRESS = 19C0
+
+FUSEOPT_t85 = -U lfuse:w:0xe1:m -U hfuse:w:0xdd:m -U efuse:w:0xfe:m
+FUSEOPT_t85_DISABLERESET = -U lfuse:w:0xe1:m -U efuse:w:0xfe:m -U hfuse:w:0x5d:m
+
+#---------------------------------------------------------------------
+# ATtiny85
+#---------------------------------------------------------------------
+# Fuse extended byte:
+# 0xFE = - - - -   - 1 1 0
+#                        ^
+#                        |
+#                        +---- SELFPRGEN (enable self programming flash)
+#
+# Fuse high byte:
+# 0xdd = 1 1 0 1   1 1 0 1
+#        ^ ^ ^ ^   ^ \-+-/ 
+#        | | | |   |   +------ BODLEVEL 2..0 (brownout trigger level -> 2.7V)
+#        | | | |   +---------- EESAVE (preserve EEPROM on Chip Erase -> not preserved)
+#        | | | +-------------- WDTON (watchdog timer always on -> disable)
+#        | | +---------------- SPIEN (enable serial programming -> enabled)
+#        | +------------------ DWEN (debug wire enable)
+#        +-------------------- RSTDISBL (disable external reset -> enabled)
+#
+# Fuse high byte ("no reset": external reset disabled, can't program through SPI anymore)
+# 0x5d = 0 1 0 1   1 1 0 1
+#        ^ ^ ^ ^   ^ \-+-/ 
+#        | | | |   |   +------ BODLEVEL 2..0 (brownout trigger level -> 2.7V)
+#        | | | |   +---------- EESAVE (preserve EEPROM on Chip Erase -> not preserved)
+#        | | | +-------------- WDTON (watchdog timer always on -> disable)
+#        | | +---------------- SPIEN (enable serial programming -> enabled)
+#        | +------------------ DWEN (debug wire enable)
+#        +-------------------- RSTDISBL (disable external reset -> disabled!)
+#
+# Fuse low byte:
+# 0xe1 = 1 1 1 0   0 0 0 1
+#        ^ ^ \+/   \--+--/
+#        | |  |       +------- CKSEL 3..0 (clock selection -> HF PLL)
+#        | |  +--------------- SUT 1..0 (BOD enabled, fast rising power)
+#        | +------------------ CKOUT (clock output on CKOUT pin -> disabled)
+#        +-------------------- CKDIV8 (divide clock by 8 -> don't divide)
+
+###############################################################################
diff --git a/firmware/bootloaderconfig.h b/firmware/configuration/t85_default/bootloaderconfig.h
index 15f3dcf..4ea59dd 100644
--- a/firmware/bootloaderconfig.h
+++ b/firmware/configuration/t85_default/bootloaderconfig.h
@@ -183,8 +183,8 @@
  *  comes with its own OSCCAL calibration or an external clock source is used. 
  */
  
-#define OSCCAL_RESTORE 1
-#define OSCCAL_16_5MHz 0
+#define OSCCAL_RESTORE 0
+#define OSCCAL_16_5MHz 1
 #define OSCCAL_HAVE_XTAL 0
   
 /*