fish

13 files changed, 2349 insertions, 0 deletions

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..cdb6e7a
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,33 @@
+db
+incremental_db
+*.qws
+*.rpt
+*.bak
+*.pof
+*.sof
+*.done
+*.fit.summary
+*.jdi
+*.map.summary
+*.sta.summary
+*.sopcinfo
+script/
+*~
+src/*.elf
+src/*.objdump
+src/*.map
+bsp
+*.swp
+elf.flash
+sof.flash
+*.stamp
+src/Makefile
+src/obj
+*.pin
+.qsys_edit
+.sopc_builder
+*.bsf
+sdram_mcu/
+sdram_mcu.cmp
+sdram_mcu.html
+*.smsg
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..9f28202
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,112 @@
+PROJ=sdram_test
+
+SRCS=$(wildcard *.vhd *.v *.qsf *.qpf )
+SRCS += $(shell find async_16bit_bus_adapter_hw -type f -print )
+
+BSP_DIR=bsp
+QSYS=sdram_test_mcu
+SOPC_FILE=${QSYS}.sopcinfo
+BSP_TYPE=hal
+NIOS2_BSP_ARGS=""
+CPU_NAME=
+
+ELF=src/${PROJ}.elf
+SOF=${PROJ}.sof
+
+default: run
+
+run: load_elf.stamp
+	tools/wrap nios2-terminal
+
+build: ${ELF} ${SOF}
+
+#default: load_sof.stamp
+
+
+sta.stamp:asm.stamp
+	tools/wrap quartus_sta ${PROJ} -c ${PROJ}
+	touch $@
+
+asm.stamp:fit.stamp
+	tools/wrap quartus_asm --read_settings_files=off --write_settings_files=off ${PROJ} -c ${PROJ}
+	touch $@
+
+${SOF}:asm.stamp
+
+fit.stamp: ans.stamp
+	tools/wrap quartus_fit --read_settings_files=off --write_settings_files=off ${PROJ} -c ${PROJ}
+	touch $@
+
+#ans.stamp: source.stamp ${SOPC_FILE}
+ans.stamp: source.stamp
+	tools/wrap quartus_map --read_settings_files=on --write_settings_files=off ${PROJ} -c ${PROJ}
+	touch $@
+ 
+${SOPC_FILE}:asm.stamp
+
+#${SOPC_FILE}:${QSYS}.qsys
+#	rm -rf ${QSYS}
+#	tools/wrap ip-generate --project-directory=. --output-directory=${QSYS}/synthesis --file-set=QUARTUS_SYNTH --report-file=sopcinfo:${SOPC_FILE} --report-file=html:${QSYS}.html --report-file=qip:${QSYS}.qip --report-file=cmp:${QSYS}.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone II" --system-info=DEVICE=EP2C8Q208C8 --system-info=DEVICE_SPEEDGRADE=8 --component-file=${QSYS}.qsys --language=VHDL
+#
+
+source.stamp:${SRCS}
+	touch source.stamp
+
+${ELF}: src/Makefile $(wildcard src/*.c)
+	tools/wrap make -C src
+
+elf.stamp:${ELF}
+	touch $@
+	
+src/Makefile: bsp.stamp
+	tools/wrap nios2-app-generate-makefile --bsp-dir bsp --src-rdir src --app-dir src --elf-name ${PROJ}.elf
+
+bsp.stamp:${SOPC_FILE}
+	/bin/rm -rf ${BSP_DIR}
+	mkdir -p ${BSP_DIR}
+	tools/wrap nios2-bsp ${BSP_TYPE} ${BSP_DIR} ${SOPC_FILE} ${NIOS2_BSP_ARGS} ${CPU_NAME}
+#	tools/wrap nios2-bsp-update-settings --bsp-dir ${BSP_DIR} --settings bsp/settings.bsp \
+#		--set hal.sys_clk_timer none \
+#		--set hal.max_file_descriptors 4 \
+#		--set hal.enable_c_plus_plus 0 \
+#		--set hal.make.bsp_cflags_optimization -Os \
+#		--set hal.enable_exit 0 \
+#		--set hal.enable_small_c_library 1 \
+#		--set hal.enable_clean_exit 0 \
+#		--set hal.enable_reduced_device_drivers 1 \
+#		--set hal.enable_lightweight_device_driver_api 1
+#	tools/wrap nios2-bsp-generate-files --bsp-dir ${BSP_DIR} --settings bsp/settings.bsp
+	tools/wrap make -C ${BSP_DIR}
+	touch $@
+
+load_elf.stamp:${ELF} load_sof.stamp
+	tools/wrap nios2-download ${ELF} -g
+
+load_sof.stamp: ${SOF}
+	tools/wrap quartus_pgm -m JTAG -o "p;${SOF}"
+	touch $@
+
+sof.flash: ${SOF}
+	tools/wrap sof2flash --input=$< --output=$@ --epcs --verbose 
+
+elf.flash: ${ELF} sof.flash
+	tools/wrap elf2flash --input=${ELF} --output=$@ --epcs --after=sof.flash --verbose 
+
+qsys:
+	tools/wrap qsys-edit ${QSYS}.qsys --project-dir=${PWD} --system-info=DEVICE_FAMILY="Cyclone II" --system-info=DEVICE=EP2C8Q208C8 --system-info=DEVICE_SPEEDGRADE=8 --host-controller
+
+${BSP_DIR}/system.h:bsp.stamp
+
+flash: load_sof.stamp sof.flash elf.flash ${BSP_DIR}/system.h
+	BASE=` grep EPCS_FLASH_CONTROLLER_0_BASE ${BSP_DIR}/system.h | awk '{print $$3}' ` && \
+	tools/wrap nios2-flash-programmer sof.flash --base=$${BASE} --epcs --accept-bad-sysid --device=1 --instance=0 --program --verbose && \
+	tools/wrap nios2-flash-programmer elf.flash --base=$${BASE} --epcs --accept-bad-sysid --device=1 --instance=0  --program --verbose -g
+
+clean:
+	/bin/rm -rf ${BSP_DIR} db incremental_db src/obj ${QSYS}
+	/bin/rm -f ${SOPC_FILE} src/Makefile elf.flash sof.flash *.stamp ${SOF} ${ELF} *.rpt *.html *.summary *.pin *.jdi *.qws *.pof *.done *.cmp *.qdi *.bsf
+	/bin/rm -f src/${PROJ}.objdump src/${PROJ}.map 
+	/bin/rm -f sopc_builder_log.txt  *.qip *.smsg
+	
+	
+	
diff --git a/async_16bit_bus_adapter_hw/async_16bit_bus_adapter_hw.tcl b/async_16bit_bus_adapter_hw/async_16bit_bus_adapter_hw.tcl
new file mode 100644
index 0000000..d18a0ed
--- /dev/null
+++ b/async_16bit_bus_adapter_hw/async_16bit_bus_adapter_hw.tcl
@@ -0,0 +1,145 @@
+# TCL File Generated by Component Editor 13.0sp1
+# Mon Oct 14 19:47:04 BST 2013
+# DO NOT MODIFY
+
+
+# 
+# async_16bit_bus_adapter "async_16bit_bus_adapter" v1.0
+#  2013.10.14.19:47:04
+# 
+# 
+
+# 
+# request TCL package from ACDS 13.1
+# 
+package require -exact qsys 13.1
+
+
+# 
+# module async_16bit_bus_adapter
+# 
+set_module_property DESCRIPTION ""
+set_module_property NAME async_16bit_bus_adapter
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP my_lib
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME async_16bit_bus_adapter
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property ANALYZE_HDL AUTO
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL async_16bit_bus_adapter
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+add_fileset_file async_16bit_bus_adapter.vhd VHDL PATH hdl/async_16bit_bus_adapter.vhd TOP_LEVEL_FILE
+
+
+# 
+# parameters
+# 
+add_parameter AUTO_CLOCK_CLOCK_RATE STRING -1 ""
+set_parameter_property AUTO_CLOCK_CLOCK_RATE DEFAULT_VALUE -1
+set_parameter_property AUTO_CLOCK_CLOCK_RATE DISPLAY_NAME AUTO_CLOCK_CLOCK_RATE
+set_parameter_property AUTO_CLOCK_CLOCK_RATE WIDTH ""
+set_parameter_property AUTO_CLOCK_CLOCK_RATE TYPE STRING
+set_parameter_property AUTO_CLOCK_CLOCK_RATE UNITS None
+set_parameter_property AUTO_CLOCK_CLOCK_RATE DESCRIPTION ""
+set_parameter_property AUTO_CLOCK_CLOCK_RATE HDL_PARAMETER true
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point clock
+# 
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+# 
+# connection point avalon_slave
+# 
+add_interface avalon_slave avalon end
+set_interface_property avalon_slave addressUnits WORDS
+set_interface_property avalon_slave associatedClock clock
+set_interface_property avalon_slave associatedReset reset
+set_interface_property avalon_slave bitsPerSymbol 8
+set_interface_property avalon_slave burstOnBurstBoundariesOnly false
+set_interface_property avalon_slave burstcountUnits WORDS
+set_interface_property avalon_slave explicitAddressSpan 0
+set_interface_property avalon_slave holdTime 0
+set_interface_property avalon_slave linewrapBursts false
+set_interface_property avalon_slave maximumPendingReadTransactions 0
+set_interface_property avalon_slave readLatency 0
+set_interface_property avalon_slave readWaitTime 1
+set_interface_property avalon_slave setupTime 0
+set_interface_property avalon_slave timingUnits Cycles
+set_interface_property avalon_slave writeWaitTime 0
+set_interface_property avalon_slave ENABLED true
+set_interface_property avalon_slave EXPORT_OF ""
+set_interface_property avalon_slave PORT_NAME_MAP ""
+set_interface_property avalon_slave SVD_ADDRESS_GROUP ""
+
+add_interface_port avalon_slave cs_n chipselect_n Input 1
+add_interface_port avalon_slave address address Input 16
+add_interface_port avalon_slave writedata writedata Input 16
+add_interface_port avalon_slave wr_n write_n Input 1
+add_interface_port avalon_slave rd_n read_n Input 1
+add_interface_port avalon_slave wait_n waitrequest_n Output 1
+add_interface_port avalon_slave readdata readdata Output 16
+set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0
+set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0
+
+
+# 
+# connection point sbb
+# 
+add_interface sbb conduit end
+set_interface_property sbb associatedClock clock
+set_interface_property sbb associatedReset ""
+set_interface_property sbb ENABLED true
+set_interface_property sbb EXPORT_OF ""
+set_interface_property sbb PORT_NAME_MAP ""
+set_interface_property sbb SVD_ADDRESS_GROUP ""
+
+add_interface_port sbb b_reset_n export Output 1
+add_interface_port sbb b_cs_n export Output 1
+add_interface_port sbb b_rnw export Output 1
+add_interface_port sbb b_wait_n export Input 1
+add_interface_port sbb b_addr export Output 16
+add_interface_port sbb b_data_in export Input 16
+add_interface_port sbb b_data_out export Output 16
+
+
+# 
+# connection point reset
+# 
+add_interface reset reset end
+set_interface_property reset associatedClock clock
+set_interface_property reset synchronousEdges DEASSERT
+set_interface_property reset ENABLED true
+set_interface_property reset EXPORT_OF ""
+set_interface_property reset PORT_NAME_MAP ""
+set_interface_property reset SVD_ADDRESS_GROUP ""
+
+add_interface_port reset rst_n reset_n Input 1
+
diff --git a/async_16bit_bus_adapter_hw/hdl/async_16bit_bus_adapter.vhd b/async_16bit_bus_adapter_hw/hdl/async_16bit_bus_adapter.vhd
new file mode 100644
index 0000000..9c8a806
--- /dev/null
+++ b/async_16bit_bus_adapter_hw/hdl/async_16bit_bus_adapter.vhd
@@ -0,0 +1,54 @@
+-- async_8bit_bus_adapter.vhd
+
+-- This file was auto-generated as a prototype implementation of a module
+-- created in component editor.  It ties off all outputs to ground and
+-- ignores all inputs.  It needs to be edited to make it do something
+-- useful.
+-- 
+-- This file will not be automatically regenerated.  You should check it in
+-- to your version control system if you want to keep it.
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity async_8bit_bus_adapter is
+	generic (
+		AUTO_CLOCK_CLOCK_RATE : string := "-1"
+	);
+	port (
+		clk        : in  std_logic                     := '0';             --         clock.clk
+		rst_n      : in  std_logic                     := '0';             --         reset.reset_n
+		cs_n       : in  std_logic                     := '0';             --  avalon_slave.chipselect_n
+		address    : in  std_logic_vector(15 downto 0) := (others => '0'); --              .address
+		writedata  : in  std_logic_vector(15 downto 0)  := (others => '0'); --              .writedata
+		wr_n       : in  std_logic                     := '0';             --              .write_n
+		rd_n       : in  std_logic                     := '0';             --              .read_n
+		wait_n     : out std_logic;                                        --              .waitrequest_n
+		readdata   : out std_logic_vector(15 downto 0);                     --              .readdata
+		b_reset_n  : out std_logic;                                        -- eight_bit_bus.export
+		b_cs_n     : out std_logic;                                        --              .export
+		b_rnw      : out std_logic;                                        --              .export
+		b_wait_n   : in  std_logic                     := '0';             --              .export
+		b_addr     : out std_logic_vector(15 downto 0);                    --              .export
+		b_data_in  : in  std_logic_vector(15 downto 0)  := (others => '0'); --              .export
+		b_data_out : out std_logic_vector(15 downto 0)                      --              .export
+	);
+end entity async_8bit_bus_adapter;
+
+architecture rtl of async_8bit_bus_adapter is
+
+signal state:std_logic_vector(2 downto 0);
+begin
+
+	b_addr <= address;
+	readdata <= b_data_in;
+	b_data_out <= writedata;
+
+	b_reset_n <= rst_n;
+	b_cs_n <= cs_n or ( wr_n and rd_n );
+	b_rnw <= wr_n;
+	wait_n <= b_wait_n;
+
+
+end architecture rtl; -- of async_8bit_bus_adapter
diff --git a/pllx2.vhd b/pllx2.vhd
new file mode 100644
index 0000000..6fa7af2
--- /dev/null
+++ b/pllx2.vhd
@@ -0,0 +1,365 @@
+-- megafunction wizard: %ALTPLL%

+-- GENERATION: STANDARD

+-- VERSION: WM1.0

+-- MODULE: altpll 

+

+-- ============================================================

+-- File Name: pllx2.vhd

+-- Megafunction Name(s):

+-- 			altpll

+--

+-- Simulation Library Files(s):

+-- 			altera_mf

+-- ============================================================

+-- ************************************************************

+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

+--

+-- 9.1 Build 222 10/21/2009 SJ Web Edition

+-- ************************************************************

+

+

+--Copyright (C) 1991-2009 Altera Corporation

+--Your use of Altera Corporation's design tools, logic functions 

+--and other software and tools, and its AMPP partner logic 

+--functions, and any output files from any of the foregoing 

+--(including device programming or simulation files), and any 

+--associated documentation or information are expressly subject 

+--to the terms and conditions of the Altera Program License 

+--Subscription Agreement, Altera MegaCore Function License 

+--Agreement, or other applicable license agreement, including, 

+--without limitation, that your use is for the sole purpose of 

+--programming logic devices manufactured by Altera and sold by 

+--Altera or its authorized distributors.  Please refer to the 

+--applicable agreement for further details.

+

+

+LIBRARY ieee;

+USE ieee.std_logic_1164.all;

+

+LIBRARY altera_mf;

+USE altera_mf.all;

+

+ENTITY pllx2 IS

+	PORT

+	(

+		areset		: IN STD_LOGIC  := '0';

+		inclk0		: IN STD_LOGIC  := '0';

+		c0		: OUT STD_LOGIC ;

+		locked		: OUT STD_LOGIC 

+	);

+END pllx2;

+

+

+ARCHITECTURE SYN OF pllx2 IS

+

+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (5 DOWNTO 0);

+	SIGNAL sub_wire1	: STD_LOGIC ;

+	SIGNAL sub_wire2	: STD_LOGIC ;

+	SIGNAL sub_wire3	: STD_LOGIC ;

+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);

+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);

+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);

+

+

+

+	COMPONENT altpll

+	GENERIC (

+		clk0_divide_by		: NATURAL;

+		clk0_duty_cycle		: NATURAL;

+		clk0_multiply_by		: NATURAL;

+		clk0_phase_shift		: STRING;

+		compensate_clock		: STRING;

+		gate_lock_signal		: STRING;

+		inclk0_input_frequency		: NATURAL;

+		intended_device_family		: STRING;

+		invalid_lock_multiplier		: NATURAL;

+		lpm_hint		: STRING;

+		lpm_type		: STRING;

+		operation_mode		: STRING;

+		port_activeclock		: STRING;

+		port_areset		: STRING;

+		port_clkbad0		: STRING;

+		port_clkbad1		: STRING;

+		port_clkloss		: STRING;

+		port_clkswitch		: STRING;

+		port_configupdate		: STRING;

+		port_fbin		: STRING;

+		port_inclk0		: STRING;

+		port_inclk1		: STRING;

+		port_locked		: STRING;

+		port_pfdena		: STRING;

+		port_phasecounterselect		: STRING;

+		port_phasedone		: STRING;

+		port_phasestep		: STRING;

+		port_phaseupdown		: STRING;

+		port_pllena		: STRING;

+		port_scanaclr		: STRING;

+		port_scanclk		: STRING;

+		port_scanclkena		: STRING;

+		port_scandata		: STRING;

+		port_scandataout		: STRING;

+		port_scandone		: STRING;

+		port_scanread		: STRING;

+		port_scanwrite		: STRING;

+		port_clk0		: STRING;

+		port_clk1		: STRING;

+		port_clk2		: STRING;

+		port_clk3		: STRING;

+		port_clk4		: STRING;

+		port_clk5		: STRING;

+		port_clkena0		: STRING;

+		port_clkena1		: STRING;

+		port_clkena2		: STRING;

+		port_clkena3		: STRING;

+		port_clkena4		: STRING;

+		port_clkena5		: STRING;

+		port_extclk0		: STRING;

+		port_extclk1		: STRING;

+		port_extclk2		: STRING;

+		port_extclk3		: STRING;

+		valid_lock_multiplier		: NATURAL

+	);

+	PORT (

+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);

+			locked	: OUT STD_LOGIC ;

+			areset	: IN STD_LOGIC ;

+			clk	: OUT STD_LOGIC_VECTOR (5 DOWNTO 0)

+	);

+	END COMPONENT;

+

+BEGIN

+	sub_wire5_bv(0 DOWNTO 0) <= "0";

+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);

+	sub_wire1    <= sub_wire0(0);

+	c0    <= sub_wire1;

+	locked    <= sub_wire2;

+	sub_wire3    <= inclk0;

+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;

+

+	altpll_component : altpll

+	GENERIC MAP (

+		clk0_divide_by => 2,

+		clk0_duty_cycle => 50,

+		clk0_multiply_by => 5,

+		clk0_phase_shift => "0",

+		compensate_clock => "CLK0",

+		gate_lock_signal => "NO",

+		inclk0_input_frequency => 41666,

+		intended_device_family => "Cyclone II",

+		invalid_lock_multiplier => 5,

+		lpm_hint => "CBX_MODULE_PREFIX=pllx2",

+		lpm_type => "altpll",

+		operation_mode => "NORMAL",

+		port_activeclock => "PORT_UNUSED",

+		port_areset => "PORT_USED",

+		port_clkbad0 => "PORT_UNUSED",

+		port_clkbad1 => "PORT_UNUSED",

+		port_clkloss => "PORT_UNUSED",

+		port_clkswitch => "PORT_UNUSED",

+		port_configupdate => "PORT_UNUSED",

+		port_fbin => "PORT_UNUSED",

+		port_inclk0 => "PORT_USED",

+		port_inclk1 => "PORT_UNUSED",

+		port_locked => "PORT_USED",

+		port_pfdena => "PORT_UNUSED",

+		port_phasecounterselect => "PORT_UNUSED",

+		port_phasedone => "PORT_UNUSED",

+		port_phasestep => "PORT_UNUSED",

+		port_phaseupdown => "PORT_UNUSED",

+		port_pllena => "PORT_UNUSED",

+		port_scanaclr => "PORT_UNUSED",

+		port_scanclk => "PORT_UNUSED",

+		port_scanclkena => "PORT_UNUSED",

+		port_scandata => "PORT_UNUSED",

+		port_scandataout => "PORT_UNUSED",

+		port_scandone => "PORT_UNUSED",

+		port_scanread => "PORT_UNUSED",

+		port_scanwrite => "PORT_UNUSED",

+		port_clk0 => "PORT_USED",

+		port_clk1 => "PORT_UNUSED",

+		port_clk2 => "PORT_UNUSED",

+		port_clk3 => "PORT_UNUSED",

+		port_clk4 => "PORT_UNUSED",

+		port_clk5 => "PORT_UNUSED",

+		port_clkena0 => "PORT_UNUSED",

+		port_clkena1 => "PORT_UNUSED",

+		port_clkena2 => "PORT_UNUSED",

+		port_clkena3 => "PORT_UNUSED",

+		port_clkena4 => "PORT_UNUSED",

+		port_clkena5 => "PORT_UNUSED",

+		port_extclk0 => "PORT_UNUSED",

+		port_extclk1 => "PORT_UNUSED",

+		port_extclk2 => "PORT_UNUSED",

+		port_extclk3 => "PORT_UNUSED",

+		valid_lock_multiplier => 1

+	)

+	PORT MAP (

+		inclk => sub_wire4,

+		areset => areset,

+		clk => sub_wire0,

+		locked => sub_wire2

+	);

+

+

+

+END SYN;

+

+-- ============================================================

+-- CNX file retrieval info

+-- ============================================================

+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"

+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"

+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"

+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"

+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"

+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"

+-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"

+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"

+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"

+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"

+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"

+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"

+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"

+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"

+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"

+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"

+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"

+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"

+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"

+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "32.000000"

+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"

+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"

+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"

+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"

+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"

+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"

+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"

+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "24.000"

+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"

+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"

+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"

+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"

+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"

+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"

+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"

+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"

+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"

+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "312.000"

+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"

+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"

+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"

+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"

+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"

+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"

+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "32.00000000"

+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"

+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"

+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"

+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"

+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"

+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"

+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"

+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"

+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"

+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"

+-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"

+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"

+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"

+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"

+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"

+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"

+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"

+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"

+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pllx2.mif"

+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"

+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"

+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"

+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"

+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"

+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"

+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"

+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"

+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"

+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"

+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"

+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"

+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"

+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"

+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"

+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"

+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"

+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"

+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all

+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"

+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"

+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"

+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"

+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"

+-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"

+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "41666"

+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"

+-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"

+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"

+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"

+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"

+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"

+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"

+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"

+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"

+-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"

+-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"

+-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"

+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"

+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"

+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"

+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"

+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"

+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0

+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0

+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0

+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0

+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0

+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllx2.vhd TRUE

+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllx2.ppf TRUE

+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllx2.inc FALSE

+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllx2.cmp FALSE

+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllx2.bsf FALSE

+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllx2_inst.vhd FALSE

+-- Retrieval info: LIB_FILE: altera_mf

+-- Retrieval info: CBX_MODULE_PREFIX: ON

diff --git a/sdram_ctrl.vhd b/sdram_ctrl.vhd
new file mode 100644
index 0000000..b0b4a1f
--- /dev/null
+++ b/sdram_ctrl.vhd
@@ -0,0 +1,615 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+library work;
+use work.sdram_util.ALL;
+
+-- a simple dram controller (no pipelineing)
+-- that looks like a slow static ram
+
+entity sdram_ctrl is
+  port
+  (  
+    clock_100  :  in std_logic;
+    reset_n    :  in std_logic;
+
+    bus_cs_n    :  in std_logic;
+    bus_rnw    :  in std_logic;
+
+    bus_wait_n  :  out std_logic;
+
+    bus_addr    :  in addr_t;
+    bus_data_in    :  in data_t;
+    bus_data_out    :  out data_t;
+
+    sdram_clk  :  out std_logic;
+    sdram_cke  :  out std_logic;
+
+    sdram_cs_n  :  out std_logic;
+
+    sdram_cas_n  :  out std_logic;
+    sdram_ras_n  :  out std_logic;
+    sdram_we_n  :  out std_logic;
+
+    sdram_addr  :  out std_logic_vector(12 downto 0);
+    sdram_ba  :  out std_logic_vector(1 downto 0);
+
+    sdram_dq  :  inout data_t;
+    sdram_dqm  :  out dqm_t;
+
+    debug : out std_logic_vector(7 downto 0)
+  );
+end entity;
+
+
+architecture rtl of sdram_ctrl is
+
+
+  signal clock : std_logic;
+
+
+  constant DEBUG_0 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#3F#,7));
+  constant DEBUG_1 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#06#,7));
+  constant DEBUG_2 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#5B#,7));
+  constant DEBUG_3 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#4F#,7));
+  constant DEBUG_4 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#66#,7));
+  constant DEBUG_5 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#6D#,7));
+  constant DEBUG_6 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#7D#,7));
+  constant DEBUG_7 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#07#,7));
+  constant DEBUG_8 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#7F#,7));
+  constant DEBUG_9 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#6F#,7));
+
+  -- bits in the MEM_CMD register RAS_N CAS_N WE_N
+
+  constant MEM_CMD_NOP : std_logic_vector(2 downto 0 ):="111";
+  constant MEM_CMD_READ : std_logic_vector(2 downto 0 ):="101";
+  constant MEM_CMD_WRIT : std_logic_vector(2 downto 0 ):="100";
+  constant MEM_CMD_ACTV : std_logic_vector(2 downto 0 ):="011";
+  constant MEM_CMD_PRE : std_logic_vector(2 downto 0 ):="010";
+  constant MEM_CMD_REF : std_logic_vector(2 downto 0 ):="001";
+  constant MEM_CMD_MRS : std_logic_vector(2 downto 0 ):="000";
+
+  constant MEM_CS_N_ALL : cs_n_t := "0";
+  constant MEM_CS_N_NONE : cs_n_t := "1";
+
+  -- refresh logic
+
+  signal need_refresh : std_logic;
+  signal refresh_counter : uint13_t;
+
+  -- init logic
+
+  signal init_done : std_logic;
+  signal      i_addr : std_logic_vector(12 downto 0);
+  signal      i_cs_n: cs_n_t;
+  signal      i_cmd : std_logic_vector(2 downto 0);
+  signal      i_count : uint4_t;
+  signal      i_next : uint3_t;
+  signal      i_refs : uint3_t;
+
+  -- debuging
+  signal      i_debug : std_logic_vector(6 downto 0);
+  signal      m_debug : std_logic_vector(7 downto 0);
+  signal      b_debug : std_logic_vector(7 downto 0);
+
+  -- init fsm
+  signal      i_state :uint3_t;
+
+  constant I_ST_RESET_WAIT : uint3_t:=0;
+  constant I_ST_PRECHARGE : uint3_t :=1;
+  constant I_ST_REFRESH : uint3_t :=2;
+  constant I_ST_WAIT_COUNT : uint3_t :=3;
+  constant I_ST_SET_MODE : uint3_t :=4;
+  constant I_ST_DONE : uint3_t :=5;
+
+  -- memory interface wires
+  signal mem_cs_n : cs_n_t;
+  signal mem_bank : std_logic_vector(1 downto 0);
+  signal mem_cmd : std_logic_vector(2 downto 0);
+  signal mem_addr : std_logic_vector(12 downto 0);
+  signal mem_data_out : data_t;
+  signal mem_data_in : data_t;
+  signal mem_dqm : dqm_t;
+  signal mem_oe: std_logic;
+
+  -- main logic
+  signal ack_refresh : std_logic;
+  signal ack_request : std_logic;
+  signal m_count: uint3_t; 
+
+  signal active_cs_n : cs_n_t;
+  signal active_addr : addr_t;
+  signal active_data : data_t;
+  signal active_rnw : std_logic;
+  signal active_dqm : dqm_t;
+
+  -- main fsm 
+  signal m_state : std_logic_vector(9 downto 0);
+  signal m_next : std_logic_vector(9 downto 0);
+
+  constant M_ST_WAITING_INIT       : std_logic_vector(9 downto 0 ):="0000000001";
+  constant M_ST_IDLE               : std_logic_vector(9 downto 0 ):="0000000010";
+  constant M_ST_RAS                : std_logic_vector(9 downto 0 ):="0000000100";
+  constant M_ST_NOP_COUNT          : std_logic_vector(9 downto 0 ):="0000001000";
+  constant M_ST_READ               : std_logic_vector(9 downto 0 ):="0000010000";
+  constant M_ST_WRITE              : std_logic_vector(9 downto 0 ):="0000100000";
+  constant M_ST_ACTIVE             : std_logic_vector(9 downto 0 ):="0001000000";
+  constant M_ST_WAIT_FOR_PRECHARGE : std_logic_vector(9 downto 0 ):="0010000000";
+  constant M_ST_PRECHARGE          : std_logic_vector(9 downto 0 ):="0100000000";
+  constant M_ST_REFRESH            : std_logic_vector(9 downto 0 ):="1000000000";
+
+
+  -- request logic
+  signal request_pending: std_logic;
+  signal request_cs_n : cs_n_t;
+  signal request_addr : addr_t;
+  signal request_data : data_t;
+  signal request_rnw : std_logic;
+  signal request_dqm : dqm_t;
+
+  -- read state logic
+  signal r_data_valid: std_logic_vector(3 downto 0);
+
+  -- bus logic
+  signal post_request: std_logic;
+
+  -- bus fsm
+  signal b_state : std_logic_vector(4 downto 0);
+
+  constant B_ST_WAIT_CS_N_LOW  : std_logic_vector(4 downto 0):="00001";
+  constant B_ST_LODGE_REQUEST  : std_logic_vector(4 downto 0):="00010";
+  constant B_ST_WAIT_ACK       : std_logic_vector(4 downto 0):="00100";
+  constant B_ST_WAIT_DATA      : std_logic_vector(4 downto 0):="01000";
+  constant B_ST_WAIT_CS_N_HIGH : std_logic_vector(4 downto 0):="10000";
+
+  -- convert boolean to active high logic 
+  function b2l_ah(constant val : in boolean) return std_logic is begin
+    if val then
+      return '1';
+    else
+      return '0';
+    end if;
+  end function; 
+
+
+  -- convert active high logic to boolean value
+  function l2b_ah(constant val : in std_logic) return boolean is begin
+    return val='1';
+  end function; 
+
+  function l2b_al(constant val : in std_logic) return boolean is begin
+    return val='0';
+  end function; 
+
+
+  function same_bank_and_row ( 	constant a1: in addr_t; constant a2: in addr_t ) return boolean is begin 
+    return a1(23 downto 9) = a2(23 downto 9); 
+  end function;
+
+begin
+
+  clock<=clock_100;
+
+  refresh_counter_process: process(reset_n,clock) begin
+    if l2b_al(reset_n) then
+      refresh_counter <= 8000;
+    elsif rising_edge(clock) then
+      if refresh_counter = 0 then
+	refresh_counter <= 624;
+      else
+	refresh_counter <= refresh_counter - 1;  
+      end if;
+    end if; 
+  end process;
+
+
+  need_refresh_process: process(reset_n,clock,refresh_counter,need_refresh,init_done,ack_refresh) begin
+    if l2b_al(reset_n)  then
+      need_refresh <= '0';
+    elsif rising_edge(clock) then
+      need_refresh <= (b2l_ah(refresh_counter = 0) or need_refresh) and init_done and not ack_refresh;
+    end if;
+  end process;
+
+  request_pending_process: process(reset_n, clock, post_request, request_pending,ack_request,refresh_counter) begin
+    if l2b_al(reset_n)  then
+      request_pending <= '0';
+    elsif rising_edge(clock) then
+      --request_pending <= post_request or (request_pending and not b2l_ah(refresh_counter = 0 ));
+      request_pending <= post_request or (request_pending and not ack_request);
+    end if;
+  end process;
+ 
+
+  init_done_process: process (reset_n,clock,i_state)  begin
+    if l2b_al(reset_n) then 
+      init_done <= '0';
+    elsif rising_edge(clock) then
+      init_done <= init_done or b2l_ah(i_state = I_ST_DONE );
+    end if;
+  end process;
+
+  init_fsm: process (reset_n,clock,i_state,i_count,i_next,refresh_counter) begin
+    if l2b_al(reset_n) then
+      i_state <= I_ST_RESET_WAIT;
+      i_next <= I_ST_RESET_WAIT;
+      i_cs_n <=MEM_CS_N_NONE;
+      i_cmd <= MEM_CMD_NOP;
+      i_addr <= (others => '1');
+      i_count <= 0;
+      i_debug <= DEBUG_0;
+    elsif rising_edge(clock) then
+
+      if i_state = I_ST_RESET_WAIT then
+        i_debug <= DEBUG_1;
+      -- after reset wait until the refresh_counter ticks over for RAM to stabalize
+	i_cs_n <=MEM_CS_N_NONE;
+	i_cmd <= MEM_CMD_NOP;
+	i_refs <= 0;
+	if refresh_counter=0 then
+	  i_state <= I_ST_PRECHARGE;
+	end if;
+      elsif i_state = I_ST_PRECHARGE then
+        i_debug <= DEBUG_2;
+      -- precharge all banks, wait one clock, then go to refresh
+	i_cs_n <=MEM_CS_N_ALL;
+	i_cmd <=MEM_CMD_PRE;
+	i_state <= I_ST_WAIT_COUNT;
+	i_count <= 1;
+	i_next <= I_ST_REFRESH;
+      elsif i_state =I_ST_REFRESH then
+        i_debug <= DEBUG_3;
+      -- repeat 7 times { refresh, wait 5 counts }
+	i_cs_n <=MEM_CS_N_ALL;
+	i_cmd <=MEM_CMD_REF;
+	i_refs <= i_refs + 1;
+
+	i_state <= I_ST_WAIT_COUNT;
+	i_count <= 5;
+
+	if i_refs = 7 then
+	  i_next <= I_ST_SET_MODE;
+	else
+	  i_next <= I_ST_REFRESH;
+	end if;
+      elsif i_state = I_ST_WAIT_COUNT then
+        i_debug <= DEBUG_4;
+      -- wait i_count ticks then goto state i_next
+	i_cs_n <=MEM_CS_N_ALL;
+	i_cmd <= MEM_CMD_NOP;
+	if (i_count > 1) then
+	  i_count <= i_count -1;
+	else
+	  i_state <= i_next;
+	end if;
+
+      elsif i_state=I_ST_SET_MODE then
+        i_debug <= DEBUG_5;
+      -- set mode, wait 3 ticks then goto done
+	i_cs_n <=MEM_CS_N_ALL;
+	i_cmd <= MEM_CMD_MRS;
+
+      -- reserverd      000
+      -- opcode burst read/write  0
+      -- reserved       00
+      -- cas latency 3    011
+      -- sequential burst    0
+      -- burst length 1     000
+
+	i_addr <= "0000000110000";
+	i_count <= 3;
+	i_next <= I_ST_DONE;
+	i_state <= I_ST_WAIT_COUNT;
+
+      elsif i_state=I_ST_DONE then
+        i_debug <= DEBUG_6;
+	i_state <= I_ST_DONE;
+      else
+	i_state <= I_ST_RESET_WAIT;      
+      end if;
+    end if;
+  end process;
+
+  main_fsm: process (reset_n,clock,m_state,need_refresh,request_pending,request_addr,request_data,request_cs_n,request_rnw,request_dqm,i_debug) begin
+
+    if reset_n ='0' then
+      m_state <= M_ST_WAITING_INIT;
+      m_next <= M_ST_WAITING_INIT;
+      mem_cmd  <= MEM_CMD_NOP;
+      mem_cs_n <= MEM_CS_N_NONE;
+      mem_bank <= (others => '0');
+      mem_addr <= (others => '0');
+      mem_data_out <= (others => '0');
+      mem_dqm <= (others => '0');
+      m_count <= 0;
+      ack_refresh <= '0';
+      ack_request <= '0';
+      mem_oe <= '0';
+      m_debug(6 downto 0) <=(others =>'0');
+      m_debug(7) <='1';
+    elsif rising_edge(clock) then
+      if m_state =M_ST_WAITING_INIT then
+      	m_debug(6 downto 0) <= i_debug;
+        m_debug(7) <='1';
+	mem_addr <= i_addr;
+	mem_cmd <= i_cmd;
+	mem_cs_n <= i_cs_n;
+
+	if l2b_ah(init_done) then
+	  m_state <= M_ST_IDLE;
+	end if;
+      elsif m_state = M_ST_IDLE then
+      	m_debug(6 downto 0) <= DEBUG_1;
+        m_debug(7) <='0';
+	mem_cmd <= MEM_CMD_NOP;
+
+	ack_refresh <='0';
+
+	if l2b_ah(need_refresh) then
+	    -- If we got here needing a refresh
+	    -- we may have come straight from a 
+	    -- read so leave CS on so we get
+	    -- that data
+
+	  mem_cs_n<=MEM_CS_N_ALL;
+
+	    -- precharge everyone (putting back 
+	    -- the open row if we did come from a read
+	    -- or write) then refresh everyone.
+
+	  m_state <= M_ST_PRECHARGE;
+	  m_next <= M_ST_REFRESH;
+	else 
+	  -- idle to all chips (MEM_CMD_IGN)
+	  mem_cs_n<=MEM_CS_N_NONE; 
+
+	  -- find out if anyone wants us 
+	  if l2b_ah(request_pending) then
+	    active_cs_n <= request_cs_n;
+	    active_rnw <= request_rnw;
+	    active_addr <= request_addr;
+	    active_data <= request_data;
+	    active_dqm <= request_dqm;
+	    m_state <= M_ST_RAS;
+	    ack_request <='1';
+	  end if;
+	end if;
+      elsif m_state = M_ST_RAS then
+      	m_debug(6 downto 0) <= DEBUG_2;
+	  -- activate the relevant ROW, wait 3 clocks, then go and do the read or write
+
+	ack_request <='0';
+
+	mem_cs_n <= active_cs_n;
+	mem_cmd  <= MEM_CMD_ACTV;
+	mem_bank(1) <= active_addr(23);
+	mem_bank(0) <= active_addr(9);
+	mem_addr <= active_addr(22 downto 10);
+	mem_data_out <= active_data;
+	mem_dqm  <= active_dqm;
+
+	m_state <= M_ST_NOP_COUNT;
+	m_count <= 2; --t  3 clocks : FIXME
+	if l2b_ah(active_rnw) then
+	  m_next <= M_ST_READ;
+	else
+	  m_next <= M_ST_WRITE;
+	end if;
+      elsif m_state = M_ST_NOP_COUNT then
+      	m_debug(6 downto 0) <= DEBUG_3;
+	  -- send nops for m_count, then go to state m_next
+	mem_cmd <=MEM_CMD_NOP;
+	if m_count > 1 then
+	  m_count <= m_count - 1;
+	else
+	  m_state <= m_next;
+	end if;
+      elsif m_state = M_ST_READ then
+      	m_debug(6 downto 0) <= DEBUG_4;
+	ack_request <='0';
+
+	mem_cmd <=MEM_CMD_READ;
+
+	mem_addr(12 downto 9) <= (others => '0');
+	mem_addr(8 downto 0) <= active_addr(8 downto 0);
+
+	m_state <= M_ST_ACTIVE;
+      elsif m_state = M_ST_WRITE then
+      	m_debug(6 downto 0) <= DEBUG_5;
+	ack_request <='0';
+
+	mem_cmd<=MEM_CMD_WRIT;
+
+	mem_addr(12 downto 9) <= (others => '0');
+	mem_addr(8 downto 0) <= active_addr(8 downto 0);
+
+	mem_oe <= '1';
+	mem_data_out <= active_data;
+
+	m_state <=M_ST_ACTIVE;
+      elsif m_state = M_ST_ACTIVE then
+      	m_debug(6 downto 0) <= DEBUG_6;
+	  -- turn off drivers (we might have come from a write)
+	mem_oe <= '0';
+
+	  -- sit doing NOPS on this row until either we get a new request
+	  -- or we need a refresh
+	mem_cmd <= MEM_CMD_NOP;
+
+	if l2b_ah(need_refresh) then
+	    -- the refresh will first precharge everything, so no need to precharge
+	    -- just this row. 
+	  m_state <= M_ST_NOP_COUNT;
+	  m_next <= M_ST_IDLE;
+	  m_count <= 1;
+	elsif l2b_ah(request_pending) then
+	  if (active_cs_n = request_cs_n) and (active_rnw = request_rnw) and same_bank_and_row(active_addr,request_addr) then
+	      -- this request matches our currently active row
+	      -- we can process it 
+
+	    active_addr <= request_addr;
+	    active_data <= request_data;
+	    active_dqm <= request_dqm;
+
+	    ack_request <='1';
+
+	    if l2b_ah(request_rnw) then
+	      m_state <= M_ST_READ;
+	    else
+	      m_state <= M_ST_WRITE;
+	    end if;
+	  else
+	      -- new request doesn't match, precharge and go to idle
+	    m_state <= M_ST_WAIT_FOR_PRECHARGE;
+	    m_next <= M_ST_IDLE;
+	  end if;
+	end if;
+
+      elsif m_state = M_ST_WAIT_FOR_PRECHARGE then
+      	m_debug(6 downto 0) <= DEBUG_7;
+	  -- wait count then do a precharge
+	mem_cmd <= MEM_CMD_NOP;
+	if m_count > 1 then
+	  m_count <= m_count -1;
+	else
+	  m_state<=M_ST_PRECHARGE;
+	end if;
+      elsif m_state = M_ST_PRECHARGE then
+      	m_debug(6 downto 0) <= DEBUG_8;
+	-- do a precharge, wait two clocks, then goto m_next
+	mem_addr <= (others => '1');
+	mem_cmd <= MEM_CMD_PRE;
+	m_count <= 1;
+	m_state <= M_ST_NOP_COUNT;
+      elsif m_state=M_ST_REFRESH then
+      	m_debug(6 downto 0) <= DEBUG_9;
+	-- do a refresh, wait six clocks, return to idle
+
+	mem_cmd <= MEM_CMD_REF;
+	m_count <=5;
+	m_next <=M_ST_IDLE;
+	m_state <= M_ST_NOP_COUNT;
+
+	-- tell the gubbins we did the refresh
+	ack_refresh <= '1';
+      else  
+	-- shouldn't be here - crash
+        m_debug(7) <='1';
+      	m_debug(6 downto 0) <= DEBUG_9;
+	mem_cmd <=MEM_CMD_NOP;
+	mem_cs_n <= MEM_CS_N_NONE;
+	mem_oe <= '0';
+      end if;
+    end if;
+
+  end process;
+
+  -- drive the memory lines
+  sdram_clk <= clock;
+  sdram_cke <= '1';
+  sdram_cs_n  <= mem_cs_n(0);
+  sdram_ras_n <= mem_cmd(2);
+  sdram_cas_n <= mem_cmd(1);
+  sdram_we_n  <= mem_cmd(0);
+  sdram_addr  <= mem_addr;
+  sdram_ba    <= mem_bank;
+
+  sdram_dq_tristate: process(mem_oe,mem_data_out)  begin
+  if l2b_ah(mem_oe) then
+	sdram_dq <= mem_data_out;
+  else
+	sdram_dq <= (others => 'Z' );
+  end if;
+  end process;
+
+  mem_data_in <= sdram_dq;
+
+  sdram_dqm <= mem_dqm;
+
+  -- a shift register to track the reads
+  read_process: process(reset_n,clock, mem_cmd) begin
+    if l2b_al(reset_n) then
+	r_data_valid <= (others => '0');
+    elsif rising_edge(clock) then
+	r_data_valid(2 downto 0)<=r_data_valid(3 downto 1);
+	r_data_valid(3) <= b2l_ah(mem_cmd = MEM_CMD_READ);
+    end if;
+  end process;
+	
+
+  bus_fsm: process (reset_n,clock,b_state,bus_cs_n,bus_rnw,bus_addr,bus_data_in,ack_request,r_data_valid) begin
+    if l2b_al(reset_n) then
+	bus_data_out <= (others => '0');
+	request_data <= (others => '0');
+	request_addr <= (others => '0');
+	request_rnw <= '0';
+  	request_cs_n <= MEM_CS_N_NONE;
+  	request_dqm <= "00";
+	b_state <= B_ST_WAIT_CS_N_LOW;
+	b_debug(6 downto 0) <= DEBUG_0;
+	b_debug(7) <='0';
+	bus_wait_n <= '0';
+   elsif rising_edge(clock) then
+	if b_state = B_ST_WAIT_CS_N_LOW then
+		b_debug(6 downto 0) <= DEBUG_1;
+		bus_wait_n <= '0';
+		if l2b_al(bus_cs_n) then
+			-- new request ship it to the main state machine
+			post_request <='1';
+			request_addr <= bus_addr;
+			request_rnw <= bus_rnw;
+			request_data <= bus_data_in;
+
+			-- send to first chip and all bytes
+  			request_cs_n <= "0"; -- (others => '1');
+  			request_dqm <= "00";
+
+			b_state <= B_ST_LODGE_REQUEST;
+		end if;
+	elsif b_state =B_ST_LODGE_REQUEST then
+	b_debug(6 downto 0) <= DEBUG_2;
+		post_request <='0';
+		b_state <= B_ST_WAIT_ACK;
+	elsif b_state =B_ST_WAIT_ACK then
+	b_debug(6 downto 0) <= DEBUG_3;
+		if not l2b_ah(request_pending) then
+			-- the logic has pushed the request to the ram
+			if l2b_al(request_rnw) then
+				-- if it's a write we're all done
+				b_state <= B_ST_WAIT_CS_N_HIGH;
+			else
+				-- if it's a read we have to wait for the data
+				b_state <= B_ST_WAIT_DATA;
+			end if;
+		end if;
+	elsif b_state = B_ST_WAIT_DATA then
+		b_debug(6 downto 0) <= DEBUG_4;
+		if l2b_ah(r_data_valid(0)) then
+			bus_data_out <= mem_data_in;
+--			bus_data_out <= request_addr(15 downto 0);
+			b_state <= B_ST_WAIT_CS_N_HIGH;
+		end if;
+	elsif b_state = B_ST_WAIT_CS_N_HIGH then
+	b_debug(6 downto 0) <= DEBUG_5;
+	b_debug(7) <='1';
+			bus_wait_n <= '1'; 
+		if not l2b_al(bus_cs_n) then
+			b_state <=B_ST_WAIT_CS_N_LOW;
+		end if;
+	else
+		b_state <=B_ST_WAIT_CS_N_LOW;
+	end if;
+ end if;
+
+   end process;
+--   debug <=b_debug;
+    debug <= m_debug;
+
+
+end;
+
+
+
+
+
diff --git a/sdram_test.qpf b/sdram_test.qpf
new file mode 100644
index 0000000..9ad2991
--- /dev/null
+++ b/sdram_test.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #

+#

+# Copyright (C) 1991-2012 Altera Corporation

+# Your use of Altera Corporation's design tools, logic functions 

+# and other software and tools, and its AMPP partner logic 

+# functions, and any output files from any of the foregoing 

+# (including device programming or simulation files), and any 

+# associated documentation or information are expressly subject 

+# to the terms and conditions of the Altera Program License 

+# Subscription Agreement, Altera MegaCore Function License 

+# Agreement, or other applicable license agreement, including, 

+# without limitation, that your use is for the sole purpose of 

+# programming logic devices manufactured by Altera and sold by 

+# Altera or its authorized distributors.  Please refer to the 

+# applicable agreement for further details.

+#

+# -------------------------------------------------------------------------- #

+#

+# Quartus II 32-bit

+# Version 12.0 Build 178 05/31/2012 SJ Web Edition

+# Date created = 21:48:38  September 12, 2013

+#

+# -------------------------------------------------------------------------- #

+

+QUARTUS_VERSION = "12.0"

+DATE = "21:48:38  September 12, 2013"

+

+# Revisions

+

+PROJECT_REVISION = "sdram_test"

diff --git a/sdram_test.qsf b/sdram_test.qsf
new file mode 100644
index 0000000..a90ba5d
--- /dev/null
+++ b/sdram_test.qsf
@@ -0,0 +1,154 @@
+# -------------------------------------------------------------------------- #

+#

+# Copyright (C) 1991-2012 Altera Corporation

+# Your use of Altera Corporation's design tools, logic functions 

+# and other software and tools, and its AMPP partner logic 

+# functions, and any output files from any of the foregoing 

+# (including device programming or simulation files), and any 

+# associated documentation or information are expressly subject 

+# to the terms and conditions of the Altera Program License 

+# Subscription Agreement, Altera MegaCore Function License 

+# Agreement, or other applicable license agreement, including, 

+# without limitation, that your use is for the sole purpose of 

+# programming logic devices manufactured by Altera and sold by 

+# Altera or its authorized distributors.  Please refer to the 

+# applicable agreement for further details.

+#

+# -------------------------------------------------------------------------- #

+#

+# Quartus II 32-bit

+# Version 12.0 Build 178 05/31/2012 SJ Web Edition

+# Date created = 21:48:38  September 12, 2013

+#

+# -------------------------------------------------------------------------- #

+#

+# Notes:

+#

+# 1) The default values for assignments are stored in the file:

+#		sdram.qdf

+#    If this file doesn't exist, see file:

+#		assignment_defaults.qdf

+#

+# 2) Altera recommends that you do not modify this file. This

+#    file is updated automatically by the Quartus II software

+#    and any changes you make may be lost or overwritten.

+#

+# -------------------------------------------------------------------------- #

+

+

+set_global_assignment -name FAMILY "Cyclone II"
+set_global_assignment -name DEVICE EP2C8Q208C8
+set_global_assignment -name TOP_LEVEL_ENTITY sdram_test

+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:48:38  SEPTEMBER 12, 2013"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 208
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_location_assignment PIN_41 -to seven_seg[7]
+set_location_assignment PIN_40 -to seven_seg[6]
+set_location_assignment PIN_37 -to seven_seg[5]
+set_location_assignment PIN_43 -to seven_seg[4]
+set_location_assignment PIN_44 -to seven_seg[3]
+set_location_assignment PIN_39 -to seven_seg[2]
+set_location_assignment PIN_35 -to seven_seg[1]
+set_location_assignment PIN_34 -to seven_seg[0]
+set_location_assignment PIN_23 -to clock_50
+set_location_assignment PIN_27 -to reset_n
+set_location_assignment PIN_92 -to sdram_addr[12]
+set_location_assignment PIN_90 -to sdram_addr[11]
+set_location_assignment PIN_75 -to sdram_addr[10]
+set_location_assignment PIN_89 -to sdram_addr[9]
+set_location_assignment PIN_88 -to sdram_addr[8]
+set_location_assignment PIN_87 -to sdram_addr[7]
+set_location_assignment PIN_86 -to sdram_addr[6]
+set_location_assignment PIN_84 -to sdram_addr[5]
+set_location_assignment PIN_82 -to sdram_addr[4]
+set_location_assignment PIN_81 -to sdram_addr[3]
+set_location_assignment PIN_80 -to sdram_addr[2]
+set_location_assignment PIN_77 -to sdram_addr[1]
+set_location_assignment PIN_76 -to sdram_addr[0]
+set_location_assignment PIN_74 -to sdram_ba[1]
+set_location_assignment PIN_72 -to sdram_ba[0]
+set_location_assignment PIN_69 -to sdram_cas_n
+set_location_assignment PIN_46 -to sdram_cke
+set_location_assignment PIN_47 -to sdram_clk
+set_location_assignment PIN_45 -to sdram_cs_n
+set_location_assignment PIN_94 -to sdram_dq[15]
+set_location_assignment PIN_95 -to sdram_dq[14]
+set_location_assignment PIN_96 -to sdram_dq[13]
+set_location_assignment PIN_97 -to sdram_dq[12]
+set_location_assignment PIN_99 -to sdram_dq[11]
+set_location_assignment PIN_101 -to sdram_dq[10]
+set_location_assignment PIN_102 -to sdram_dq[9]
+set_location_assignment PIN_103 -to sdram_dq[8]
+set_location_assignment PIN_57 -to sdram_dq[7]
+set_location_assignment PIN_58 -to sdram_dq[6]
+set_location_assignment PIN_59 -to sdram_dq[5]
+set_location_assignment PIN_60 -to sdram_dq[4]
+set_location_assignment PIN_61 -to sdram_dq[3]
+set_location_assignment PIN_63 -to sdram_dq[2]
+set_location_assignment PIN_64 -to sdram_dq[1]
+set_location_assignment PIN_67 -to sdram_dq[0]
+set_location_assignment PIN_104 -to sdram_dqm[1]
+set_location_assignment PIN_56 -to sdram_dqm[0]
+set_location_assignment PIN_70 -to sdram_ras_n
+set_location_assignment PIN_68 -to sdram_we_n
+set_location_assignment PIN_41 -to seg[7]
+set_location_assignment PIN_160 -to dm9000_cmd
+set_location_assignment PIN_165 -to dm9000_cs_n
+set_location_assignment PIN_144 -to dm9000_data[15]
+set_location_assignment PIN_145 -to dm9000_data[14]
+set_location_assignment PIN_146 -to dm9000_data[13]
+set_location_assignment PIN_147 -to dm9000_data[12]
+set_location_assignment PIN_149 -to dm9000_data[11]
+set_location_assignment PIN_150 -to dm9000_data[10]
+set_location_assignment PIN_151 -to dm9000_data[9]
+set_location_assignment PIN_152 -to dm9000_data[8]
+set_location_assignment PIN_135 -to dm9000_data[7]
+set_location_assignment PIN_134 -to dm9000_data[6]
+set_location_assignment PIN_138 -to dm9000_data[5]
+set_location_assignment PIN_137 -to dm9000_data[4]
+set_location_assignment PIN_141 -to dm9000_data[3]
+set_location_assignment PIN_139 -to dm9000_data[2]
+set_location_assignment PIN_143 -to dm9000_data[1]
+set_location_assignment PIN_142 -to dm9000_data[0]
+set_location_assignment PIN_162 -to dm9000_rd_n
+set_location_assignment PIN_163 -to dm9000_wr_n
+set_location_assignment PIN_164 -to dm9000_rst_n
+set_location_assignment PIN_161 -to dm9000_int
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name SEARCH_PATH sdram_test_mcu/synthesis/ -tag from_archive
+set_global_assignment -name SEARCH_PATH sdram_test_mcu/synthesis/submodules/ -tag from_archive
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_location_assignment PIN_108 -to vga_red[0]
+set_location_assignment PIN_113 -to vga_red[1]
+set_location_assignment PIN_112 -to vga_red[2]
+set_location_assignment PIN_128 -to vga_hs
+set_location_assignment PIN_115 -to vga_green[0]
+set_location_assignment PIN_114 -to vga_green[1]
+set_location_assignment PIN_117 -to vga_green[2]
+set_location_assignment PIN_116 -to vga_blue[0]
+set_location_assignment PIN_127 -to vga_blue[1]
+set_location_assignment PIN_118 -to vga_blue[2]
+set_location_assignment PIN_133 -to vga_vs
+
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+
+set_global_assignment -name PIN_FILE sdram_test.pin
+set_global_assignment -name VHDL_FILE sdram_test.vhd
+set_global_assignment -name VHDL_FILE sdram_util.vhd
+set_global_assignment -name VHDL_FILE sdram_ctrl.vhd
+set_global_assignment -name VHDL_FILE pllx2.vhd
+set_global_assignment -name QSYS_FILE sdram_test_mcu.qsys
+
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
diff --git a/sdram_test.vhd b/sdram_test.vhd
new file mode 100644
index 0000000..156ca28
--- /dev/null
+++ b/sdram_test.vhd
@@ -0,0 +1,177 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+library work;
+use work.sdram_util.ALL;
+
+entity sdram is
+port (
+	clock_50	:	in	std_logic;	
+	reset_n		:	in	std_logic;
+	seven_seg	:	out 	std_logic_vector(7 downto 0);
+
+	sdram_clk	:	out std_logic;
+
+	sdram_cs_n	:	out std_logic;
+	sdram_cas_n	:	out std_logic;
+	sdram_ras_n	:	out std_logic;
+	sdram_we_n	:	out std_logic;
+	sdram_cke	:	out std_logic;
+
+	sdram_addr	:	out std_logic_vector(12 downto 0);
+	sdram_ba	:	out std_logic_vector(1 downto 0);
+
+	sdram_dq	:	inout std_logic_vector(15 downto 0);
+	sdram_dqm	:	out std_logic_vector(1 downto 0)
+);
+end entity;
+
+architecture rtl of sdram is
+
+component pllx2 IS
+        PORT
+        (
+                areset          : IN STD_LOGIC  := '0';
+                inclk0          : IN STD_LOGIC  := '0';
+                c0              : OUT STD_LOGIC ;
+                locked          : OUT STD_LOGIC
+        );
+end component;
+
+
+
+component sdram_test_mcu is
+	port (
+		clk_clk		: in    std_logic                     := 'X';             -- clk
+		reset_reset_n	: in    std_logic                     := 'X';             -- reset_n
+		pio_0_d_export	: out   std_logic_vector(7 downto 0);                     -- export
+		sbb_0_reset_n	: out   std_logic                                        -- reset_n
+		sbb_0_cs_n	: out   std_logic;                                        -- cs_n
+		sbb_0_rnw	: out   std_logic;                                        -- rnw
+		sbb_0_wait_n	: in    std_logic                     := 'X';             -- wait_n
+		sbb_0_addr	: out   std_logic_vector(15 downto 0);                    -- addr
+		sbb_0_data_in	: in    std_logic_vector(15 downto 0)  := (others => 'X'); -- data_in
+		sbb_0_data_out	: out   std_logic_vector(15 downto 0);                     -- data_out
+	);
+end component sdram_mcu;
+
+component sdram_ctrl is
+  port
+  (  
+    clock_100  :  in std_logic;
+    reset_n    :  in std_logic;
+
+    bus_cs_n    :  in std_logic;
+    bus_rnw    :  in std_logic;
+
+    bus_wait_n  :  out std_logic;
+
+    bus_addr    :  in addr_t;
+    bus_data_in    :  in data_t;
+    bus_data_out    :  out data_t;
+
+    sdram_clk  :  out std_logic;
+    sdram_cke  :  out std_logic;
+
+    sdram_cs_n  :  out std_logic;
+
+    sdram_cas_n  :  out std_logic;
+    sdram_ras_n  :  out std_logic;
+    sdram_we_n  :  out std_logic;
+
+    sdram_addr  :  out std_logic_vector(12 downto 0);
+    sdram_ba  :  out std_logic_vector(1 downto 0);
+
+    sdram_dq  :  inout data_t;
+    sdram_dqm  :  out dqm_t;
+
+    debug  :  out std_logic_vector(7 downto 0)
+  );
+end component;
+
+signal b_data_in8 : std_logic_vector(7 downto 0);
+signal b_data_out8 : std_logic_vector(7 downto 0);
+signal b_addr16: std_logic_vector(15 downto 0);
+
+signal b_addr : addr_t;
+signal b_data_in : data_t;
+signal b_data_out : data_t;
+signal b_cs_n : std_logic;
+signal b_rnw : std_logic;
+signal b_wait_n : std_logic;
+
+signal pll_reset : std_logic;
+signal mcu_clock : std_logic;
+signal clock_100 : std_logic;
+signal pll_locked : std_logic;
+signal debug : std_logic_vector(7 downto 0);
+
+signal global_reset_n : std_logic;
+signal b_reset_n : std_logic;
+
+signal buf8 : std_logic_vector(7 downto 0);
+
+
+begin
+
+        pll:   pllx2 port map (
+                pll_reset,
+                clock_50,
+                clock_100,
+                pll_locked );
+
+	mcu_clock <= clock_50;
+
+   	u0 : component sdram_mcu port map (
+		clk_clk        => mcu_clock,        --     clk.clk
+		reset_reset_n  => global_reset_n,  --   reset.reset_n
+		pio_0_d_export => seven_seg, -- pio_0_d.export
+		sbb_0_reset_n   => b_reset_n  
+		sbb_0_cs_n      => b_cs_n,      --    ebb_0.cs_n
+		sbb_0_rnw       => b_rnw,      --        .rnw
+		sbb_0_wait_n    => b_wait_n,    --        .wait_n
+		sbb_0_addr      => b_addr16,      --        .addr
+		sbb_0_data_in   => b_data_in,   --        .data
+		sbb_0_data_out  => b_data_out,   --        .data
+	);
+
+ 	-- bodge buses together
+
+	b_addr(15 downto 0) <= b_addr16;
+	b_addr(23 downto 16) <= (others => '0');
+
+	sdram_ctrl0: sdram_ctrl port map (
+		clock_100 => clock_50,
+		reset_n => b_reset_n,
+
+		bus_cs_n => b_cs_n,
+		bus_rnw => b_rnw,
+
+		bus_wait_n => b_wait_n,
+
+		bus_addr => b_addr,
+		bus_data_in => b_data_in,
+		bus_data_out => b_data_out,
+
+		sdram_clk => sdram_clk,
+		sdram_cke => sdram_cke,
+
+		sdram_cs_n => sdram_cs_n,
+		sdram_cas_n => sdram_cas_n,
+		sdram_ras_n => sdram_ras_n,
+		sdram_we_n => sdram_we_n,
+
+		sdram_addr => sdram_addr,
+		sdram_ba => sdram_ba,
+
+		sdram_dq => sdram_dq,
+		sdram_dqm => sdram_dqm,
+
+		debug => debug
+	);
+
+	pll_reset <= '0';
+	global_reset_n <= reset_n and pll_locked;
+	
+end architecture;
diff --git a/sdram_test_mcu.qsys b/sdram_test_mcu.qsys
new file mode 100644
index 0000000..c0cba01
--- /dev/null
+++ b/sdram_test_mcu.qsys
@@ -0,0 +1,543 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element $${FILENAME}
+   {
+   }
+   element async_16bit_bus_adapter_0
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+   }
+   element jtag_uart_0.avalon_jtag_slave
+   {
+      datum baseAddress
+      {
+         value = "270432";
+         type = "String";
+      }
+   }
+   element async_16bit_bus_adapter_0.avalon_slave
+   {
+      datum baseAddress
+      {
+         value = "131072";
+         type = "String";
+      }
+   }
+   element clk_0
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+   element epcs_flash_controller_0.epcs_control_port
+   {
+      datum baseAddress
+      {
+         value = "266240";
+         type = "String";
+      }
+   }
+   element epcs_flash_controller_0
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+      datum megawizard_uipreferences
+      {
+         value = "{}";
+         type = "String";
+      }
+   }
+   element nios2_qsys_0.jtag_debug_module
+   {
+      datum baseAddress
+      {
+         value = "268288";
+         type = "String";
+      }
+   }
+   element jtag_uart_0
+   {
+      datum _sortIndex
+      {
+         value = "5";
+         type = "int";
+      }
+   }
+   element nios2_qsys_0
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+   }
+   element pio_0
+   {
+      datum _sortIndex
+      {
+         value = "4";
+         type = "int";
+      }
+   }
+   element timer_0.s1
+   {
+      datum baseAddress
+      {
+         value = "270368";
+         type = "String";
+      }
+   }
+   element pio_0.s1
+   {
+      datum baseAddress
+      {
+         value = "270416";
+         type = "String";
+      }
+   }
+   element timer_0
+   {
+      datum _sortIndex
+      {
+         value = "3";
+         type = "int";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="EP2C8Q208C8" />
+ <parameter name="deviceFamily" value="Cyclone II" />
+ <parameter name="deviceSpeedGrade" value="8" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="sdram_test.qpf" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="1" />
+ <parameter name="timeStamp" value="1381776549910" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
+ <interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
+ <interface
+   name="pio_0_d"
+   internal="pio_0.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sbb_0"
+   internal="async_16bit_bus_adapter_0.sbb"
+   type="conduit"
+   dir="end" />
+ <module kind="clock_source" version="13.0" enabled="1" name="clk_0">
+  <parameter name="clockFrequency" value="80000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="0" />
+  <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module
+   kind="altera_nios2_qsys"
+   version="13.0"
+   enabled="1"
+   name="nios2_qsys_0">
+  <parameter name="setting_showUnpublishedSettings" value="false" />
+  <parameter name="setting_showInternalSettings" value="false" />
+  <parameter name="setting_preciseSlaveAccessErrorException" value="false" />
+  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+  <parameter name="setting_preciseDivisionErrorException" value="false" />
+  <parameter name="setting_performanceCounter" value="false" />
+  <parameter name="setting_illegalMemAccessDetection" value="false" />
+  <parameter name="setting_illegalInstructionsTrap" value="false" />
+  <parameter name="setting_fullWaveformSignals" value="false" />
+  <parameter name="setting_extraExceptionInfo" value="false" />
+  <parameter name="setting_exportPCB" value="false" />
+  <parameter name="setting_debugSimGen" value="false" />
+  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+  <parameter name="setting_bit31BypassDCache" value="true" />
+  <parameter name="setting_bigEndian" value="false" />
+  <parameter name="setting_export_large_RAMs" value="false" />
+  <parameter name="setting_asic_enabled" value="false" />
+  <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
+  <parameter name="setting_oci_export_jtag_signals" value="false" />
+  <parameter name="setting_bhtIndexPcOnly" value="false" />
+  <parameter name="setting_avalonDebugPortPresent" value="false" />
+  <parameter name="setting_alwaysEncrypt" value="true" />
+  <parameter name="setting_allowFullAddressRange" value="false" />
+  <parameter name="setting_activateTrace" value="true" />
+  <parameter name="setting_activateTestEndChecker" value="false" />
+  <parameter name="setting_activateMonitors" value="true" />
+  <parameter name="setting_activateModelChecker" value="false" />
+  <parameter name="setting_HDLSimCachesCleared" value="true" />
+  <parameter name="setting_HBreakTest" value="false" />
+  <parameter name="muldiv_divider" value="false" />
+  <parameter name="mpu_useLimit" value="false" />
+  <parameter name="mpu_enabled" value="false" />
+  <parameter name="mmu_enabled" value="false" />
+  <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
+  <parameter name="manuallyAssignCpuID" value="true" />
+  <parameter name="debug_triggerArming" value="true" />
+  <parameter name="debug_embeddedPLL" value="true" />
+  <parameter name="debug_debugReqSignals" value="false" />
+  <parameter name="debug_assignJtagInstanceID" value="false" />
+  <parameter name="dcache_omitDataMaster" value="false" />
+  <parameter name="cpuReset" value="false" />
+  <parameter name="is_hardcopy_compatible" value="false" />
+  <parameter name="setting_shadowRegisterSets" value="0" />
+  <parameter name="mpu_numOfInstRegion" value="8" />
+  <parameter name="mpu_numOfDataRegion" value="8" />
+  <parameter name="mmu_TLBMissExcOffset" value="0" />
+  <parameter name="debug_jtagInstanceID" value="0" />
+  <parameter name="resetOffset" value="0" />
+  <parameter name="exceptionOffset" value="32" />
+  <parameter name="cpuID" value="0" />
+  <parameter name="cpuID_stored" value="0" />
+  <parameter name="breakOffset" value="32" />
+  <parameter name="userDefinedSettings" value="" />
+  <parameter name="resetSlave">async_16bit_bus_adapter_0.avalon_slave</parameter>
+  <parameter name="mmu_TLBMissExcSlave" value="" />
+  <parameter name="exceptionSlave">async_16bit_bus_adapter_0.avalon_slave</parameter>
+  <parameter name="breakSlave">nios2_qsys_0.jtag_debug_module</parameter>
+  <parameter name="setting_perfCounterWidth" value="32" />
+  <parameter name="setting_interruptControllerType" value="Internal" />
+  <parameter name="setting_branchPredictionType" value="Automatic" />
+  <parameter name="setting_bhtPtrSz" value="8" />
+  <parameter name="muldiv_multiplierType" value="EmbeddedMulFast" />
+  <parameter name="mpu_minInstRegionSize" value="12" />
+  <parameter name="mpu_minDataRegionSize" value="12" />
+  <parameter name="mmu_uitlbNumEntries" value="4" />
+  <parameter name="mmu_udtlbNumEntries" value="6" />
+  <parameter name="mmu_tlbPtrSz" value="7" />
+  <parameter name="mmu_tlbNumWays" value="16" />
+  <parameter name="mmu_processIDNumBits" value="8" />
+  <parameter name="impl" value="Tiny" />
+  <parameter name="icache_size" value="2048" />
+  <parameter name="icache_tagramBlockType" value="Automatic" />
+  <parameter name="icache_ramBlockType" value="Automatic" />
+  <parameter name="icache_numTCIM" value="0" />
+  <parameter name="icache_burstType" value="None" />
+  <parameter name="dcache_bursts" value="false" />
+  <parameter name="dcache_victim_buf_impl" value="ram" />
+  <parameter name="debug_level" value="Level1" />
+  <parameter name="debug_OCIOnchipTrace" value="_128" />
+  <parameter name="dcache_size" value="1024" />
+  <parameter name="dcache_tagramBlockType" value="Automatic" />
+  <parameter name="dcache_ramBlockType" value="Automatic" />
+  <parameter name="dcache_numTCDM" value="0" />
+  <parameter name="dcache_lineSize" value="32" />
+  <parameter name="setting_exportvectors" value="false" />
+  <parameter name="setting_ecc_present" value="false" />
+  <parameter name="regfile_ramBlockType" value="Automatic" />
+  <parameter name="ocimem_ramBlockType" value="Automatic" />
+  <parameter name="mmu_ramBlockType" value="Automatic" />
+  <parameter name="bht_ramBlockType" value="Automatic" />
+  <parameter name="instAddrWidth" value="19" />
+  <parameter name="dataAddrWidth" value="19" />
+  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='async_16bit_bus_adapter_0.avalon_slave' start='0x20000' end='0x40000' /><slave name='epcs_flash_controller_0.epcs_control_port' start='0x41000' end='0x41800' /><slave name='nios2_qsys_0.jtag_debug_module' start='0x41800' end='0x42000' /><slave name='timer_0.s1' start='0x42020' end='0x42040' /><slave name='pio_0.s1' start='0x42050' end='0x42060' /></address-map>]]></parameter>
+  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='async_16bit_bus_adapter_0.avalon_slave' start='0x20000' end='0x40000' /><slave name='epcs_flash_controller_0.epcs_control_port' start='0x41000' end='0x41800' /><slave name='nios2_qsys_0.jtag_debug_module' start='0x41800' end='0x42000' /><slave name='timer_0.s1' start='0x42020' end='0x42040' /><slave name='pio_0.s1' start='0x42050' end='0x42060' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x42060' end='0x42068' /></address-map>]]></parameter>
+  <parameter name="clockFrequency" value="80000000" />
+  <parameter name="deviceFamilyName" value="Cyclone II" />
+  <parameter name="internalIrqMaskSystemInfo" value="7" />
+  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
+  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 0 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 1 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 0 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 1 HAS_JITTER_SUPPORT 0 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 1 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 0 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 0 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 1 HAS_SPLIT_IO_SUPPORT 0 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 0 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 1 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 1 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 1 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 0 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 1 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 1 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 0 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 0 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 0 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 0 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
+  <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+ </module>
+ <module
+   kind="altera_avalon_epcs_flash_controller"
+   version="13.0.1.99.2"
+   enabled="1"
+   name="epcs_flash_controller_0">
+  <parameter name="autoSelectASMIAtom" value="true" />
+  <parameter name="useASMIAtom" value="true" />
+  <parameter name="clockRate" value="80000000" />
+  <parameter name="deviceFamilyString" value="Cyclone II" />
+  <parameter name="autoInitializationFileName">$${FILENAME}_epcs_flash_controller_0</parameter>
+ </module>
+ <module
+   kind="altera_avalon_timer"
+   version="13.0.1.99.2"
+   enabled="1"
+   name="timer_0">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="systemFrequency" value="80000000" />
+ </module>
+ <module
+   kind="altera_avalon_pio"
+   version="13.0.1.99.2"
+   enabled="1"
+   name="pio_0">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="8" />
+  <parameter name="clockRate" value="80000000" />
+ </module>
+ <module
+   kind="altera_avalon_jtag_uart"
+   version="13.0.1.99.2"
+   enabled="1"
+   name="jtag_uart_0">
+  <parameter name="allowMultipleConnections" value="false" />
+  <parameter name="hubInstanceID" value="0" />
+  <parameter name="readBufferDepth" value="64" />
+  <parameter name="readIRQThreshold" value="8" />
+  <parameter name="simInputCharacterStream" value="" />
+  <parameter name="simInteractiveOptions">INTERACTIVE_ASCII_OUTPUT</parameter>
+  <parameter name="useRegistersForReadBuffer" value="false" />
+  <parameter name="useRegistersForWriteBuffer" value="false" />
+  <parameter name="useRelativePathForSimFile" value="false" />
+  <parameter name="writeBufferDepth" value="64" />
+  <parameter name="writeIRQThreshold" value="8" />
+  <parameter name="avalonSpec" value="2.0" />
+ </module>
+ <module
+   kind="async_16bit_bus_adapter"
+   version="1.0"
+   enabled="1"
+   name="async_16bit_bus_adapter_0">
+  <parameter name="AUTO_CLOCK_CLOCK_RATE" value="-1" />
+  <parameter name="AUTO_CLOCK_CLOCK_RATE_1" value="80000000" />
+ </module>
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="nios2_qsys_0.instruction_master"
+   end="nios2_qsys_0.jtag_debug_module">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00041800" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="nios2_qsys_0.data_master"
+   end="nios2_qsys_0.jtag_debug_module">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00041800" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_0.clk_reset"
+   end="nios2_qsys_0.reset_n" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="nios2_qsys_0.jtag_debug_module_reset"
+   end="nios2_qsys_0.reset_n" />
+ <connection kind="clock" version="13.0" start="clk_0.clk" end="nios2_qsys_0.clk" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_0.clk_reset"
+   end="epcs_flash_controller_0.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="nios2_qsys_0.jtag_debug_module_reset"
+   end="epcs_flash_controller_0.reset" />
+ <connection
+   kind="clock"
+   version="13.0"
+   start="clk_0.clk"
+   end="epcs_flash_controller_0.clk" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="nios2_qsys_0.instruction_master"
+   end="epcs_flash_controller_0.epcs_control_port">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00041000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="nios2_qsys_0.data_master"
+   end="epcs_flash_controller_0.epcs_control_port">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00041000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="13.0" start="clk_0.clk" end="timer_0.clk" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_0.clk_reset"
+   end="timer_0.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="nios2_qsys_0.jtag_debug_module_reset"
+   end="timer_0.reset" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="nios2_qsys_0.data_master"
+   end="timer_0.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00042020" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="nios2_qsys_0.instruction_master"
+   end="timer_0.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00042020" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="13.0" start="clk_0.clk" end="pio_0.clk" />
+ <connection kind="reset" version="13.0" start="clk_0.clk_reset" end="pio_0.reset" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="nios2_qsys_0.data_master"
+   end="pio_0.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00042050" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="nios2_qsys_0.instruction_master"
+   end="pio_0.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00042050" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="reset"
+   version="13.0"
+   start="nios2_qsys_0.jtag_debug_module_reset"
+   end="pio_0.reset" />
+ <connection kind="clock" version="13.0" start="clk_0.clk" end="jtag_uart_0.clk" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="nios2_qsys_0.jtag_debug_module_reset"
+   end="jtag_uart_0.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_0.clk_reset"
+   end="jtag_uart_0.reset" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="nios2_qsys_0.data_master"
+   end="jtag_uart_0.avalon_jtag_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00042060" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="13.0"
+   start="nios2_qsys_0.d_irq"
+   end="epcs_flash_controller_0.irq">
+  <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="13.0"
+   start="nios2_qsys_0.d_irq"
+   end="timer_0.irq">
+  <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="13.0"
+   start="nios2_qsys_0.d_irq"
+   end="jtag_uart_0.irq">
+  <parameter name="irqNumber" value="2" />
+ </connection>
+ <connection
+   kind="clock"
+   version="13.0"
+   start="clk_0.clk"
+   end="async_16bit_bus_adapter_0.clock" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_0.clk_reset"
+   end="async_16bit_bus_adapter_0.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="nios2_qsys_0.jtag_debug_module_reset"
+   end="async_16bit_bus_adapter_0.reset" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="nios2_qsys_0.instruction_master"
+   end="async_16bit_bus_adapter_0.avalon_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00020000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="nios2_qsys_0.data_master"
+   end="async_16bit_bus_adapter_0.avalon_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00020000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/sdram_util.vhd b/sdram_util.vhd
new file mode 100644
index 0000000..7dfcb47
--- /dev/null
+++ b/sdram_util.vhd
@@ -0,0 +1,50 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+package sdram_util is
+
+subtype uint3_t is integer range 0 to 7;
+subtype uint4_t is integer range 0 to 15;
+subtype uint8_t is integer range 0 to 255;
+subtype uint13_t is integer range 0 to 8191;
+subtype cs_n_t is std_logic_vector(0 downto 0);
+subtype addr_t is std_logic_vector(23 downto 0);
+subtype data_t is std_logic_vector(15 downto 0);
+subtype dqm_t is std_logic_vector(1 downto 0);
+
+
+  function b2l_ah(constant val : in boolean) return std_logic;
+  function l2b_ah(constant val : in std_logic) return boolean;
+  function l2b_al(constant val : in std_logic) return boolean;
+
+end package;
+
+
+package body sdram_util is 
+
+  -- convert boolean to active high logic 
+  function b2l_ah(constant val : in boolean) return std_logic is begin
+    if val then
+      return '1';
+    else
+      return '0';
+    end if;
+  end function; 
+
+
+  -- convert active high logic to boolean value
+  function l2b_ah(constant val : in std_logic) return boolean is begin
+    return val='1';
+  end function; 
+
+  function l2b_al(constant val : in std_logic) return boolean is begin
+    return val='0';
+  end function; 
+
+end package body;
+
+
+
+
+
diff --git a/src/sdram_test.c b/src/sdram_test.c
new file mode 100644
index 0000000..ba1be8d
--- /dev/null
+++ b/src/sdram_test.c
@@ -0,0 +1,56 @@
+#include <io.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdint.h>
+#include "system.h"
+
+
+#define msleep(msec) usleep(1000*msec);
+
+pio_write (unsigned int data)
+{
+  IOWR (PIO_0_BASE, 0, data);
+}
+
+static void
+show (int v)
+{
+  // int to seven segment lookup: MSB dp g f e d c b a LSB
+  const uint8_t lookup[10] =
+    { 0x3F, 0x6, 0x5B, 0x4F, 0x66, 0x6D, 0x7D, 0x7, 0x7F, 0x6F };
+
+  uint8_t pio = 0;
+
+  // show negative with DP
+  if (v < 0)
+    {
+      pio |= 0x80;
+      v = -v;
+    }
+
+  if (v > 9)
+    v = 9;
+
+  pio |= lookup[v];
+
+  pio_write (pio);
+}
+
+
+
+int
+main (void)
+{
+  int i;
+  printf ("Working...\n");
+  for (;;) {
+  for (i=-9;i<10;++i) {
+	printf("Showing %d\n",i);
+	show(i);
+	msleep(1000);
+  }
+ }
+	
+}
diff --git a/tools/wrap b/tools/wrap
new file mode 100755
index 0000000..26a0640
--- /dev/null
+++ b/tools/wrap
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+AD=/software/apps/altera/quartus_ii_13.0sp1
+if [ $(uname -m ) == "x86_64" ]; then
+	LL=linux64
+else
+	LL=linux
+fi
+QUARTUS_ROOTDIR="${AD}/quartus"
+PATH="${AD}/quartus/bin:${AD}/quartus/sopc_builder/bin:${AD}/nios2eds/sdk2/bin:${AD}/nios2eds/bin:${AD}/nios2eds/bin/gnu/H-i686-pc-linux-gnu/bin:${PATH}"
+LD_LIBRARY_PATH="${AD}/quartus/${LL}:${LD_LIBRARY_PATH}"
+
+export LD_LIBRARY_PATH PATH QUARTUS_ROOTDIR
+
+"$@"