diff options
| -rw-r--r-- | .gitignore | 1 | ||||
| -rw-r--r-- | async_8bit_bus_adapter_hw/async_8bit_bus_adapter.v | 44 | ||||
| -rw-r--r-- | async_8bit_bus_adapter_hw/async_8bit_bus_adapter.vhd | 53 | ||||
| -rw-r--r-- | async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl | 9 | ||||
| -rw-r--r-- | async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ | 14 | ||||
| -rw-r--r-- | async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd | 56 | ||||
| -rw-r--r-- | sdram.qsf | 1 | ||||
| -rw-r--r-- | sdram.vhd | 68 | ||||
| -rw-r--r-- | sdram_ctrl.vhd | 41 | ||||
| -rw-r--r-- | sdram_mcu.qsys | 32 | ||||
| -rw-r--r-- | sdram_util.vhd | 49 |
11 files changed, 193 insertions, 175 deletions
@@ -30,3 +30,4 @@ src/obj sdram_mcu/ sdram_mcu.cmp sdram_mcu.html +*.smsg diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.v b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.v deleted file mode 100644 index bfd69c3..0000000 --- a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.v +++ /dev/null @@ -1,44 +0,0 @@ -// async_8bit_bus_adapter.v - -// This file was auto-generated as a prototype implementation of a module -// created in component editor. It ties off all outputs to ground and -// ignores all inputs. It needs to be edited to make it do something -// useful. -// -// This file will not be automatically regenerated. You should check it in -// to your version control system if you want to keep it. - -`timescale 1 ps / 1 ps -module async_8bit_bus_adapter #( - parameter AUTO_CLOCK_CLOCK_RATE = "-1" - ) ( - input wire clk, // clock.clk - input wire rst_n, // reset.reset_n - input wire cs_n, // avalon_slave.chipselect_n - input wire [15:0] address, // .address - input wire [7:0] writedata, // .writedata - input wire wr_n, // .write_n - input wire rd_n, // .read_n - output wire wait_n, // .waitrequest_n - output wire [7:0] readdata, // .readdata - output wire b_cs_n, // eight_bit_bus.export - output wire b_rd_n, // .export - output wire b_wr_n, // .export - input wire b_wait_n, // .export - output wire [15:0] b_addr, // .export - inout wire [7:0] b_data // .export - ); - - // TODO: Auto-generated HDL template - - assign readdata = 8'b00000000; - - assign b_cs_n = 1'b0; - - assign b_wr_n = 1'b0; - - assign b_rd_n = 1'b0; - - assign b_addr = 16'b0000000000000000; - -endmodule diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.vhd b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.vhd deleted file mode 100644 index 5983f63..0000000 --- a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.vhd +++ /dev/null @@ -1,53 +0,0 @@ --- async_8bit_bus_adapter.vhd - --- This file was auto-generated as a prototype implementation of a module --- created in component editor. It ties off all outputs to ground and --- ignores all inputs. It needs to be edited to make it do something --- useful. --- --- This file will not be automatically regenerated. You should check it in --- to your version control system if you want to keep it. - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity async_8bit_bus_adapter is - generic ( - AUTO_CLOCK_CLOCK_RATE : string := "-1" - ); - port ( - clk : in std_logic := '0'; -- clock.clk - rst_n : in std_logic := '0'; -- reset.reset_n - cs_n : in std_logic := '0'; -- avalon_slave.chipselect_n - address : in std_logic_vector(15 downto 0) := (others => '0'); -- .address - writedata : in std_logic_vector(7 downto 0) := (others => '0'); -- .writedata - wr_n : in std_logic := '0'; -- .write_n - rd_n : in std_logic := '0'; -- .read_n - wait_n : out std_logic; -- .waitrequest_n - readdata : out std_logic_vector(7 downto 0); -- .readdata - b_cs_n : out std_logic; -- eight_bit_bus.export - b_rd_n : out std_logic; -- .export - b_wr_n : out std_logic; -- .export - b_wait_n : in std_logic := '0'; -- .export - b_addr : out std_logic; -- .export - b_data : inout std_logic := '0' -- .export - ); -end entity async_8bit_bus_adapter; - -architecture rtl of async_8bit_bus_adapter is -begin - - -- TODO: Auto-generated HDL template - - readdata <= "00000000"; - - b_cs_n <= '0'; - - b_wr_n <= '0'; - - b_rd_n <= '0'; - - b_addr <= '0'; - -end architecture rtl; -- of async_8bit_bus_adapter diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl index d4f8021..d4b4688 100644 --- a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl +++ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 13.0sp1 -# Sun Oct 13 12:34:21 BST 2013 +# Mon Oct 14 15:03:03 BST 2013 # DO NOT MODIFY # # async_8bit_bus_adapter "async_8bit_bus_adapter" v1.0 -# 2013.10.13.12:34:21 +# 2013.10.14.15:03:03 # # @@ -39,7 +39,7 @@ set_module_property ALLOW_GREYBOX_GENERATION false add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" set_fileset_property QUARTUS_SYNTH TOP_LEVEL async_8bit_bus_adapter set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false -add_fileset_file async_8bit_bus_adapter.v VERILOG PATH async_8bit_bus_adapter.v TOP_LEVEL_FILE +add_fileset_file async_8bit_bus_adapter.vhd VHDL PATH hdl/async_8bit_bus_adapter.vhd TOP_LEVEL_FILE add_fileset SIM_VHDL SIM_VHDL "" "" set_fileset_property SIM_VHDL TOP_LEVEL async_8bit_bus_adapter @@ -137,5 +137,6 @@ add_interface_port eight_bit_bus b_rd_n export Output 1 add_interface_port eight_bit_bus b_wr_n export Output 1 add_interface_port eight_bit_bus b_wait_n export Input 1 add_interface_port eight_bit_bus b_addr export Output 16 -add_interface_port eight_bit_bus b_data export Bidir 8 +add_interface_port eight_bit_bus b_data_in export Input 8 +add_interface_port eight_bit_bus b_data_out export Output 8 diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ index bd77527..5171d01 100644 --- a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ +++ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 13.0sp1 -# Sun Oct 13 12:34:12 BST 2013 +# Mon Oct 14 15:01:25 BST 2013 # DO NOT MODIFY # # async_8bit_bus_adapter "async_8bit_bus_adapter" v1.0 -# 2013.10.13.12:34:12 +# 2013.10.14.15:01:25 # # @@ -26,7 +26,7 @@ set_module_property OPAQUE_ADDRESS_MAP true set_module_property GROUP my_lib set_module_property AUTHOR "" set_module_property DISPLAY_NAME async_8bit_bus_adapter -set_module_property INSTANTIATE_IN_SYSTEM_MODULE false +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true set_module_property EDITABLE true set_module_property ANALYZE_HDL AUTO set_module_property REPORT_TO_TALKBACK false @@ -36,6 +36,11 @@ set_module_property ALLOW_GREYBOX_GENERATION false # # file sets # +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL async_8bit_bus_adapter +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +add_fileset_file async_8bit_bus_adapter.vhd VHDL PATH hdl/async_8bit_bus_adapter.vhd TOP_LEVEL_FILE + add_fileset SIM_VHDL SIM_VHDL "" "" set_fileset_property SIM_VHDL TOP_LEVEL async_8bit_bus_adapter set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false @@ -132,5 +137,6 @@ add_interface_port eight_bit_bus b_rd_n export Output 1 add_interface_port eight_bit_bus b_wr_n export Output 1 add_interface_port eight_bit_bus b_wait_n export Input 1 add_interface_port eight_bit_bus b_addr export Output 16 -add_interface_port eight_bit_bus b_data export Bidir 8 +add_interface_port eight_bit_bus b_data_in export Input 8 +add_interface_port eight_bit_bus b_data_out export Output 8 diff --git a/async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd b/async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd new file mode 100644 index 0000000..29e4ff3 --- /dev/null +++ b/async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd @@ -0,0 +1,56 @@ +-- async_8bit_bus_adapter.vhd + +-- This file was auto-generated as a prototype implementation of a module +-- created in component editor. It ties off all outputs to ground and +-- ignores all inputs. It needs to be edited to make it do something +-- useful. +-- +-- This file will not be automatically regenerated. You should check it in +-- to your version control system if you want to keep it. + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity async_8bit_bus_adapter is + generic ( + AUTO_CLOCK_CLOCK_RATE : string := "-1" + ); + port ( + clk : in std_logic := '0'; -- clock.clk + rst_n : in std_logic := '0'; -- reset.reset_n + cs_n : in std_logic := '0'; -- avalon_slave.chipselect_n + address : in std_logic_vector(15 downto 0) := (others => '0'); -- .address + writedata : in std_logic_vector(7 downto 0) := (others => '0'); -- .writedata + wr_n : in std_logic := '0'; -- .write_n + rd_n : in std_logic := '0'; -- .read_n + wait_n : out std_logic; -- .waitrequest_n + readdata : out std_logic_vector(7 downto 0); -- .readdata + b_cs_n : out std_logic; -- eight_bit_bus.export + b_rd_n : out std_logic; -- .export + b_wr_n : out std_logic; -- .export + b_wait_n : in std_logic := '0'; -- .export + b_addr : out std_logic_vector(15 downto 0); -- .export + b_data_in : in std_logic_vector(7 downto 0) := (others => '0'); -- .export + b_data_out : out std_logic_vector(7 downto 0) -- .export + ); +end entity async_8bit_bus_adapter; + +architecture rtl of async_8bit_bus_adapter is +begin + + -- TODO: Auto-generated HDL template + + readdata <= "00000000"; + + b_cs_n <= '0'; + + b_wr_n <= '0'; + + b_rd_n <= '0'; + + b_data_out <= "00000000"; + + b_addr <= "0000000000000000"; + +end architecture rtl; -- of async_8bit_bus_adapter @@ -145,6 +145,7 @@ set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name PIN_FILE sdram.pin set_global_assignment -name VHDL_FILE sdram.vhd +set_global_assignment -name VHDL_FILE sdram_util.vhd set_global_assignment -name VHDL_FILE sdram_ctrl.vhd set_global_assignment -name QSYS_FILE sdram_mcu.qsys @@ -2,6 +2,9 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; +library work; +use work.sdram_util.ALL; + entity sdram is port ( clock_50 : in std_logic; @@ -53,43 +56,43 @@ component sdram_mcu is end component sdram_mcu; -component sdram_ctrl is - port - ( - clock_50 : in std_logic; - reset_n : in std_logic; +entity sdram_ctrl is + port + ( + clock_100 : in std_logic; + reset_n : in std_logic; - b_cs_n : in std_logic; - b_rd_n : in std_logic; - b_wr_n : in std_logic; + bus_cs_n : in std_logic; + bus_rnw : in std_logic; - b_wait_n : out std_logic; + bus_wait_n : out std_logic; - b_addr : in std_logic_vector(15 downto 0); - b_data : inout std_logic_vector(7 downto 0); + bus_addr : in addr_t; + bus_data_in : in data_t; + bus_data_out : out data_t; + sdram_clk : out std_logic; + sdram_cke : out std_logic; - sdram_clk : out std_logic; + sdram_cs_n : out std_logic; - sdram_cs_n : out std_logic; - sdram_cas_n : out std_logic; - sdram_ras_n : out std_logic; - sdram_we_n : out std_logic; - sdram_cke : out std_logic; + sdram_cas_n : out std_logic; + sdram_ras_n : out std_logic; + sdram_we_n : out std_logic; - sdram_addr : out std_logic_vector(12 downto 0); - sdram_ba : out std_logic_vector(1 downto 0); + sdram_addr : out std_logic_vector(12 downto 0); + sdram_ba : out std_logic_vector(1 downto 0); - sdram_dq : inout std_logic_vector(15 downto 0); - sdram_dqm : out std_logic_vector(1 downto 0) - ); -end component; + sdram_dq : inout data_t; + sdram_dqm : out dqm_t + ); +end entity; -signal b_addr : std_logic_vector(15 downto 0); -signal b_data : std_logic_vector(7 downto 0); + +signal b_addr : addr_t; +signal b_data : data_t; signal b_cs_n : std_logic; -signal b_rd_n : std_logic; -signal b_wr_n : std_logic; +signal b_rnw : std_logic; signal b_wait_n : std_logic; signal pll_reset : std_logic; @@ -121,25 +124,26 @@ begin sdram_ctrl0: sdram_ctrl port map ( - clock_50, + clock_100, global_reset_n, b_cs_n, - b_rd_n, - b_wr_n, + b_rnw, b_wait_n, + sdram_cke, b_addr, - b_data, + b_data_in, + b_data_out, sdram_clk, + sdram_cke, sdram_cs_n, sdram_cas_n, sdram_ras_n, sdram_we_n, - sdram_cke, sdram_addr, sdram_ba, diff --git a/sdram_ctrl.vhd b/sdram_ctrl.vhd index b89ece5..d41b1b6 100644 --- a/sdram_ctrl.vhd +++ b/sdram_ctrl.vhd @@ -2,18 +2,12 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; +library work; +use work.sdram_util.ALL; + -- a simple dram controller (no pipelineing) -- that looks like a slow static ram -subtype uint3_t is integer range 0 to 7; -subtype uint4_t is integer range 0 to 15; -subtype uint13_t is integer range 0 to 8191; -subtype cs_n_t is std_logic_vector(0 downto 0); -subtype addr_t is std_logic_vector(23 downto 0); -subtype data_t is std_logic_vector(15 downto 0); -subtype dqm_t is std_logic_vector(1 downto 0); - - entity sdram_ctrl is port ( @@ -21,13 +15,13 @@ entity sdram_ctrl is reset_n : in std_logic; bus_cs_n : in std_logic; - bus_rd_n : in std_logic; - bus_wr_n : in std_logic; + bus_rnw : in std_logic; bus_wait_n : out std_logic; bus_addr : in addr_t; - bus_data : inout data_t; + bus_data_in : in data_t; + bus_data_out : out data_t; sdram_clk : out std_logic; sdram_cke : out std_logic; @@ -42,13 +36,14 @@ entity sdram_ctrl is sdram_ba : out std_logic_vector(1 downto 0); sdram_dq : inout data_t; - sdram_dqm : out dqm_t; + sdram_dqm : out dqm_t ); end entity; architecture rtl of sdram_ctrl is + signal clock : std_logic; -- bits in the MEM_CMD register RAS_N CAS_N WE_N @@ -138,16 +133,16 @@ architecture rtl of sdram_ctrl is signal r_data_valid: std_logic_vector(2 downto 0); -- bus logic - signal request_post: std_logic; + signal post_request: std_logic; -- bus fsm signal b_state : std_logic_vector(4 downto 0); - constant B_ST_WAIT_CS_LOW : std_logic_vector(4 downto 0):="00001"; + constant B_ST_WAIT_CS_N_LOW : std_logic_vector(4 downto 0):="00001"; constant B_ST_LODGE_REQUEST : std_logic_vector(4 downto 0):="00010"; constant B_ST_WAIT_ACK : std_logic_vector(4 downto 0):="00100"; constant B_ST_WAIT_DATA : std_logic_vector(4 downto 0):="01000"; - constant B_ST_WAIT_CS_HIGH : std_logic_vector(4 downto 0):="10000"; + constant B_ST_WAIT_CS_N_HIGH : std_logic_vector(4 downto 0):="10000"; -- convert boolean to active high logic function b2l_ah(constant val : in boolean) return std_logic is begin @@ -476,11 +471,14 @@ begin sdram_addr <= mem_addr; sdram_ba <= mem_bank; + sdram_dq_tristate: process(mem_oe,mem_data_out) begin if l2b_ah(mem_oe) then sdram_dq <= mem_data_out; else sdram_dq <= (others => 'Z' ); end if; + end process; + mem_data_in <= sdram_dq; sdram_dqm <= mem_dqm; @@ -490,20 +488,19 @@ begin if l2b_al(reset_n) then r_data_valid <= (others => '0'); elsif rising_edge(clock) then - r_data_valid(1 downto 0)=r_data_valid(2 downto 1); + r_data_valid(1 downto 0)<=r_data_valid(2 downto 1); r_data_valid(2) <= b2l_ah(mem_cmd = MEM_CMD_READ); end if; end process; - bus: process (reset_n,clock,b_state,bus_cs_n,bus_rnw,bus_addr,bus_data,ack_request,r_data_valid) begin + bus_fsm: process (reset_n,clock,b_state,bus_cs_n,bus_rnw,bus_addr,bus_data_in,ack_request,r_data_valid) begin if l2b_al(reset_n) then - request_pending <= '0'; bus_data_out <= (others => '0'); request_data <= (others => '0'); request_addr <= (others => '0'); request_rnw <= '0'; - request_cs_n <= CS_N_NONE; + request_cs_n <= MEM_CS_N_NONE; request_dqm <= "00"; b_state <= B_ST_WAIT_CS_N_LOW; elsif rising_edge(clock) then @@ -517,7 +514,7 @@ begin request_rnw <= '0'; -- send to first chip and all bytes - request_cs_n <= "0" (others => '1'); + request_cs_n <= "0"; -- (others => '1'); request_dqm <= "00"; bus_wait_n <= '0'; @@ -544,7 +541,7 @@ begin bus_wait_n <= '1'; b_state <= B_ST_WAIT_CS_N_HIGH; end if; - elsif b_state = B_ST_WAIT_CS_N_HIGH: + elsif b_state = B_ST_WAIT_CS_N_HIGH then if not l2b_al(bus_cs_n) then b_state <=B_ST_WAIT_CS_N_LOW; end if; diff --git a/sdram_mcu.qsys b/sdram_mcu.qsys index 5f8c178..f2d8f4e 100644 --- a/sdram_mcu.qsys +++ b/sdram_mcu.qsys @@ -105,27 +105,27 @@ type = "int"; } } - element pio_0.s1 + element onchip_memory2_0.s1 { datum baseAddress { - value = "172112"; + value = "147456"; type = "String"; } } - element timer_0.s1 + element pio_0.s1 { datum baseAddress { - value = "172064"; + value = "172112"; type = "String"; } } - element onchip_memory2_0.s1 + element timer_0.s1 { datum baseAddress { - value = "147456"; + value = "172064"; type = "String"; } } @@ -152,7 +152,7 @@ <parameter name="projectName" value="sdram.qpf" /> <parameter name="sopcBorderPoints" value="false" /> <parameter name="systemHash" value="1" /> - <parameter name="timeStamp" value="1381666549691" /> + <parameter name="timeStamp" value="1381759077868" /> <parameter name="useTestBenchNamingPattern" value="false" /> <instanceScript></instanceScript> <interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" /> @@ -580,6 +580,15 @@ <parameter name="defaultConnection" value="false" /> </connection> <connection + kind="avalon" + version="13.0" + start="nios2_qsys_0.instruction_master" + end="jtag_uart_0.avalon_jtag_slave"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0002a060" /> + <parameter name="defaultConnection" value="false" /> + </connection> + <connection kind="clock" version="13.0" start="clk_0.clk" @@ -612,15 +621,6 @@ <parameter name="baseAddress" value="0x00010000" /> <parameter name="defaultConnection" value="false" /> </connection> - <connection - kind="avalon" - version="13.0" - start="nios2_qsys_0.instruction_master" - end="jtag_uart_0.avalon_jtag_slave"> - <parameter name="arbitrationPriority" value="1" /> - <parameter name="baseAddress" value="0x0002a060" /> - <parameter name="defaultConnection" value="false" /> - </connection> <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" /> </system> diff --git a/sdram_util.vhd b/sdram_util.vhd new file mode 100644 index 0000000..23c1d1e --- /dev/null +++ b/sdram_util.vhd @@ -0,0 +1,49 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +package sdram_util is + +subtype uint3_t is integer range 0 to 7; +subtype uint4_t is integer range 0 to 15; +subtype uint13_t is integer range 0 to 8191; +subtype cs_n_t is std_logic_vector(0 downto 0); +subtype addr_t is std_logic_vector(23 downto 0); +subtype data_t is std_logic_vector(15 downto 0); +subtype dqm_t is std_logic_vector(1 downto 0); + + + function b2l_ah(constant val : in boolean) return std_logic; + function l2b_ah(constant val : in std_logic) return boolean; + function l2b_al(constant val : in std_logic) return boolean; + +end package; + + +package body sdram_util is + + -- convert boolean to active high logic + function b2l_ah(constant val : in boolean) return std_logic is begin + if val then + return '1'; + else + return '0'; + end if; + end function; + + + -- convert active high logic to boolean value + function l2b_ah(constant val : in std_logic) return boolean is begin + return val='1'; + end function; + + function l2b_al(constant val : in std_logic) return boolean is begin + return val='0'; + end function; + +end package body; + + + + + |