fish

1 files changed, 13 insertions, 5 deletions

diff --git a/sdram.vhd b/sdram.vhd
index f899f17..557d3b0 100644
--- a/sdram.vhd
+++ b/sdram.vhd
@@ -90,7 +90,10 @@ end entity;
 
 
 signal b_addr : addr_t;
-signal b_data : data_t;
+signal b_data_in8 : std_logic_vector(7 downto 0);
+signal b_data_in : data_t;
+signal b_data_out8 : std_logic_vector(7 downto 0);
+signal b_data_out : data_t;
 signal b_cs_n : std_logic;
 signal b_rnw : std_logic;
 signal b_wait_n : std_logic;
@@ -111,17 +114,22 @@ begin
                 pll_locked );
 
    	u0 : component sdram_mcu port map (
-		clk_clk        => clock_50,        --     clk.clk
+		clk_clk        => clock_100,        --     clk.clk
 		reset_reset_n  => global_reset_n,  --   reset.reset_n
 		pio_0_d_export => seven_seg, -- pio_0_d.export
 		ebb_0_cs_n      => b_cs_n,      --    ebb_0.cs_n
-		ebb_0_rd_n      => b_rd_n,      --        .rd_n
-		ebb_0_wr_n      => b_wr_n,      --        .wr_n
+		ebb_0_rnw       => b_rnw,      --        .rnw
 		ebb_0_wait_n    => b_wait_n,    --        .wait_n
 		ebb_0_addr      => b_addr,      --        .addr
-		ebb_0_data      => b_data       --        .data
+		ebb_0_data_in   => b_data_in8   --        .data
+		ebb_0_data_out  => b_data_out8   --        .data
 	);
 
+ 	b_data_in(7 downto 0)  <= b_data_in8;
+	b_data_in(15 downto 8) <= (others => '0');
+
+ 	b_data_out8  <= b_data_out(7 downto 0);
+
 
 	sdram_ctrl0: sdram_ctrl port map (
 		clock_100,