800x600

1 files changed, 112 insertions, 112 deletions

diff --git a/pong3.v b/pong3.v
index 0ad6803..1f5f68e 100644
--- a/pong3.v
+++ b/pong3.v
@@ -1,112 +1,112 @@
-module pong3(

-		clk,

-		rst_n,

-		

-		sdram_clk      ,//connected to the CLK port of SDRAM  

-		sdram_cke      ,//connected to the CKE port of SDRAM  

-		sdram_cs_n     ,//connected to the CS_n port of SDRAM 

-		sdram_ras_n    ,//connected to the RAS_n port of SDRAM

-		sdram_cas_n    ,//connected to the CAS_n port of SDRAM

-		sdram_we_n     ,//connected to the WE_n port of SDRAM 

-		sdram_ba       ,//connected to the BA port of SDRAM 

-		sdram_addr     ,//connected to the ADDR port of SDRAM   

-		sdram_dqm      ,//connected to the DQM port of SDRAM 

-		sdram_dq       ,//connected to the DQ port of SDRAM

-		

-		dm9000_int  ,

-		dm9000_rst_n,

-		dm9000_cs_n ,

-    	dm9000_cmd  ,

-    	dm9000_rd_n ,

-    	dm9000_wr_n ,

-    	dm9000_data ,

-		

-      vga_hs,

-      vga_vs,

-      vga_red,

-      vga_green,

-      vga_blue,

-    	

-		seven_seg

-	);

-	

-	input clk;

-	input rst_n;

-	

-	output			sdram_clk  ;

-	output			sdram_cke  ;

-	output			sdram_cs_n ;

-	output			sdram_ras_n;

-	output			sdram_cas_n;

-	output			sdram_we_n ;

-	output [ 1 : 0]	sdram_ba   ;

-	output [12 : 0]	sdram_addr ;

-	output [ 1 : 0]	sdram_dqm  ;

-	inout  [15 : 0]	sdram_dq   ;

-	

-	input           dm9000_int  ;

-	output			dm9000_rst_n;

-   output 			dm9000_cs_n ;

-   output 			dm9000_cmd  ;

-   output 			dm9000_rd_n ;

-   output 			dm9000_wr_n ;

-   inout  [15:0]	dm9000_data ;

-	

-	output [ 7:0] seven_seg;

-

-

-   output vga_hs;

-   output vga_vs;

-   output [2:0] vga_red;

-   output [2:0] vga_green;

-   output [2:0] vga_blue;		

-

-	

-	wire sclk;

-	

-	

-	pll u_pll(

-		.inclk0(clk      ),

-		.c0    (sclk     ),

-		.c1    (sdram_clk)

-	);

-	

-	

-	

-	my_sys u_my_sys(

-		.reset_reset_n     (rst_n      ),
-		.clk_clk           (sclk       ),
-		.sdram_0_wire_addr (sdram_addr ),
-		.sdram_0_wire_ba   (sdram_ba   ),
-		.sdram_0_wire_cas_n(sdram_cas_n),
-		.sdram_0_wire_cke  (sdram_cke  ),
-		.sdram_0_wire_cs_n (sdram_cs_n ),
-		.sdram_0_wire_dq   (sdram_dq   ),
-		.sdram_0_wire_dqm  (sdram_dqm  ),
-		.sdram_0_wire_ras_n(sdram_ras_n),
-		.sdram_0_wire_we_n (sdram_we_n ),
-		.pio_0_d_export    (seven_seg  ),

-		

-		

-		.gpu_0_vga_red(vga_red),

-		.gpu_0_vga_green(vga_green),

-		.gpu_0_vga_blue(vga_blue),

-		.gpu_0_vga_hs(vga_hs),

-		.gpu_0_vga_vs(vga_vs),

-		.gpu_0_vga_clk(clk),

-		

-    	.dm9000a_0_conduit_end_iOSC_50   (            ),
-		.dm9000a_0_conduit_end_ENET_DATA (dm9000_data ),
-		.dm9000a_0_conduit_end_ENET_CMD  (dm9000_cmd  ),
-		.dm9000a_0_conduit_end_ENET_RD_N (dm9000_rd_n ),
-		.dm9000a_0_conduit_end_ENET_WR_N (dm9000_wr_n ),
-		.dm9000a_0_conduit_end_ENET_CS_N (dm9000_cs_n ),
-		.dm9000a_0_conduit_end_ENET_RST_N(dm9000_rst_n),
-		.dm9000a_0_conduit_end_ENET_INT  (dm9000_int  ),
-		.dm9000a_0_conduit_end_ENET_CLK  (            ) 

-	);

-

-	

-	

-	

-endmodule 
+module pong3(
+    clk,
+    rst_n,
+
+    sdram_clk,		//connected to the CLK port of SDRAM
+    sdram_cke,		//connected to the CKE port of SDRAM
+    sdram_cs_n,		//connected to the CS_n port of SDRAM
+    sdram_ras_n,	//connected to the RAS_n port of SDRAM
+    sdram_cas_n,	//connected to the CAS_n port of SDRAM
+    sdram_we_n,		//connected to the WE_n port of SDRAM
+    sdram_ba,		//connected to the BA port of SDRAM
+    sdram_addr,		//connected to the ADDR port of SDRAM
+    sdram_dqm,		//connected to the DQM port of SDRAM
+    sdram_dq,		//connected to the DQ port of SDRAM
+
+    dm9000_int  ,
+    dm9000_rst_n,
+    dm9000_cs_n ,
+    dm9000_cmd  ,
+    dm9000_rd_n ,
+    dm9000_wr_n ,
+    dm9000_data ,
+
+    vga_hs,
+    vga_vs,
+    vga_red,
+    vga_green,
+    vga_blue,
+
+    seven_seg
+);
+
+input clk;
+input rst_n;
+
+output sdram_clk  ;
+output sdram_cke  ;
+output sdram_cs_n ;
+output sdram_ras_n;
+output sdram_cas_n;
+output sdram_we_n ;
+output [ 1 : 0]	sdram_ba   ;
+output [12 : 0]	sdram_addr ;
+output [ 1 : 0]	sdram_dqm  ;
+inout  [15 : 0]	sdram_dq   ;
+
+input  dm9000_int  ;
+output dm9000_rst_n;
+output dm9000_cs_n ;
+output dm9000_cmd  ;
+output dm9000_rd_n ;
+output dm9000_wr_n ;
+inout  [15:0] dm9000_data ;
+
+output [ 7:0] seven_seg;
+
+
+output vga_hs;
+output vga_vs;
+output [2:0] vga_red;
+output [2:0] vga_green;
+output [2:0] vga_blue;
+
+
+wire sclk;
+
+
+pll u_pll(
+    .inclk0(clk      ),
+    .c0    (sclk     ),
+    .c1    (sdram_clk)
+);
+
+
+
+my_sys u_my_sys(
+    .reset_reset_n     (rst_n      ),
+    .clk_clk           (sclk       ),
+    .sdram_0_wire_addr (sdram_addr ),
+    .sdram_0_wire_ba   (sdram_ba   ),
+    .sdram_0_wire_cas_n(sdram_cas_n),
+    .sdram_0_wire_cke  (sdram_cke  ),
+    .sdram_0_wire_cs_n (sdram_cs_n ),
+    .sdram_0_wire_dq   (sdram_dq   ),
+    .sdram_0_wire_dqm  (sdram_dqm  ),
+    .sdram_0_wire_ras_n(sdram_ras_n),
+    .sdram_0_wire_we_n (sdram_we_n ),
+    .pio_0_d_export    (seven_seg  ),
+
+
+    .gpu_0_vga_red(vga_red),
+    .gpu_0_vga_green(vga_green),
+    .gpu_0_vga_blue(vga_blue),
+    .gpu_0_vga_hs(vga_hs),
+    .gpu_0_vga_vs(vga_vs),
+    .gpu_0_vga_clk(clk),
+
+    .dm9000a_0_conduit_end_iOSC_50   (            ),
+    .dm9000a_0_conduit_end_ENET_DATA (dm9000_data ),
+    .dm9000a_0_conduit_end_ENET_CMD  (dm9000_cmd  ),
+    .dm9000a_0_conduit_end_ENET_RD_N (dm9000_rd_n ),
+    .dm9000a_0_conduit_end_ENET_WR_N (dm9000_wr_n ),
+    .dm9000a_0_conduit_end_ENET_CS_N (dm9000_cs_n ),
+    .dm9000a_0_conduit_end_ENET_RST_N(dm9000_rst_n),
+    .dm9000a_0_conduit_end_ENET_INT  (dm9000_int  ),
+    .dm9000a_0_conduit_end_ENET_CLK  (            )
+);
+
+
+
+
+endmodule