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* VMX: use proper instruction mnemonics if assembler supports themJan Beulich2013-09-094-29/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the hex byte emission we were taking away a good part of flexibility from the compiler, as for simplicity reasons these were built using fixed operands. All half way modern build environments would allow using the mnemonics (but we can't disable the hex variants yet, since the binutils around at the time gcc 4.1 got released didn't support these yet). I didn't convert __vmread() yet because that would, just like for __vmread_safe(), imply converting to a macro so that the output operand can be the caller supplied variable rather than an intermediate one. As that would require touching all invocation points of __vmread() (of which there are quite a few), I'd first like to be certain the approach is acceptable; the main question being whether the now conditional code might be considered to cause future maintenance issues, and the second being that of parameter/argument ordering (here I made __vmread_safe() match __vmwrite(), but one could also take the position that read and write should use the inverse order of one another, in line with the actual instruction operands). Additionally I was quite puzzled to find that all the asm()-s involved here have memory clobbers - what are they needed for? Or can they be dropped at least in some cases? Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Tim Deegan <tim@xen.org>
* VMX: move various uses of UD2 out of fast pathsJan Beulich2013-09-092-6/+43
| | | | | | | | | ... at once making conditional forward jumps, which are statically predicted to be not taken, only used for the unlikely (error) cases. Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Tim Deegan <tim@xen.org>
* VMX: streamline entry.S codeJan Beulich2013-09-093-62/+48
| | | | | | | | | | | | | - move stuff easily/better done in C into C code - re-arrange code paths so that no redundant GET_CURRENT() would remain on the fast paths - move long latency operations earlier - slightly defer disabling interrupts on the VM entry path - use ENTRY() instead of open coding it Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Tim Deegan <tim@xen.org>
* xen/char: dt-uart: Allow the user to give a path to the nodeJulien Grall2013-09-061-6/+10
| | | | | | | | | | | On some board, there is no alias to the UART. To avoid modification in the device tree, dt-uart should also search device by path. To distinguish an alias from a path, dt-uart will check the first character. If it's a / then it's path, otherwise it's an alias. Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* pl011: preserve RTS and DTR signal on UART initAndre Przywara2013-09-032-2/+9
| | | | | | | | | | | | | Although we do not support hardware flow control in the Xen driver for the PL011 UART, the other end may be configured to use it. In this case it waits in vain for the RTS signal to be asserted by the host and will never transmit any characters. So we leave RTS and DTR as they had been setup before. This fixes the UART input on Calxeda Midway, which uses hardware flow control for the serial-over-LAN functionality. Signed-off-by: Andre Przywara <andre.przywara@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* xen/x86: don't use '.ifnes' in bug frame construction.Tim Deegan2013-08-301-6/+8
| | | | | | | | | | | | | | | Spotted because it breaks the clang build for LLVM <3.2. .ifnes is not right here as it will choke on a string with embedded quotes. .ifnb would be better except that LLVM <3.2 doesn't support that either (and nor does binutils 2.16). It should be possible to use something like !!msg or !!msg[0] instead of a separate flag, but I gave up trying to find something that would make it through CPP, asm() and gas as a usable constant. :| Signed-off-by: Tim Deegan <tim@xen.org> Acked-by: Jan Beulich <jbeulich@suse.com>
* x86/mwait_idle: initial C8, C9, C10 supportLen Brown2013-08-301-0/+18
| | | | | | | | | | Allow mwait_idle to utilize C8, C9, C10 when they are present on... "Fourth Generation Intel(R) Core(TM) Processors", which are based on Intel(R) microarchitecture code name Haswell. Signed-off-by: Len Brown <len.brown@intel.com> Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* x86/mwait_idle: export both C1 and C1ELen Brown2013-08-302-5/+48
| | | | | | | | | | | | | | | | | | Here we disable HW promotion of C1 to C1E and export both C1 and C1E as distinct C-states. This allows a cpuidle governor to choose a lower latency C-state than C1E when necessary to satisfy performance and QOS constraints -- and still save power versus polling. This also corrects the erroneous latency previously reported for C1E -- it is 10usec, not 1usec. Signed-off-by: Len Brown <len.brown@intel.com> Avoided the effect of changing the meaning of "max_cstate=". Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* x86/mwait_idle: remove assumption of one C-state per MWAIT flagLen Brown2013-08-302-57/+50
| | | | | | | | | | | | | | | | | | | Remove the assumption that cstate_tables are indexed by MWAIT flag values. Each entry identifies itself via its own flags value. This change is needed to support multiple states that share the same MWAIT flags. Note that this can have an effect on what state is described by 'N' on cmdline max_cstate=N on some systems. Signed-off-by: Len Brown <len.brown@intel.com> Avoided the effect of changing the meaning of "max_cstate=". Drop MWAIT_MAX_NUM_CSTATES (done differently in a prior patch on Linux). Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* x86/xsave: initialization improvementsJan Beulich2013-08-303-15/+17
| | | | | | | | | | - properly validate available feature set on APs - also validate xsaveopt availability on APs - properly indicate whether the initialization is on the BSP (we shouldn't be using "cpu == 0" checks for this) Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* x86: remove PentiumPro checkMatt Wilson2013-08-301-4/+0
| | | | | | | ... as it's not a supported processor Signed-off-by: Matt Wilson <msw@amazon.com> Acked-by: Keir Fraser <keir@xen.org>
* x86: remove X86_INTEL_USERCOPY codeMatt Wilson2013-08-301-21/+0
| | | | | | | | Nothing defines CONFIG_X86_INTEL_USERCOPY, and as far as I can tell it was never used even when Xen supported 32-bit x86. Signed-off-by: Matt Wilson <msw@amazon.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
* x86/apic: remove DMI checks in bigsmp driver for obsolete systemsMatt Wilson2013-08-301-9/+0
| | | | | | | | | The DMI checks that force the use of the bigsmp APIC driver are for systems that are no longer supported by Xen (32-bit x86). Signed-off-by: Matt Wilson <msw@amazon.com> Acked-by: Keir Fraser <keir@xen.org> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
* x86: remove references to unimplemented BIOS reboot optionMatt Wilson2013-08-301-25/+17
| | | | | | | | | The BIOS reboot option was never implemented for x86_64, and retaining it is somewhat false advertising. Signed-off-by: Matt Wilson <msw@amazon.com> Acked-by: Keir Fraser <keir@xen.org> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
* public/hvm_xs_strings.h: Fix ABI regression for OEM SMBios stringsAndrew Cooper2013-08-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The old code for OEM SMBios strings was: char path[20] = "bios-strings/oem-XX"; path[(sizeof path) - 3] = '0' + ((i < 10) ? i : i / 10); path[(sizeof path) - 2] = (i < 10) ? '\0' : '0' + (i % 10); Where oem-1 thru 9 specifically had no leading 0. However, the definition of HVM_XS_OEM_STRINGS specifically requires leading 0s. This regression was introduced by the combination of c/s 4d23036e709627 and e64c3f71ceb662 I realise that this patch causes a change to the public headers. However I feel it is justified as: * All toolstacks used to have to embed the magic string (and almost certainly still do) * If by some miriacle a new toolstack has started using the new define will continue to work. * The only intree consumer of the define is hvmloader itself. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* AMD IOMMU: allow command line overrides for broken IVRS tablesJan Beulich2013-08-293-18/+87
| | | | | | | | | | | | | | With there being so many systems with broken ACPI tables, and with it generally being known what's wrong with those tables, give people a handle to overcome the resulting disabling of their IOMMUs. Inspired by Linux side patches providing similar functionality. Suggested-by: Sander Eikelenboom <linux@eikelenboom.it> Signed-off-by: Jan Beulich <jbeulich@suse.com> Tested-By: Sander Eikelenboom <linux@eikelenboom.it> Acked-by: Keir Fraser <keir@xen.org> Acked-by: Suravee Suthikulpanit <suravee.suthikulapanit@amd.com>
* AMD IOMMU: add missing checksJan Beulich2013-08-291-3/+11
| | | | | | | | | | | For one we shouldn't accept IVHD tables specifying IO-APIC IDs beyond the limit we support (MAX_IO_APICS, currently 128). And then we shouldn't memset() a pointer allocation of which failed. Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Suravee Suthikulpanit <suravee.suthikulapanit@amd.com>
* x86: AVX instruction emulation fixesJan Beulich2013-08-281-9/+7
| | | | | | | | | | | | | | | | | | | - we used the C4/C5 (first prefix) byte instead of the apparent ModR/M one as the second prefix byte - early decoding normalized vex.reg, thus corrupting it for the main consumer (copy_REX_VEX()), resulting in #UD on the two-operand instructions we emulate Also add respective test cases to the testing utility plus - fix get_fpu() (the fall-through order was inverted) - add cpu_has_avx2, even if it's currently unused (as in the new test cases I decided to refrain from using AVX2 instructions in order to be able to actually run all the tests on the hardware I have) - slightly tweak cpu_has_avx to more consistently express the outputs we don't care about (sinking them all into the same variable) Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* xen: update tx_ready callback for ARM serial driversTomasz Wroblewski2013-08-283-3/+3
| | | | | | | | Type of tx_ready callback got changed to int to facilitate error condition, but the ARM serial drivers were not modified thus breaking the compilation. Reported-by: Julien Grall <julien.grall@linaro.org> Signed-off-by: Tomasz Wroblewski <tomasz.wroblewski@citrix.com>
* PCI UART: better cope with UART being temporarily unavailableTomasz Wroblewski2013-08-284-27/+45
| | | | | | | | | | | | | This happens for example when dom0 disables ioport responses during PCI subsystem initialisation. If a __ns16550_poll() happens to be scheduled during that time, Xen hangs. Detect and exit that condition. Amended ns16550_ioport_invalid function to only check IER register, which contins 3 reserved (always 0) bits, therefore it's sufficient for that test. Signed-off-by: Tomasz Wroblewski <tomasz.wroblewski@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* Fix inactive timer list corruption on second S3 resumeTomasz Wroblewski2013-08-281-1/+3
| | | | | | | | | | | init_timer cannot be safely called multiple times on same timer since it does memset(0) on the structure, erasing the auxiliary member used by linked list code. This breaks inactive timer list in common/timer.c. Moved resume_timer initialisation to ns16550_init_postirq, so it's only done once. Signed-off-by: Tomasz Wroblewski <tomasz.wroblewski@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* PCI: centralize parsing of device coordinates in command line optionsJan Beulich2013-08-285-45/+66
| | | | | | | | | With yet another case to come in a subsequent patch, it seems time to do this in a single place rather than hand crafting it in various scattered around locations. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* AMD IOMMU: also allocate IRTEs for HPET MSIJan Beulich2013-08-281-5/+22
| | | | | | | | | | | | | | Omitting this was a blatant oversight of mine in commit 2ca9fbd7 ("AMD IOMMU: allocate IRTE entries instead of using a static mapping"). This also changes a bogus inequality check into a sensible one, even though it is already known that this will make HPET MSI unusable on certain systems (having respective broken firmware). This, however, seems better than failing on systems with consistent ACPI tables. Reported-by: Sander Eikelenboom <linux@eikelenboom.it> Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
* xen/arm: use defines for boot module indexes instead of open coded numbersIan Campbell2013-08-275-16/+21
| | | | | Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Reviewed-by: Julien Grall <julien.grall@linaro.org>
* xen: arm: indicate when we have early panicedIan Campbell2013-08-271-0/+2
| | | | | | | | Otherwise the hypervisor simply appears to stop after a message which may or may not look all that severe. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Reviewed-by: Julien Grall <julien.grall@linaro.org>
* pl011: early_panic if baud rate not set in hardwareIan Campbell2013-08-271-0/+2
| | | | | | | | | | | Now that the driver defaults to BAUD_AUTO this can happen if the early uart != console or if early printk isn't in use. The following division by zero causes a trap but that uses regular printk and not early_printk, so it is never seen. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Julien Grall <julien.grall@linaro.org>
* xen/arm: add lower-bound check in mfn_validJaeyong Yoo2013-08-271-1/+1
| | | | | | | | | mfn_valid only checks the upper-bound of mfn (max_page). Add the lower-bound check of mfn (frametable_base_mfn). Signed-off-by: Jaeyong Yoo <jaeyong.yoo@samsung.com> Acked-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Julien Grall <julien.grall@linaro.org>
* xen/arm: Introduce and use GLOBAL() in asm code.Andrew Cooper2013-08-277-20/+12
| | | | | Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* drivers/char: pl011: Enable receive timeout interruptJulien Grall2013-08-271-1/+1
| | | | | | | | | | | | The commit 874f76a "PL011: fix reverse logic for interrupt mask register" introduced regression on the Versatile Express. The board didn't receive correctly input. The timeout interrupt may be asserted when the FIFO is not empty, and no futher data is received over a 32-bit period. Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* Revert "x86/boot: Explicitly clean pcpu stacks in debug builds"Jan Beulich2013-08-272-13/+0
| | | | | This reverts commit 8a3c4acc9907cfec9aae9f1bc251fbf50af6828e. It's reportedly broken.
* fix gdbstub build c/s c8177e691fAndrew Cooper2013-08-271-1/+1
| | | | | | | | | That changeset moved the watchdog functions from nmi.h to their own watchdog.h. I thought I had updated all relevant header files and the compiler was happy as well. However, gdbstub is not even compiled by default, and I accidentally missed it. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
* x86/boot: Explicitly clean pcpu stacks in debug buildsAndrew Cooper2013-08-272-0/+13
| | | | | | | | | This reduces confusion when looking at a hexdump of the pcpu stacks and wondering were on earth some of the junk was coming from. Also leave some grep fodder for finding where the BSP switches stack (because it took me far longer to find than I care to admit to). Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
* x86/time: remove Cyclone as a platform timerMatt Wilson2013-08-272-69/+3
| | | | | | | | | The Cyclone time source was part of IBM's Summit chipset, which was only used for 32-bit only ccNUMA and IA-64 machines. Neither of these are supported by Xen anymore. Signed-off-by: Matt Wilson <msw@amazon.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
* x86/apic: remove Summit supportMatt Wilson2013-08-275-139/+1
| | | | | | | | IBM's Summit chipset was only used for 32-bit only Intel ccNUMA and IA-64 machines, neither of which are supported by Xen anymore. Signed-off-by: Matt Wilson <msw@amazon.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
* x86/Intel: add support for Haswell CPU modelsJan Beulich2013-08-273-3/+10
| | | | | | | ... according to their most recent public documentation. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* VMX: convert EOI exit bitmap to a proper bitmapJan Beulich2013-08-273-41/+22
| | | | | | | | | ... allowing bitmap operations to be used on it, making things consistent with struct pi_desc's pir field, and shrinking overall source code size. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* x86: don't allow Dom0 access to the HT address rangeJan Beulich2013-08-271-0/+4
| | | | | | In particular, MMIO assignments should not be done using this area. Signed-off-by: Jan Beulich <jbeulich@suse.com>
* x86: don't allow Dom0 access to the MSI address rangeJan Beulich2013-08-271-0/+4
| | | | | | | In particular, MMIO assignments should not be done using this area. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by Xiantao Zhang <xiantao.zhang@intel.com>
* Revert "interrupts: allow guest to set/clear MSI-X mask bit"Jan Beulich2013-08-261-47/+14
| | | | | This reverts commit 54a46bce768033b1c36e25eace15f7abde972389. It's not fully cooked yet.
* domctl: replace cpumask_weight() usesJan Beulich2013-08-231-4/+4
| | | | | | | | | | | In one case it could easily be replaced by range checking the result of a subsequent operation, and in general cpumask_next(), not always needing to scan the whole bitmap, is more efficient than the specific uses of cpumask_weight() here. (When running on big systems, operations on CPU masks aren't cheap enough to use them carelessly.) Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* credit1: replace cpumask_empty() usesJan Beulich2013-08-231-4/+3
| | | | | | | | | | | In one case it was redundant with the operation it got combined with, and in the other it could easily be replaced by range checking the result of a subsequent operation. (When running on big systems, operations on CPU masks aren't cheap enough to use them carelessly.) Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org> Reviewed-by: George Dunlap <george.dunlap@eu.citrix.com>
* credit2: replace cpumask_first() usesJan Beulich2013-08-231-8/+10
| | | | | | | | | | | | | ... with cpumask_any() or cpumask_cycle(). In one case this also allows elimination of a cpumask_empty() call, and while doing this I also spotted a redundant use of cpumask_weight(). (When running on big systems, operations on CPU masks aren't cheap enough to use them carelessly.) Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org> Reviewed-by: George Dunlap <george.dunlap@eu.citrix.com>
* x86: use cpumask_any() in mask-to-APIC-ID conversionsJan Beulich2013-08-232-2/+2
| | | | | | | | This is to avoid picking CPU0 for almost any such operation, resulting in very uneven distribution of interrupt load. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* un-alias cpumask_any() from cpumask_first()Jan Beulich2013-08-237-1/+90
| | | | | | | | | | | | | | | | | | In order to achieve more symmetric distribution of certain things, cpumask_any() shouldn't always pick the first CPU (which frequently will end up being CPU0). To facilitate that, introduce a library-like function to obtain random numbers. The per-architecture function is supposed to return zero if no valid random number can be obtained (implying that if occasionally zero got produced as random number, it wouldn't be considered such). As fallback this uses the trivial algorithm from the C standard, extended to produce "unsigned int" results. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org> Reviewed-by: George Dunlap <george.dunlap@eu.citrix.com>
* x86: correct public header's documentation of PAT MSR settingsJan Beulich2013-08-231-9/+9
| | | | | | | | The first (PAT6) column was wrong across the board, and the column for PAT7 was missing altogether. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* PCI: break MSI-X data out of struct pci_dev_infoJan Beulich2013-08-235-64/+86
| | | | | | | | | | | Considering that a significant share of PCI devices out there (not the least the myriad of CPU-exposed ones) don't support MSI-X at all, and that the amount of data is well beyond a handful of bytes, break this out of the common structure, at once allowing the actual data to be tracked to become architecture specific. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* x86: move struct bug_frame instances out of lineJan Beulich2013-08-235-84/+105
| | | | | | | | | | | | | | Just like Linux did many years ago, move them into a separate (data) section, such that they no longer pollute instruction caches and TLBs. Assertion frames, requiring two pointers to be stored, occupy two slots in the array, with the second slot mimicking a frame the location pointer of which doesn't match any address within .text or .init.text (it effectively points back to the slot itself, which - being in a data section - can't be reached by non-buggy execution). Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* xen: arm: retry trylock if strex fails on free lock.Ian Campbell2013-08-222-12/+16
| | | | | | | | | | | | | | | | | | | | | | | This comes from the Linux patches 15e7e5c1ebf5 for arm32 and 4ecf7ccb1973 for arm64 by Will Deacon and Catalin Marinas respectively. The Linux commit message says: An exclusive store instruction may fail for reasons other than lock contention (e.g. a cache eviction during the critical section) so, in line with other architectures using similar exclusive instructions (alpha, mips, powerpc), retry the trylock operation if the lock appears to be free but the strex reported failure. I have observed this due to register_cpu_notifier containing: if ( !spin_trylock(&cpu_add_remove_lock) ) BUG(); /* Should never fail as we are called only during boot. */ which was spuriously failing. The ARMv8 variant is taken directly from the Linux patch. For v7 I had to reimplement since we don't currently use ticket locks. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Tim Deegan <tim@xen.org>
* xen/arm64: resync atomics and spinlock asm with LinuxIan Campbell2013-08-223-94/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | This picks up the changes from Linux commit 3a0310eb369a: arm64: atomics: fix grossly inconsistent asm constraints for exclusives Our uses of inline asm constraints for atomic operations are fairly wild and varied. We basically need to guarantee the following: 1. Any instructions with barrier implications (load-acquire/store-release) have a "memory" clobber 2. When performing exclusive accesses, the addresing mode is generated using the "Q" constraint 3. Atomic blocks which use the condition flags, have a "cc" clobber This patch addresses these concerns which, as well as fixing the semantics of the code, stops GCC complaining about impossible asm constraints. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Tim Deegan <tim@xen.org>
* xen/arm64: Assembly optimized bitops from LinuxIan Campbell2013-08-223-217/+76
| | | | | | | | | | | | | | | | | | | | | | | This patch replaces the previous hashed lock implementaiton of bitops with assembly optimized ones taken from Linux v3.10-rc4. The Linux derived ASM only supports 8 byte aligned bitmaps (which under Linux are unsigned long * rather than our void *). We do have actually uses of 4 byte alignment (i.e. the bitmaps in struct xmem_pool) which trigger alignment faults. Therefore adjust the assembly to work in 4 byte increments, which involved: - bit offset now bits 4:0 => mask #31 not #63 - use wN register not xN for load/modify/store loop. There is no need to adjust the shift used to calculate the word offset, the difference is already acounted for in the #63->#31 change. NB: Xen's build system cannot cope with the change from .c to .S file, remove xen/arch/arm/arm64/lib/.bitops.o.d or clean your build tree. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Tim Deegan <tim@xen.org>
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