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authorLen Brown <len.brown@intel.com>2013-08-30 11:00:07 +0200
committerJan Beulich <jbeulich@suse.com>2013-08-30 11:00:07 +0200
commit6e287713c94b40bbf21a378eab622108b1186233 (patch)
tree051637dce6c517bd7c53190b418aa50b49bbda51 /xen
parent91413b51963127d435cfba38e382e81188527ef5 (diff)
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x86/mwait_idle: initial C8, C9, C10 support
Allow mwait_idle to utilize C8, C9, C10 when they are present on... "Fourth Generation Intel(R) Core(TM) Processors", which are based on Intel(R) microarchitecture code name Haswell. Signed-off-by: Len Brown <len.brown@intel.com> Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
Diffstat (limited to 'xen')
-rw-r--r--xen/arch/x86/cpu/mwait-idle.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c
index 879963215f..85179f2f81 100644
--- a/xen/arch/x86/cpu/mwait-idle.c
+++ b/xen/arch/x86/cpu/mwait-idle.c
@@ -252,6 +252,24 @@ static const struct cpuidle_state hsw_cstates[] = {
.exit_latency = 166,
.target_residency = 500,
},
+ {
+ .name = "C8-HSW",
+ .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 300,
+ .target_residency = 900,
+ },
+ {
+ .name = "C9-HSW",
+ .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 600,
+ .target_residency = 1800,
+ },
+ {
+ .name = "C10-HSW",
+ .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 2600,
+ .target_residency = 7700,
+ },
{}
};