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* sched/credit: Remove redundant assignments from alloc_* functionsAndrew Cooper2013-09-131-4/+0
| | | | | | | | Noticed because Coverity was complaining at the atomic_set(), but because of the use of xzalloc(), these assignments of 0 are completely redundent. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: George Dunlap <george.dunlap@eu.citrix.com>
* x86: machine_restart() must not call acpi_dmar_reinstate() twiceJan Beulich2013-09-131-2/+3
| | | | | | | | | | | | | | .. as that function is not idempotent (it always alters the table checksum). The (generally) duplicate call was a result from it being made before machine_restart() re-invoking itself on the boot CPU. Considering that no problem arose so far from the table corruption I doubt that we need to restore the correct table signature on the reboot path in general. The only case I can see this as potentially necessary is the tboot one, hence do the call just in that case. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* acpi/pmstat: fix check for empty name strings.Tim Deegan2013-09-121-2/+2
| | | | | | | | | | | | These 'name' strings are actually arrays in their structs. So the address is never NULL: instead, we should check the first character to detect cases where the field wasn't initialized. Coverity CID 1055633 Signed-off-by: Tim Deegan <tim@xen.org> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Jan Beulich <jbeulich@suse.com>
* ehci-dbgp: avoid division by zero.Tim Deegan2013-09-121-0/+3
| | | | | | | | | | | Unlikely to ever see hardware reporting 0 ports, but might as well fail gracefully if we do. Coverity CID 1055266 Signed-off-by: Tim Deegan <tim@xen.org> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Jan Beulich <jbeulich@suse.com>
* ehci-dbgp: drop dead code.Tim Deegan2013-09-121-5/+0
| | | | | | | | | | | We can only reach this spot by breaking out of the scan loop, so by construction ret > 0. Coverity CID 1055259 Signed-off-by: Tim Deegan <tim@xen.org> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Jan Beulich <jbeulich@suse.com>
* cpufreq: missing check of copy_from_guest()Tim Deegan2013-09-121-2/+6
| | | | | | | | | Coverity CID 1055131 Coverity CID 1055132 Signed-off-by: Tim Deegan <tim@xen.org> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Jan Beulich <jbeulich@suse.com>
* cpufreq: avoid integer overflows.Tim Deegan2013-09-121-3/+4
| | | | | | | | | | | | | The def_sampling_rate() one is, I think, a real bug. The others were spotted at the same time and are probably not bugs until we start dealing with 40GHz CPus. Coverity CID 1055682 Coverity CID 1055683 Signed-off-by: Tim Deegan <tim@xen.org> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Jan Beulich <jbeulich@suse.com>
* x86/mm: Don't dereference p2m pointer before NULL check.Tim Deegan2013-09-121-1/+3
| | | | | | | | | | Not a security bug, because in fact this is never called with a NULL argument. Coverity CID 1055955 Signed-off-by: Tim Deegan <tim@xen.org> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
* x86: fix memory cut-off when using PFN compressionJan Beulich2013-09-122-9/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | For one setup_max_pdx(), when invoked a second time (after SRAT got parsed), needs to start from the original max_page value again (using the already adjusted one from the first invocation would not allow the cut-off boundary to be moved up). Second, _if_ we need to cut off some part of memory, we must not allow this to also propagate into the NUMA accounting. Otherwise cutoff_node() results in nodes_cover_memory() to find some parts of memory apparently not having a PXM association, causing all SRAT info to be ignored. The only possibly problematic consumer of node_spanned_pages (the meaning of which gets altered here in that it now also includes memory Xen can't actively make use of) is XEN_SYSCTL_numainfo: At a first glance the potentially larger reported memory size shouldn't confuse tool stacks. And finally we must not put our boot time modules at addresses which (at that time) can't be guaranteed to be accessible later. This applies to both the EFI boot loader and the module relocation code. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org> Acked-by: Dario Faggioli <dario.faggioli@citrix.com>
* sched/arinc653: check for guest data transfer failuresMatthew Daley2013-09-101-2/+11
| | | | | | | | | | | Coverity-ID: 1055121 Coverity-ID: 1055122 Coverity-ID: 1055123 Coverity-ID: 1055124 Signed-off-by: Matthew Daley <mattjd@gmail.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: George Dunlap <george.dunlap@eu.citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* x86: add missing va_end to hypercall_xlat_continuationMatthew Daley2013-09-101-0/+4
| | | | | | | Coverity-ID: 1056208 Signed-off-by: Matthew Daley <mattjd@gmail.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* x86/mm: Fix possible increment of uninitialised variableAndrew Cooper2013-09-101-1/+1
| | | | | | | | | | | | | | | Discovered by Coverity, CID 1056101 When taking the continue branch on the first iteration of the loop, gfn would indeed be uninitialised when incremented. However, as gfn is unconditionally constructed from i{1..4} before use in the loop body, having it incremented in the loop header is useless. Therefore, simply remove it. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com> Acked-by: Tim Deegan <tim@xen.org>
* Nested VMX: Clear bit 31 of IA32_VMX_BASIC MSRYang Zhang2013-09-101-1/+1
| | | | | | | | | | The bit 31 of revision_id will set to 1 if vmcs shadowing enabled. And according intel SDM, the bit 31 of IA32_VMX_BASIC MSR is always 0. So we cannot set low 32 bit of IA32_VMX_BASIC to revision_id directly. Must clear the bit 31 to 0. Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
* x86/ioapic: avoid trying to access the -1th ioapicAndrew Cooper2013-09-101-1/+1
| | | | | | | | | | | | | Discovered by Coverity, CID 1055743 Depending on the contents of the mp_irqs/mp_ioapics from the MP table, find_isa_irq_apic() might return -1, at which point calling ioapic_read_entry() with it is bad. In addition to bailing if pin is -1, bail if apic is -1. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* console: buffer and show origin of guest PV writesDaniel De Graaf2013-09-106-40/+102
| | | | | | | | | | | | | Guests other than domain 0 using the console output have previously been controlled by the VERBOSE #define, but with no designation of which guest's output was on the console. This patch converts the HVM output buffering to be used by all domains except the hardware domain (dom0): stripping non-printable characters, line buffering the output, and prefixing it with the domain ID. This is especially useful for debugging stub domains during early boot. Signed-off-by: Daniel De Graaf <dgdegra@tycho.nsa.gov> Acked-by: Keir Fraser <keir@xen.org>
* libelf: add hvm callback vector featureMukesh Rathor2013-09-101-0/+1
| | | | | | | | | Add XENFEAT_hvm_callback_vector to elf_xen_feature_names so we can ensure the kernel supports all features required for PVH mode when building a PVH domU here. Note, hvm callback is required for PVH. Signed-off-by: Mukesh Rathor <mukesh.rathor@oracle.com> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* xen: Add new string functionJulien Grall2013-09-102-0/+18
| | | | | | | Add strcasecmp. The code is copied from Linux. Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* xen/arm: Move __PSCI* from traps.c to the headerJulien Grall2013-09-102-5/+5
| | | | | | | These defines will be used to create the fake PSCI node in dom0 device tree. Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* xen/dts: Don't check the number of address and size cells in process_cpu_nodeJulien Grall2013-09-101-6/+0
| | | | | | | | | | | | | | CPU nodes are not required to have #address-cells == 1 and #size-cells == 0, so don't check for that (see Linux Documentation/devicetree/booting-without-of.txt Section III.5.a). In some OMAP5 device, tree, these 2 properties are not correctly set. Therefore, Xen will only able to handle 1 CPU. Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com> CC: andrii.anisov@globallogic.com CC: baozich@gmail.com
* xen: Introduce __initconst to store initial const dataJulien Grall2013-09-101-0/+1
| | | | | | | | | | | | | | | It's possible to have 2 type (const and non-const) of data in the same compilation unit. Using only __initdata will result to a compilation error: error: $variablename causes as section tupe conflict with $variablename2 because a section containing const variables is marked read only and so cannot contain non-const variables. Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Cambell <ian.campbell@citrix.com> CC: Jan Beulich <JBeulich@suse.com> CC: Keir Fraser <keir@xen.org>
* xen/dts: fix DT_ROOT_NODE_ADDR_CELLS_DEFAULTJulien Grall2013-09-091-1/+1
| | | | | | | | | | | | The commit dbd1243 "xen/arm: Add helpers to use the device tree" introduced DT_ROOT_NODE_ADDR_CELLS_DEFAULT with is used for default value when bad copy from Linux code. The ePAR (section 2.3.5) says: "If missing, a client program should assume a default value of 2 for #address-cells, and a value of 1 for #size-cells." Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* xen/arm: Panic if we can't copy the DTB to dom0 memoryJulien Grall2013-09-091-1/+4
| | | | | Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* xen/arm: Introduce MPIDR_HWID_MASKJulien Grall2013-09-092-1/+2
| | | | | | | | This define will be use later to retrieve the correct hardware CPU ID. Also replace hardcoded mask in arm32/head.S by this define. Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* x86/xsave: fix migration from xsave-capable to xsave-incapable hostJan Beulich2013-09-0910-88/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With CPUID features suitably masked this is supposed to work, but was completely broken (i.e. the case wasn't even considered when the original xsave save/restore code was written). First of all, xsave_enabled() wrongly returned the value of cpu_has_xsave, i.e. not even taking into consideration attributes of the vCPU in question. Instead this function ought to check whether the guest ever enabled xsave support (by writing a [non-zero] value to XCR0). As a result of this, a vCPU's xcr0 and xcr0_accum must no longer be initialized to XSTATE_FP_SSE (since that's a valid value a guest could write to XCR0), and the xsave/xrstor as well as the context switch code need to suitably account for this (by always enforcing at least this part of the state to be saved/loaded). This involves undoing large parts of c/s 22945:13a7d1f7f62c ("x86: add strictly sanity check for XSAVE/XRSTOR") - we need to cleanly distinguish between hardware capabilities and vCPU used features. Next both HVM and PV save code needed tweaking to not always save the full state supported by the underlying hardware, but just the parts that the guest actually used. Similarly the restore code should bail not just on state being restored that the hardware cannot handle, but also on inconsistent save state (inconsistent XCR0 settings or size of saved state not in line with XCR0). And finally the PV extended context get/set code needs to use slightly different logic than the HVM one, as here we can't just key off of xsave_enabled() (i.e. avoid doing anything if a guest doesn't use xsave) because the tools use this function to determine host capabilities as well as read/write vCPU state. The set operation in particular needs to be capable of cleanly dealing with input that consists of only the xcr0 and xcr0_accum values (if they're both zero then no further data is required). While for things to work correctly both sides (saving _and_ restoring host) need to run with the fixed code, afaict no breakage should occur if either side isn't up to date (other than the breakage that this patch attempts to fix). Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Yang Zhang <yang.z.zhang@intel.com> Acked-by: Keir Fraser <keir@xen.org>
* EFI: fix tool chain capabilities detectionJan Beulich2013-09-091-5/+4
| | | | | | | | | | | Commit f5a54e92 ("xen: move some arch CFLAGS into the common Rules.mk") transformed CFLAGS assignments to CFLAGS-y ones, which collides with the was xen/arch/x86/efi/Makefile determines whether the tol chain is usable for an EFI build. Transform the block back to using CFLAGS. Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Tim Deegan <tim@xen.org> Acked-by: Keir Fraser <keir@xen.org>
* xmalloc: make whole pages xfree() clear the order field (ab)used by xmalloc()Jan Beulich2013-09-091-0/+1
| | | | | | | | | | | | | Not doing this was found to cause problems with sequences of allocation (multi-page), freeing, and then again allocation of the same page upon boot when interrupts are still disabled (causing the owner field to be non-zero, thus making the allocator attempt a TLB flush and, in its processing, triggering an assertion). Reported-by: Tomasz Wroblewski <tomasz.wroblewski@citrix.com> Signed-off-by: Jan Beulich <jbeulich@suse.com> Tested-by: Tomasz Wroblewski <tomasz.wroblewski@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* x86: allow guest to set/clear MSI-X mask bit (try 2)Joby Poriyath2013-09-091-12/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Guest needs the ability to enable and disable MSI-X interrupts by setting the MSI-X control bit, for a passed-through device. Guest is allowed to write MSI-X mask bit only if Xen *thinks* that mask is clear (interrupts enabled). If the mask is set by Xen (interrupts disabled), writes to mask bit by the guest is ignored. Currently, a write to MSI-X mask bit by the guest is silently ignored. A likely scenario is where we have a 82599 SR-IOV nic passed through to a guest. From the guest if you do ifconfig <ETH_DEV> down ifconfig <ETH_DEV> up the interrupts remain masked. On VF reset, the mask bit is set by the controller. At this point, Xen is not aware that mask is set. However, interrupts are enabled by VF driver by clearing the mask bit by writing directly to BAR3 region containing the MSI-X table. From dom0, we can verify that interrupts are being masked using 'xl debug-keys M'. Initially, guest was allowed to modify MSI-X bit. Later this behaviour was changed. See changeset 74c213c506afcd74a8556dd092995fd4dc38b225. Signed-off-by: Joby Poriyath <joby.poriyath@citrix.com>
* x86/EFI: properly handle run time memory regions outside the 1:1 mapJan Beulich2013-09-091-11/+93
| | | | | | | | | | | | | | Namely with PFN compression, MMIO ranges that the firmware may need runtime access to can live in the holes that gets shrunk/eliminated by PFN compression, and hence no mappings would result from simply copying Xen's direct mapping table's L3 page table entries. Build mappings for this "manually" in the EFI runtime call 1:1 page tables. Use the opportunity to also properly identify (via a forcibly undefined manifest constant) all the disabled code regions associated with it not being acceptable for us to call SetVirtualAddressMap(). Signed-off-by: Jan Beulich <jbeulich@suse.com>
* x86: Introduce and use GLOBAL() in asm codeAndrew Cooper2013-09-0912-77/+59
| | | | | | Also clean up some cases of misused/opencoded ENTRY() Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
* SVM: streamline entry.S codeJan Beulich2013-09-093-39/+34
| | | | | | | | | | | | | - fix a bogus "test" with zero immediate - move stuff easily/better done in C into C code - re-arrange code paths so that no redundant GET_CURRENT() would remain on the fast paths - move long latency operations earlier - slightly defer disabling global interrupts on the VM entry path Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Tim Deegan <tim@xen.org>
* VMX: use proper instruction mnemonics if assembler supports themJan Beulich2013-09-094-29/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the hex byte emission we were taking away a good part of flexibility from the compiler, as for simplicity reasons these were built using fixed operands. All half way modern build environments would allow using the mnemonics (but we can't disable the hex variants yet, since the binutils around at the time gcc 4.1 got released didn't support these yet). I didn't convert __vmread() yet because that would, just like for __vmread_safe(), imply converting to a macro so that the output operand can be the caller supplied variable rather than an intermediate one. As that would require touching all invocation points of __vmread() (of which there are quite a few), I'd first like to be certain the approach is acceptable; the main question being whether the now conditional code might be considered to cause future maintenance issues, and the second being that of parameter/argument ordering (here I made __vmread_safe() match __vmwrite(), but one could also take the position that read and write should use the inverse order of one another, in line with the actual instruction operands). Additionally I was quite puzzled to find that all the asm()-s involved here have memory clobbers - what are they needed for? Or can they be dropped at least in some cases? Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Tim Deegan <tim@xen.org>
* VMX: move various uses of UD2 out of fast pathsJan Beulich2013-09-092-6/+43
| | | | | | | | | ... at once making conditional forward jumps, which are statically predicted to be not taken, only used for the unlikely (error) cases. Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Tim Deegan <tim@xen.org>
* VMX: streamline entry.S codeJan Beulich2013-09-093-62/+48
| | | | | | | | | | | | | - move stuff easily/better done in C into C code - re-arrange code paths so that no redundant GET_CURRENT() would remain on the fast paths - move long latency operations earlier - slightly defer disabling interrupts on the VM entry path - use ENTRY() instead of open coding it Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Tim Deegan <tim@xen.org>
* xen/char: dt-uart: Allow the user to give a path to the nodeJulien Grall2013-09-061-6/+10
| | | | | | | | | | | On some board, there is no alias to the UART. To avoid modification in the device tree, dt-uart should also search device by path. To distinguish an alias from a path, dt-uart will check the first character. If it's a / then it's path, otherwise it's an alias. Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* pl011: preserve RTS and DTR signal on UART initAndre Przywara2013-09-032-2/+9
| | | | | | | | | | | | | Although we do not support hardware flow control in the Xen driver for the PL011 UART, the other end may be configured to use it. In this case it waits in vain for the RTS signal to be asserted by the host and will never transmit any characters. So we leave RTS and DTR as they had been setup before. This fixes the UART input on Calxeda Midway, which uses hardware flow control for the serial-over-LAN functionality. Signed-off-by: Andre Przywara <andre.przywara@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* xen/x86: don't use '.ifnes' in bug frame construction.Tim Deegan2013-08-301-6/+8
| | | | | | | | | | | | | | | Spotted because it breaks the clang build for LLVM <3.2. .ifnes is not right here as it will choke on a string with embedded quotes. .ifnb would be better except that LLVM <3.2 doesn't support that either (and nor does binutils 2.16). It should be possible to use something like !!msg or !!msg[0] instead of a separate flag, but I gave up trying to find something that would make it through CPP, asm() and gas as a usable constant. :| Signed-off-by: Tim Deegan <tim@xen.org> Acked-by: Jan Beulich <jbeulich@suse.com>
* x86/mwait_idle: initial C8, C9, C10 supportLen Brown2013-08-301-0/+18
| | | | | | | | | | Allow mwait_idle to utilize C8, C9, C10 when they are present on... "Fourth Generation Intel(R) Core(TM) Processors", which are based on Intel(R) microarchitecture code name Haswell. Signed-off-by: Len Brown <len.brown@intel.com> Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* x86/mwait_idle: export both C1 and C1ELen Brown2013-08-302-5/+48
| | | | | | | | | | | | | | | | | | Here we disable HW promotion of C1 to C1E and export both C1 and C1E as distinct C-states. This allows a cpuidle governor to choose a lower latency C-state than C1E when necessary to satisfy performance and QOS constraints -- and still save power versus polling. This also corrects the erroneous latency previously reported for C1E -- it is 10usec, not 1usec. Signed-off-by: Len Brown <len.brown@intel.com> Avoided the effect of changing the meaning of "max_cstate=". Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* x86/mwait_idle: remove assumption of one C-state per MWAIT flagLen Brown2013-08-302-57/+50
| | | | | | | | | | | | | | | | | | | Remove the assumption that cstate_tables are indexed by MWAIT flag values. Each entry identifies itself via its own flags value. This change is needed to support multiple states that share the same MWAIT flags. Note that this can have an effect on what state is described by 'N' on cmdline max_cstate=N on some systems. Signed-off-by: Len Brown <len.brown@intel.com> Avoided the effect of changing the meaning of "max_cstate=". Drop MWAIT_MAX_NUM_CSTATES (done differently in a prior patch on Linux). Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* x86/xsave: initialization improvementsJan Beulich2013-08-303-15/+17
| | | | | | | | | | - properly validate available feature set on APs - also validate xsaveopt availability on APs - properly indicate whether the initialization is on the BSP (we shouldn't be using "cpu == 0" checks for this) Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* x86: remove PentiumPro checkMatt Wilson2013-08-301-4/+0
| | | | | | | ... as it's not a supported processor Signed-off-by: Matt Wilson <msw@amazon.com> Acked-by: Keir Fraser <keir@xen.org>
* x86: remove X86_INTEL_USERCOPY codeMatt Wilson2013-08-301-21/+0
| | | | | | | | Nothing defines CONFIG_X86_INTEL_USERCOPY, and as far as I can tell it was never used even when Xen supported 32-bit x86. Signed-off-by: Matt Wilson <msw@amazon.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
* x86/apic: remove DMI checks in bigsmp driver for obsolete systemsMatt Wilson2013-08-301-9/+0
| | | | | | | | | The DMI checks that force the use of the bigsmp APIC driver are for systems that are no longer supported by Xen (32-bit x86). Signed-off-by: Matt Wilson <msw@amazon.com> Acked-by: Keir Fraser <keir@xen.org> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
* x86: remove references to unimplemented BIOS reboot optionMatt Wilson2013-08-301-25/+17
| | | | | | | | | The BIOS reboot option was never implemented for x86_64, and retaining it is somewhat false advertising. Signed-off-by: Matt Wilson <msw@amazon.com> Acked-by: Keir Fraser <keir@xen.org> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
* public/hvm_xs_strings.h: Fix ABI regression for OEM SMBios stringsAndrew Cooper2013-08-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The old code for OEM SMBios strings was: char path[20] = "bios-strings/oem-XX"; path[(sizeof path) - 3] = '0' + ((i < 10) ? i : i / 10); path[(sizeof path) - 2] = (i < 10) ? '\0' : '0' + (i % 10); Where oem-1 thru 9 specifically had no leading 0. However, the definition of HVM_XS_OEM_STRINGS specifically requires leading 0s. This regression was introduced by the combination of c/s 4d23036e709627 and e64c3f71ceb662 I realise that this patch causes a change to the public headers. However I feel it is justified as: * All toolstacks used to have to embed the magic string (and almost certainly still do) * If by some miriacle a new toolstack has started using the new define will continue to work. * The only intree consumer of the define is hvmloader itself. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* AMD IOMMU: allow command line overrides for broken IVRS tablesJan Beulich2013-08-293-18/+87
| | | | | | | | | | | | | | With there being so many systems with broken ACPI tables, and with it generally being known what's wrong with those tables, give people a handle to overcome the resulting disabling of their IOMMUs. Inspired by Linux side patches providing similar functionality. Suggested-by: Sander Eikelenboom <linux@eikelenboom.it> Signed-off-by: Jan Beulich <jbeulich@suse.com> Tested-By: Sander Eikelenboom <linux@eikelenboom.it> Acked-by: Keir Fraser <keir@xen.org> Acked-by: Suravee Suthikulpanit <suravee.suthikulapanit@amd.com>
* AMD IOMMU: add missing checksJan Beulich2013-08-291-3/+11
| | | | | | | | | | | For one we shouldn't accept IVHD tables specifying IO-APIC IDs beyond the limit we support (MAX_IO_APICS, currently 128). And then we shouldn't memset() a pointer allocation of which failed. Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Suravee Suthikulpanit <suravee.suthikulapanit@amd.com>
* x86: AVX instruction emulation fixesJan Beulich2013-08-281-9/+7
| | | | | | | | | | | | | | | | | | | - we used the C4/C5 (first prefix) byte instead of the apparent ModR/M one as the second prefix byte - early decoding normalized vex.reg, thus corrupting it for the main consumer (copy_REX_VEX()), resulting in #UD on the two-operand instructions we emulate Also add respective test cases to the testing utility plus - fix get_fpu() (the fall-through order was inverted) - add cpu_has_avx2, even if it's currently unused (as in the new test cases I decided to refrain from using AVX2 instructions in order to be able to actually run all the tests on the hardware I have) - slightly tweak cpu_has_avx to more consistently express the outputs we don't care about (sinking them all into the same variable) Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* xen: update tx_ready callback for ARM serial driversTomasz Wroblewski2013-08-283-3/+3
| | | | | | | | Type of tx_ready callback got changed to int to facilitate error condition, but the ARM serial drivers were not modified thus breaking the compilation. Reported-by: Julien Grall <julien.grall@linaro.org> Signed-off-by: Tomasz Wroblewski <tomasz.wroblewski@citrix.com>
* PCI UART: better cope with UART being temporarily unavailableTomasz Wroblewski2013-08-284-27/+45
| | | | | | | | | | | | | This happens for example when dom0 disables ioport responses during PCI subsystem initialisation. If a __ns16550_poll() happens to be scheduled during that time, Xen hangs. Detect and exit that condition. Amended ns16550_ioport_invalid function to only check IER register, which contins 3 reserved (always 0) bits, therefore it's sufficient for that test. Signed-off-by: Tomasz Wroblewski <tomasz.wroblewski@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
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