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* ARM: add Calxeda Midway platformAndre Przywara2013-08-203-0/+84
| | | | | | | | | | Calxeda Midway is an ARMv7 server platform with Cortex-A15 cores. The peripheral side has many similarities with the machine known as Highbank. Add Calxeda Midway to the list of supported platforms to avoid a warning on boot and provide the proper reset method. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
* PL011: don't force baud rate of 38400 bpsAndre Przywara2013-08-201-1/+1
| | | | | | | | | | | | The PL011 driver currently sets the baudrate to a hardcoded value of 38400 bits/second. This will break Calxeda Midway, which uses 115200 bps. Instead don't tinker with the baud rate register at all and rely on the firmware or bootloader setting the correct value in here. This works fine on Versatile Express and Calxeda Midway. Signed-off-by: Andre Przywara <andre.przywara@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* xen/arm: erratum 766422: decode thumb store during data abortJulien Grall2013-08-203-0/+21
| | | | | | | | | | | | | | | | | | | | | From the errata document: When a non-secure non-hypervisor memory operation instruction generates a stage2 page table translation fault, a trap to the hypervisor will be triggered. For an architecturally defined subset of instructions, the Hypervisor Syndrome Register (HSR) will have the Instruction Syndrome Valid (ISV) bit set to 1’b1, and the Rt field should reflect the source register (for stores) or destination register for loads. On Cortex-A15, for Thumb and ThumbEE stores, the Rt value may be incorrect and should not be used, even if the ISV bit is set. All loads, and all ARM instruction set loads and stores, will have the correct Rt value if the ISV bit is set. To avoid this issue, Xen needs to decode thumb store instruction and update the transfer register. Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* xen/arm: Start to implement an ARM decoder instructionJulien Grall2013-08-203-0/+215
| | | | | | | | | | | | Some errata on ARM processor requires to decode the instruction. The decoder will, obviously, decode and fill the ISS fields of the hsr_dabt. For the moment, the decoder only supports: - THUMB2 store instruction - THUMB single load/store instruction Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* xen/x86: hypervisor build fixes for FreeBSD.Tim Deegan2013-08-162-2/+2
| | | | | | | | | These allow an x86_64 hypervisor to build on FreeBSD 9.1/amd64. - like OpenBSD, needs a different arch passed to ld. - like OpenBSD, stdarg.h and stdbool.h are in /usr/include. Signed-off-by: Tim Deegan <tim@xen.org> Acked-by: Keir Fraser <keir@xen.org>
* x86/boot: Remove stack segment parameter from smpbootAndrew Cooper2013-08-161-6/+3
| | | | | | | | | | | The stack segment is legacy remnant of a 32bit hypervisor, and not used in 64bit. Furthermore, the unsigned short in the structure actually aliases whatever the linker decides to put next in the data section. Drop the extern struct definition and change it to a simple void pointer, which matches its definition in arch/x86/boot/x86_64.S Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
* xen: Add stdbool.h workaround for BSD.Tim Deegan2013-08-152-2/+15
| | | | | | | | | | | | | | | | On *BSD, stdbool.h lives in /usr/include, but we don't want to have that on the search path in case we pick up any headers from the build host's C libraries. Copy the equivalent hack already in place for stdarg.h: on all supported compilers the contents of stdbool.h are trivial, so just supply the things we need in a xen/stdbool.h header. Signed-off-by: Tim Deegan <tim@xen.org> Reviewed-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Keir Fraser <keir@xen.org> Tested-by: Patrick Welche <prlw1@cam.ac.uk>
* xen: move -nostdinc into common Rules.mk.Tim Deegan2013-08-152-7/+5
| | | | | | | | | | | | | | | | | Previously we didn't use it at all the on ARM ports or for clang builds. For ARM, I think this is just an oversight. For clang, this used not to work, because '-withprefix include' didn't let us see stdarg.h, but that's fixed in clang v3.0. Also move the '-withprefix include' to beside -nostdinc as it's only needed with -nostdinc anyway. Signed-off-by: Tim Deegan <tim@xen.org> Reviewed-by: Jan Beulich <jbeulich@suse.com> Acked-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* xen: move some arch CFLAGS into the common Rules.mk.Tim Deegan2013-08-153-4/+4
| | | | | | | | | | These are the same on all current architectures, so move them into xen/Rules.mk. Lay them out a little more neatly too. Signed-off-by: Tim Deegan <tim@xen.org> Reviewed-by: Jan Beulich <jbeulich@suse.com> Acked-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* x86/time: fix check for negative time in __update_vcpu_system_time()Tim Deegan2013-08-151-1/+2
| | | | | | Clang points out that u64 stime variable is always >= 0. Signed-off-by: Tim Deegan <tim@xen.org>
* x86/MTRR: fix range check in mtrr_add_page()Jan Beulich2013-08-141-1/+1
| | | | | | | | | Extracted from Yinghai Lu's Linux commit d5c78673 ("x86: Fix /proc/mtrr with base/size more than 44bits"). Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* x86: use "R" constraint for fxsaveq/fxrstorq enforcementJan Beulich2013-08-141-3/+2
| | | | | | | | | | I became aware of this constraint's (referring to all legacy registers in one go) existence by (accidentally) noticing Linux commit 82024135 ("x86-64, fpu: Simplify constraints for fxsave/fxtstor"). Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* VT-d: protect against bogus information coming from BIOSJan Beulich2013-08-142-0/+6
| | | | | | | | | | | | | Add checks similar to those done by Linux: The DRHD address must not be all zeros or all ones (Linux only checks for zero), and capabilities as well as extended capabilities must not be all ones. Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Ben Guthro <benjamin.guthro@citrix.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Tested-by: Ben Guthro <benjamin.guthro@citrix.com> Acked by: Yang Zhang <yang.z.zhang@intel.com> Acked-by: Xiantao Zhang <xiantao.zhang@intel.com>
* VMX: add boot parameter to enable/disable APIC-v dynamicallyYang Zhang2013-08-131-2/+5
| | | | | | | Add a boot parameter to enable/disable the APIC-v dynamically. APIC-v is enabled by default. User can use apicv=0 to disable it. Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com>
* watchdog/crash: Always disable watchdog in console_force_unlock()Andrew Cooper2013-08-132-2/+1
| | | | | | | | | | | | | | | | | | | | | | Depending on the state of the conring and serial_tx_buffer, console_force_unlock() can be a long running operation, usually because of serial_start_sync() XenServer testing has found a reliable case where console_force_unlock() on one PCPU takes long enough for another PCPU to timeout due to the watchdog (such as waiting for a tlb flush callin). The watchdog timeout causes the second PCPU to repeat the console_force_unlock(), at which point the first PCPU typically fails an assertion in spin_unlock_irqrestore(&port->tx_lock) (because the tx_lock has been unlocked behind itself). console_force_unlock() is only on emergency paths, so one way or another the host is going down. Disable the watchdog before forcing the console lock to help prevent having pcpus completing with each other to bring the host down. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* x86/watchdog: Tweak implementation given new common codeAndrew Cooper2013-08-131-2/+1
| | | | | Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* watchdog: Move watchdog from being x86 specific to common codeAndrew Cooper2013-08-1312-10/+51
| | | | | | | | | | | | | | | Augment watchdog_setup() to be able to possibly return an error, and introduce watchdog_enabled() as a better alternative to knowing the architectures internal details. This patch does not change the x86 implementaion, beyond making it compile. For header files, some includes of xen/nmi.h were only for the watchdog functions, so are replaced rather than adding an extra include of xen/watchdog.h Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* x86/AMD: Inject #GP instead of #UD when unable to map vmcbSuravee Suthikulpanit2013-08-132-11/+15
| | | | | | | | | | According to AMD Programmer's Manual vol2, vmrun, vmsave and vmload should inject #GP instead of #UD when unable to access memory location for vmcb. Also, the code should make sure that L1 guest EFER.SVME is not zero. Otherwise, #UD should be injected. Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Reviewed-by: Tim Deegan <tim@xen.org>
* x86/AMD: Fix nested svm crash due to assertion in __virt_to_maddrSuravee Suthikulpanit2013-08-132-13/+50
| | | | | | | | | Fix assertion in __virt_to_maddr when starting nested SVM guest in debug mode. Investigation has shown that svm_vmsave/svm_vmload make use of __pa() with invalid address. Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Reviewed-by: Tim Deegan <tim@xen.org>
* xen: arm: document which hypercalls (and subops) are supported on ARMIan Campbell2013-08-081-2/+64
| | | | | | | | | | | There are many hypercalls which make no sense or which are not supported on ARM systems but it's not all that obvious which ones we do support. So lets try and document the hypercalls which are useful on ARM. I'm not sure this is the best way to go about this, I'm open to other ideas. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Tim Deegan <tim@xen.org>?
* cleanup unused request{_dt,}_irq() parameterAndrew Cooper2013-08-089-12/+11
| | | | | | | | | The irqflags parameter appears to be an unused vestigial parameter right from the integration of the IOMMU code in 2007. The parameter is 0 at all callsites and never used. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Ian Campbell <Ian.Campbell@citrix.com>
* Revert "xen/arm: Add support for device tree specified arch_timer clock ↵Ian Campbell2013-08-081-6/+1
| | | | | | | | | frequency." This reverts commit dd11cc89c5ba53ae8d969037eda8b8c70d20ffa6. Broke the build due to dt_property_read_u32 being defined in an as yet unapplied patch.
* Merge branch 'staging' of ssh://xenbits.xen.org/home/xen/git/xen into stagingIan Campbell2013-08-088-96/+317
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| * mem_sharing_nominate_page: p2mt should never change before p2m_change_type()Nai Xia2013-08-081-14/+2
| | | | | | | | | | | | | | | | | | | | | | The p2mt change check for p2m_change_type() was first introduced when this code path was not protected by p2m_lock(). Now this code path is protected by p2m_lock. So p2mt should never change before p2m_change_type(). Signed-off-by: Nai Xia <nai.xia@gmail.com> Acked-by: Andres Lagar-Cavilla <andres@lagarcavilla.org> Acked-by: Tim Deegan <tim@xen.org>
| * pciif: add multi-vector-MSI commandJan Beulich2013-08-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | The requested vector count is to be passed in struct xen_pci_op's info field. Upon failure, if a smaller vector count might work, the backend will pass that smaller count in the value field (which so far is always being set to zero in the error path). Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
| * x86: enable multi-vector MSIJan Beulich2013-08-086-82/+314
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This implies - extending the public interface to have a way to request a block of MSIs - allocating a block of contiguous pIRQ-s for the target domain (but note that the Xen IRQs allocated have no need of being contiguous) - repeating certain operations for all involved IRQs - fixing multi_msi_enable() - adjusting the mask bit accesses for maskable MSIs Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* | pl011: Implement vuart_info callbackJulien Grall2013-08-081-0/+15
| | | | | | | | | | Signed-off-by: Julien Grall <julien.grall@linaro.org> Reviewed-by: Tim Deegan <tim@xen.org>
* | exynos4210: Implement vuart_info callbackJulien Grall2013-08-082-0/+16
| | | | | | | | | | Signed-off-by: Julien Grall <julien.grall@linaro.org> Reviewed-by: Tim Deegan <tim@xen.org>
* | exynos4210: rename UTRSTAT_TX_EMPTY in UTRSTAT_TXFEJulien Grall2013-08-082-2/+2
| | | | | | | | | | Signed-off-by: Julien Grall <julien.grall@linaro.org> Reviewed-by: Tim Deegan <tim@xen.org>
* | xen/arm: Implement a virtual UARTJulien Grall2013-08-088-172/+176
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This code is based on the previous vuart0 implementation. Unlike the latter, it's intend to replace UART stolen by XEN to DOM0 via dtuart=... on its command line. It's useful when the kernel is compiled with early printk enabled or for a single platform. Most of the time, the hardcoded code to handle the UART will need 2 registers: status and data, the others registers can be implemented as RAZ/WI. This commit will also drop support of early printk (based on vexpress pl011) in the guest. Signed-off-by: Julien Grall <julien.grall@linaro.org> Reviewed-by: Tim Deegan <tim@xen.org>
* | xen/arm: New callback in uart_driver to retrieve serial informationJulien Grall2013-08-082-0/+21
| | | | | | | | | | | | | | | | | | | | There is no way to retrieve basic informations (base address, size, ....) for an UART. This callback will be used later to partially emulate the real UART for DOM0 on ARM. Signed-off-by: Julien Grall <julien.grall@linaro.org> Reviewed-by: Tim Deegan <tim@xen.org> Acked-by: Keir Fraser <keir@xen.org>
* | libelf: Fix typo in header guard macroPatrick Welche2013-08-081-2/+2
| | | | | | | | | | | | | | | | s/__LIBELF_PRIVATE_H_/__LIBELF_PRIVATE_H__/ Signed-off-by: Patrick Welche <prlw1@cam.ac.uk> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* | xen/arm: Add support for device tree specified arch_timer clock frequency.Chen Baozi2013-08-081-1/+6
|/ | | | | Signed-off-by: Chen Baozi <baozich@gmail.com> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* Intel/VPMU: Add support for full-width PMC writesBoris Ostrovsky2013-08-072-6/+37
| | | | | | | | | | | A recent Linux commit (069e0c3c405814778c7475d95b9fff5318f39834) added support for full-width PMC writes to performance counter registers, making these registers default for perf. Since current Xen VPMU does not support these new MSRs perf will fail to initialise in guests. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com> Acked-by: Keir Faser <keir@xen.org>
* xen/conring: Write to console ring even if console lock is bustedAndrew Cooper2013-08-061-3/+2
| | | | | | | | | | | | | | | | | | console_lock_busted gets set when an NMI/MCE/Double Fault handler decides to bring Xen down in an emergency. conring_puts() cannot block and does not have problematic interactions with the console_lock. Therefore, choosing to not put the string into the console ring simply means that the kexec environment cant find any panic() message caused by an IST interrupt, which is unhelpful for debugging purposes. In the case that two pcpus fight with console_force_unlock(), having slightly garbled strings in the console ring is far more useful than having nothing at all. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Matt Wilson <msw@amazon.com> Acked-by: Keir Fraser <keir@xen.org>
* xen/conring: Clean up writing to the console ringAndrew Cooper2013-08-061-9/+10
| | | | | | | | | | | | Refactor putchar_console_ring() to conring_puts(). This allows for consistency with {sercon,vga}_puts(), prevents needless recalculation of the conring consumer index, and slight cleanup at the two callsites. There is no functional change. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Matt Wilson <msw@amazon.com> Acked-by: Keir Fraser <keir@xen.org>
* Nested VMX: Flush TLBs and Caches if paging mode changedYang Zhang2013-08-061-0/+1
| | | | | | | | | According to SDM, if paging mode is changed, then whole TLBs and caches will be flushed. This is missed in nested handle logic. Also this fixed the issue that 64 bits windows cannot boot up on top of L1 kvm. Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com> Acked-by: Keir Fraser <keir@xen.org>
* x86: refine FPU selector handling code for XSAVEOPTJan Beulich2013-08-051-0/+25
| | | | | | | | | | Some extra tweaks are necessary to deal with the situation of XSAVEOPT not writing the FPU portion of the save image (due to it detecting that the register state did not get modified since the last XRSTOR). Signed-off-by: Jan Beulich <jbeulich@suse.com> Tested-by: Ben Guthro <ben.guthro@gmail.com> Acked-by: Keir Fraser <keir@xen.org>
* fix off-by-one mistakes in vm_alloc()Jan Beulich2013-08-051-10/+18
| | | | | | | | | | | Also add another pair of assertions to catch eventual further cases of incorrect accounting, and remove the temporary debuggin messages again which commit 68caac7f ("x86: don't use destroy_xen_mappings() for vunmap()") added. Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* xen/arm: Use define instead of hardcoded value in debug-pl011Julien Grall2013-08-052-8/+11
| | | | | Signed-off-by: Julien Grall <julien.grall@linaro.org> Reviewed-by: Tim Deegan <tim@xen.org>
* pl011: Move registers' definition in a separate fileJulien Grall2013-08-052-47/+81
| | | | | Signed-off-by: Julien Grall <julien.grall@linaro.org> Reviewed-by: Tim Deegan <tim@xen.org>
* pl011: Use ioreadl/iowritelJulien Grall2013-08-051-38/+42
| | | | | Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* scmversion: 'Improve' svn interaction.Andrew Cooper2013-08-021-10/+1
| | | | | | | | | | | Xen has never been in an svn tree, and the current code will unconditionally create a .svn directory when run from a tarball. Therefore, simply discard the svn support. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* xen: arm: handle traps of conditional instructions.Ian Campbell2013-08-022-24/+145
| | | | | | | | | | | | | This means handling the HSR.ccvalid field as well as correctly processing the Thumb If-Then state block in the CPSR correctly which is rather tricky. KVM provided a useful reference for all this. I suspect we aren't actually hitting these paths very often since the sorts of traps we take will not often be conditional so my limited testing may not actually be exercising these paths very much. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Julien Grall <julien.linaro.org>
* xen: arm: do not pretend to be a Cortex-A15 when running 32-bit guestsIan Campbell2013-08-021-3/+0
| | | | | | | | | | It is definitely wrong to do this when running on non-Cortex-A15 32-bit hardware but even when running on 64-bit hardware it's not really necessary and may cause more harm than good if the underlying processor is not all that similar to an A15. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Julien Grall <julien.grall@linaro.org>
* stubdom: Fix stubdom undeclared function build warningsSamuel Thibault2013-08-021-0/+2
| | | | | | | | | | | This includes a few headers to fix some missing function declarations. ../grub-upstream/stage2/builtins.c:1728:3: warning: implicit declaration of function ‘do_exit’ [-Wimplicit-function-declaration] stubdom/include/xen/libelf/libelf.h:453:5: warning: implicit declaration of function ‘memcpy’ [-Wimplicit-function-declaration] Reported-by: IAN DELANEY <della5@iinet.com.au> Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* xen/arm: Fix guest secondaries CPU boot after bcac10fJulien Grall2013-07-303-4/+14
| | | | | | | | | | | The commit bcac10f "xen: arm: support building a 64-bit dom0 domain" breaks secondary cpus boot for all the guest. Linux requires CPUs to boot on SVC mode. Divide PSR_GUEST_INIT in 2 distinct defines: one for 32 bit, the other for 64 bits guests. Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* Merge branch 'staging' of ssh://xenbits.xen.org/home/xen/git/xen into stagingIan Campbell2013-07-293-14/+3
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| * Don't take the domain lock for p2m operations.Tim Deegan2013-07-293-14/+3
| | | | | | | | | | | | | | | | | | | | P2M ops are covered by their own locks, and these uses of the domain lock are relics of shadow-v1 code. Signed-off-by: Tim Deegan <tim@xen.org> Reviewed-by: Andres Lagar-Cavilla <andres@lagarcavilla.org> Acked-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* | xen: arm: Handle SMC from 64-bit guestsIan Campbell2013-07-293-9/+48
| | | | | | | | | | | | | | | | Similarly to arm32 guests handle it by injecting an undefined instruction trap. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Tim Deegan <tim@xen.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-12 20:30:28 +0000