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| author | Jan Beulich <jbeulich@suse.com> | 2013-08-14 11:19:45 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2013-08-14 11:19:45 +0200 |
| commit | 78742c233c664cac6cac8405c154f82239ab6995 (patch) | |
| tree | 06ee3cfccb6568951d6f6a3aaf51c516c9a67d23 /xen | |
| parent | e8e8b030ecf916fea19639f0b6a446c1c9dbe174 (diff) | |
| download | xen-78742c233c664cac6cac8405c154f82239ab6995.tar.gz xen-78742c233c664cac6cac8405c154f82239ab6995.tar.bz2 xen-78742c233c664cac6cac8405c154f82239ab6995.zip | |
x86: use "R" constraint for fxsaveq/fxrstorq enforcement
I became aware of this constraint's (referring to all legacy registers
in one go) existence by (accidentally) noticing Linux commit 82024135
("x86-64, fpu: Simplify constraints for fxsave/fxtstor").
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
Acked-by: Keir Fraser <keir@xen.org>
Diffstat (limited to 'xen')
| -rw-r--r-- | xen/arch/x86/i387.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/xen/arch/x86/i387.c b/xen/arch/x86/i387.c index bd162a8e1e..1230a527b7 100644 --- a/xen/arch/x86/i387.c +++ b/xen/arch/x86/i387.c @@ -96,8 +96,7 @@ static inline void fpu_fxrstor(struct vcpu *v) ".previous \n" _ASM_EXTABLE(1b, 2b) : - : "m" (*fpu_ctxt), "i" (sizeof(*fpu_ctxt) / 4), - "cdaSDb" (fpu_ctxt) ); + : "m" (*fpu_ctxt), "i" (sizeof(*fpu_ctxt) / 4), "R" (fpu_ctxt) ); break; case 4: case 2: asm volatile ( @@ -162,7 +161,7 @@ static inline void fpu_fxsave(struct vcpu *v) * addressing mode that doesn't require extended registers. */ asm volatile ( REX64_PREFIX "fxsave (%1)" - : "=m" (*fpu_ctxt) : "cdaSDb" (fpu_ctxt) ); + : "=m" (*fpu_ctxt) : "R" (fpu_ctxt) ); /* * AMD CPUs don't save/restore FDP/FIP/FOP unless an exception |