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* xen: remove more declarations from C files.Tim Deegan2011-05-271-0/+1
| | | | | | | | | | This patch moves some more, mostly data, extern declarations into header files. I haven't been as strict as I was with functions; in particular there are a number of declarations of assembler labels that are only used in one place. I've also left a few compat-mode tricks, and all the magic in symbols.c Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com>
* x86 hvm: Fix MTRR physaddr-width check.Keir Fraser2010-11-091-2/+3
| | | | | | | Should be checking against physaddr width presented to teh guest, rather than the host physaddr width. Signed-off-by: Keir Fraser <keir@xen.org>
* VMX: cleanup ept_set_entry:Keir Fraser2010-07-021-1/+1
| | | | | | | | | 1) more strict input parameters checking; 2) better comments; 3) fewer variable; 4) change direct_mmio type to bool_t. Signed-off-by: Xin Li <xin.li@intel.com>
* mtrr msr-handling cleanupKeir Fraser2010-06-111-4/+2
| | | | Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
* x86: Intel EPT entry structure changes.Keir Fraser2010-02-041-1/+1
| | | | | | | | | - Intel SDM defines bit6 in EPT page table entry as "Ignore PAT memory type", so change the abbreviation from "igmt" to "ipat". - Change the mfn and avail2 fields according to SDM definition. Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com>
* Scattered code arrangement cleanups.Keir Fraser2009-10-071-0/+10
| | | | | | | | - remove redundant declarations - add/move prototypes to headers - move things where they belong to Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
* ept: code clean up and formatting.Keir Fraser2009-08-061-3/+2
| | | | | | | Fix alignment and comments and add and remove spaces and lines where appropriate. Signed-off-by: Patrick Colp <Patrick.Colp@citrix.com>
* ept mtrr: replace unsigned long with mfn_t for mfns.Keir Fraser2009-08-061-1/+2
| | | | Signed-off-by: Patrick Colp <Patrick.Colp@citrix.com>
* x86: CPU synchronization while doing MTRR register updateKeir Fraser2009-08-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | The current Xen code does not synchronize all the cpus while initializing MTRR registers when a cpu comes up.=20 As per IA32 SDM vol 3: Section: 10.11.8 MTRR Considerations in MP Systems, all the processors should be synchronized while updating MTRRs. Processors starting with westmere are caching VMCS data for better VMX performance. These processors also has Hyper-threading support. With hyper-threading, when one thread's cache is disabled, it also disables cache for the sibling threads. And MTRR register updating procedure involves cache disabling. So if cpus are not synchronized, updating MTRR registers on a thread, results in the VMCS data from sibling threads becoming inaccessible, and it causes system failure. With this patch while updating the MTRR registers, all the cpus are synchronized as per the IA32 SDM. Also at the boot time and resume time when multiple cpus are brought up, an optimization is added to delay the MTRR initialization until all the cpus are up, to avoid multiple times cpu synchronization. Signed-off-by: Nitin A Kamble <nitin.a.kamble@intel.com> Signed-off-by: Suresh B Siddha <suresh.b.siddha@intel.com> Signed-off-by: Asit K Mallick <asit.k.mallick@intel.com>
* [VTD] Utilise the snoop control capability in shadow with VT-d codeKeir Fraser2009-02-201-1/+2
| | | | | | | | | | | | | We compute the shadow PAT index in leaf page entries now as: 1) No VT-d assigned: let shadow PAT index as WB, handled already in shadow code before. 2) direct assigned MMIO area: let shadow code compute the shadow PAT with gMTRR=UC and gPAT value. 3) Snoop control enable: let shadow PAT index as WB. 4) Snoop control disable: let shadow code compute the shadow PAT with gMTRR and gPAT, handled already in shadow code before Signed-off-by: Xin, Xiaohui <xiaohui.xin@intel.com>
* EPT/VT-d: Enhance MTRR/PAT virtualization when EPT/VT-d both enabledKeir Fraser2009-01-231-3/+5
| | | | | | | | Set effective memory type for EPT according to the VT-d snoop control capability, and also includes some cleanups for EPT & VT-d both enabled. Signed-off-by: Edwin Zhai <Edwin.Zhai@intel.com> Signed-off-by: Xiaohui Xin <xiaohui.xin@intel.com>
* MTRR virtualization for Intel EPTKeir Fraser2008-07-071-0/+3
| | | | Signed-off-by: Xiaohui Xin <xiaohui.xin@intel.com>
* Clean up shadow code after the removal of non-PAE 32-bit buildsKeir Fraser2008-05-081-0/+3
| | | | Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com>
* x86, hvm: Lots of MTRR/PAT emulation cleanup.Keir Fraser2008-04-161-8/+0
| | | | | | | | | | - Move MTRR MSR initialisation into hvmloader. - Simplify initialisation logic by overlaying UC on default WB rather than vice versa. - Clean up hypervisor HVM MTRR/PAE code's interface with rest of hypervisor. Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* hvm: MTRR MSRs save/restore support.Keir Fraser2007-12-121-0/+1
| | | | Signed-off-by: Disheng Su <disheng.su@intel.com>
* hvm/x86: MTRR/PAT virtualisation.Keir Fraser2007-10-221-0/+49
| | | | Signed-off-by: Disheng Su <disheng.su@intel.com>
* x86: AMD Fam10/11 adjustmentsKeir Fraser2007-10-111-0/+2
| | | | | | | Signed-off-by: Jan Beulich <jbeulich@novell.com> Sync up affected files with 2.6.23-rc9. Signed-off-by: Keir Fraser <keir@xensource.com>
* bitkeeper revision 1.1159.187.32 (41aaf567IYxx6S0v45_yrK6nVpncuA)kaf24@scramble.cl.cam.ac.uk2004-11-291-0/+22
Pull Linux MTRR driver into Xen. This ensures that MTRRs are consistent across all CPUs at boot time. We still need to export MTRR setting via the control interface, and virtualise the XenLinux MTRR driver.
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