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* x86/HVM: cache emulated instruction for retry processingJan Beulich2013-10-141-0/+3
| | | | | | | | | | | | | Rather than re-reading the instruction bytes upon retry processing, stash away and re-use what we already read. That way we can be certain that the retry won't do something different from what requested the retry, getting once again closer to real hardware behavior (where what we use retries for is simply a bus operation, not involving redundant decoding of instructions). Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* x86/HVM: fix direct PCI port I/O emulation retry and error handlingJan Beulich2013-10-141-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | dpci_ioport_{read,write}() guest memory access failure handling should be modelled after process_portio_intercept()'s (and others): Upon encountering an error on other than the first iteration, the count successfully handled needs to be stored and X86EMUL_OKAY returned, in order for the generic instruction emulator to update register state correctly before reporting failure or retrying (both of which would only happen after re-invoking emulation). Further we leverage (and slightly extend, due to the above mentioned need to return X86EMUL_OKAY) the "large MMIO" retry model. Note that there is still a special case not explicitly taken care of here: While the first retry on the last iteration of a "rep ins" correctly recovers the already read data, an eventual subsequent retry is being handled by the pre-existing mmio-large logic (through hvmemul_do_io() storing the [recovered] data [again], also taking into consideration that the emulator converts a single iteration "ins" to ->read_io() plus ->write()). Also fix an off-by-one in the mmio-large-read logic, and slightly simplify the copying of the data. Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* x86: Implement TSC adjust feature for HVM guestLiu, Jinsong2012-09-261-0/+1
| | | | | | | | | | | | | | | | | | | IA32_TSC_ADJUST MSR is maintained separately for each logical processor. A logical processor maintains and uses the IA32_TSC_ADJUST MSR as follows: 1). On RESET, the value of the IA32_TSC_ADJUST MSR is 0; 2). If an execution of WRMSR to the IA32_TIME_STAMP_COUNTER MSR adds (or subtracts) value X from the TSC, the logical processor also adds (or subtracts) value X from the IA32_TSC_ADJUST MSR; 3). If an execution of WRMSR to the IA32_TSC_ADJUST MSR adds (or subtracts) value X from that MSR, the logical processor also adds (or subtracts) value X from the TSC. This patch provides tsc adjust support for hvm guest, with it guest OS would be happy when sync tsc. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* x86/hvm: increase struct hvm_vcpu_io's mmio_large_read[]Jan Beulich2012-06-281-4/+4
| | | | | | | | | | | Since the emulator now supports a few 256-bit memory operations, this array needs to follow (and the comments should, too). To limit growth, re-order the mmio_large_write_* fields so that the two mmio_large_*_bytes fields end up adjacent to each other. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* xen: Define new struct hvm_trap and cleanup vmx exceptionKeir Fraser2012-05-301-4/+3
| | | | | | | | | | Define new struct hvm_trap to represent information of trap, and renames hvm_inject_exception to hvm_inject_trap, then define a couple of wrappers around that function for existing callers. Signed-off-by: Keir Fraser <keir@xen.org> Signed-off-by: Xudong Hao <xudong.hao@intel.com> Committed-by: Keir Fraser <keir@xen.org>
* hvm: Clean up I/O emulationChristoph Egger2011-10-251-21/+25
| | | | | | | | Move HVM io fields into a structure. On MMIO instruction failure print out some more bytes. Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> Committed-by: Keir Fraser <keir@xen.org>
* x86/hvm: Tidy up the viridian code a little and flesh out the APICPaul Durrant2011-09-171-0/+3
| | | | | | | | | | | assist MSR handling code. We don't say we that handle that MSR but Windows assumes it. In Windows 7 it just wrote to the MSR and we used to handle that ok. Windows 8 also reads from the MSR so we need to keep a record of the contents. Signed-off-by: Paul Durrant <paul.durrant@citrix.com>
* Nested VMX: Add data structure for nestedvmxEddie Dong2011-06-091-0/+2
| | | | | | | Signed-off-by: Qing He <qing.he@intel.com> Signed-off-by: Eddie Dong <eddie.dong@intel.com> Acked-by: Tim Deegan <Tim.Deegan@citrix.com> Committed-by: Tim Deegan <Tim.Deegan@citrix.com>
* nestedhvm: Allocate a separate host ASID for each L2 VCPU.Keir Fraser2011-04-151-2/+8
| | | | | | | This avoids TLB flushing on every L1/L2 transition. Signed-off-by: Keir Fraser <keir@xen.org> Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
* x86/hvm/asid: Use C99 integer types for asid numbersChristoph Egger2011-04-131-2/+2
| | | | Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
* Implement SVM specific part for Nested Virtualizationcegger2011-03-091-0/+2
| | | | | | Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> Acked-by: Tim Deegan <Tim.Deegan@citrix.com> Committed-by: Tim Deegan <Tim.Deegan@citrix.com>
* Data structures for Nested Virtualizationcegger2011-02-281-0/+34
| | | | | | | Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> Acked-by: Eddie Dong <eddie.dong@intel.com> Acked-by: Tim Deegan <Tim.Deegan@citrix.com> Committed-by: Tim Deegan <Tim.Deegan@citrix.com>
* mem_access: added INT3/CRx captureJoe Epstein2011-01-071-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | * Allows a memory event listener to register for events on changes to CR0, CR3, and CR4, as well as INT3 instructions, as a part of the mem_access mechanism. These events can be either synchronous or asynchronous. * For INT3, the logic works independent of a debugger, and so both can be supported. * The presence and type of listener are stored and accessed through HVM params. * Changed the event mask handling to ensure that the right events are captured based on the listeners. * Added the ability to inject HW/SW traps into a VCPU when it next resumes (rather than try to modify the existing IRQ injection code paths). Only one trap to inject can be outstanding at a time. Signed-off-by: Joe Epstein <jepstein98@gmail.com> Acked-by: Keir Fraser <keir@xen.org> Acked-by: Tim Deegan <Tim.Deegan@citrix.com>
* x86 hvm: Make a couple of hypercall state flags per-vcpuKeir Fraser2010-11-161-0/+3
| | | | | | | This is a prerequisite for allowing guest descheduling within a hypercall. Signed-off-by: Keir Fraser <keir@xen.org>
* x86: Xsave support for PV guests.Keir Fraser2010-11-031-9/+0
| | | | | Signed-off-by: Shan Haitao <haitao.shan@intel.com> Signed-off-by: Han Weidong <weidong.han@intel.com>
* x86: Clean up existing XSAVE supportKeir Fraser2010-10-291-1/+1
| | | | | Signed-off-by: Han Weidong <weidong.han@intel.com> Signed-off-by: Shan Haitao <haitao.shan@intel.com>
* x86 hvm: Clean up PIO fast path emulation.Keir Fraser2010-09-151-3/+2
| | | | Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* VPMU: Make vpmu stucture visiable for both vmx and svmKeir Fraser2010-05-131-0/+3
| | | | Signed-off-by: Wei Wang <wei.wang2@amd.com>
* Move tasklet implementation into its own source files.Keir Fraser2010-04-191-0/+1
| | | | | | | | This is preparation for implementing tasklets in vcpu context rather than softirq context. There is no change to the implementation of tasklets in this patch. Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86/hvm: accelerate I/O intercept handlingKeir Fraser2010-03-311-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | currently we go through the emulator every time a HVM guest does an I/O port access (in/out). This is unnecessary most of the times, as both VMX and SVM provide all the necessary information already in the VMCS/VMCB. String instructions are not covered by this shortcut, but they are quite rare and we would need to access the guest memory anyway. This patch decodes the information from VMCB/VMCS and calls a simple handle_mmio wrapper. In handle_mmio() itself the emulation part will simply be skipped, this approach avoids code duplication. Since the vendor specific part is quite trivial, I implemented both the VMX and SVM part, please check the VMX part for sanity. I boot-tested both versions and ran some simple benchmarks. A micro benchmark (hammering an I/O port in a tight loop) shows a significant performance improvement (down to 66% of the time needed to handle the intercept on an AMD K8, measured in the guest with TSC). Even with reading a 1GB file from an emulated IDE harddisk (Dom0 cached) I could get a 4-5% improvement. Some guest code (e.g. the TCP stack in some Windows version) exercises the PM-Timer I/O port (0x1F48) very often (multiple 10,000 times per second), these workloads also benefit with up to 5% improvement from this patch. Signed-off-by: Andre Przywara <andre.przywara@amd.com>
* hvm: Clean up RDTSCP/TSC_AUX handling.Keir Fraser2009-12-161-0/+2
| | | | Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* hvm: Pull SVM ASID management into common HVM code where it can be shared.Keir Fraser2009-12-081-0/+3
| | | | Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* vmx: add the support of XSAVE/XRSTOR to VMX guestKeir Fraser2009-09-291-0/+9
| | | | | | | | | | | | | | | XSAVE/XRSTOR manages the existing and future processor extended states on x86 architecture. The XSAVE/XRSTOR infrastructure is defined in Intel SDMs: http://www.intel.com/products/processor/manuals/ The patch uses the classical CR0.TS based algorithm to manage the states on context switch. At present, we know 3 bits in the XFEATURE_ENABLED_MASK: FPU, SSE and YMM. YMM is defined in Intel AVX Programming Reference: http://software.intel.com/sites/avx/ Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
* x86 hvm: hvm_set_callback_irq_level() must not be called in IRQKeir Fraser2009-05-081-0/+2
| | | | | | | context or with IRQs disabled. Ensure this by deferring to tasklet (softirq) context if required. Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86: Enable MTF for HVM guest single step in gdbKeir Fraser2008-12-161-0/+1
| | | | | Signed-off-by: Edwin Zhai <edwin.zhai@intel.com> Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* hvm: Build guest timers on monotonic system time.Keir Fraser2008-05-241-0/+3
| | | | | | | | | | Move hvm platform timers from underlying physical CPU TSC to Xen system time and ensure domain-wide monotonicity. TSC on many systems may skew between processors leading to 'time going backwards' messages from some guests. Signed-off-by: Dan Magenheimer <dan.magenheimer@oracle.com> Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86, hvm: Allow emulation of 'multi-cycle' MMIO reads and writes,Keir Fraser2008-04-171-2/+8
| | | | | | which may require multiple round trips to the device model. Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86_emulate: Implement a more dynamic interface for handling FPUKeir Fraser2008-04-161-0/+3
| | | | | | exceptions, which will allow emulation stubs to be built dynamically in a future patch. Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86, hvm: Clean up handling of APIC INIT and SIPI messages.Keir Fraser2008-04-151-6/+0
| | | | Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86_emulate: On HVM MMIO emulation, cache the gva->pfn mapping for theKeir Fraser2008-03-271-0/+9
| | | | | MMIO page. Speeds up Windows installation by about 20 percent. Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86_emulate: Clean up HVM emulated I/O handling.Keir Fraser2008-03-261-3/+9
| | | | Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86 hvm: More emulation simplifications.Keir Fraser2008-02-221-5/+0
| | | | Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86 hvm: Replace old MMIO emulator with x86_emulate()-based harness.Keir Fraser2008-02-201-3/+6
| | | | | Re-factor VMX real-mode emulation to use the same harness. Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* vmx realmode: Plumb through I/O port accesses in emulated realmode.Keir Fraser2007-11-251-0/+3
| | | | Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* hvm/x86: MTRR/PAT virtualisation.Keir Fraser2007-10-221-0/+7
| | | | Signed-off-by: Disheng Su <disheng.su@intel.com>
* hvm: Always keep canonical copy of RIP/RSP/RFLAGS inkfraser@localhost.localdomain2007-09-191-1/+1
| | | | | | | guest_cpu_user_regs(). Reduces complexity at little or no performance cost (except on really old Intel P4 hardware where VMREAD/VMWRITE are silly expensive). Signed-off-by: Keir Fraser <keir@xensource.com>
* hvm: Remove hvm-specific NMI flag and use generic flag instead.kfraser@localhost.localdomain2007-09-061-3/+0
| | | | Signed-off-by: Keir Fraser <keir@xensource.com>
* hvm: Handle hw_cr[] array a bit more sanely.kfraser@localhost.localdomain2007-08-081-1/+6
| | | | | | SVM for the most part does not need to use it at all, and this makes the code clearer. Signed-off-by: Keir Fraser <keir@xensource.com>
* hvm: Unify %cr0 handling.kfraser@localhost.localdomain2007-08-081-5/+1
| | | | Signed-off-by: Keir Fraser <keir@xensource.com>
* hvm: Clean up control-register and EFER handling.kfraser@localhost.localdomain2007-08-071-1/+11
| | | | | No semantic changes. :-) Signed-off-by: Keir Fraser <keir@xensource.com>
* hvm: Support injection of virtual NMIs and clean up ExtInt handling in general.kfraser@localhost.localdomain2007-06-201-1/+3
| | | | Signed-off-by: Keir Fraser <keir@xensource.com>
* hvm: Add locking to platform timers.Keir Fraser2007-06-151-0/+3
| | | | | Handy for correctness. Signed-off-by: Keir Fraser <keir@xensource.com>
* hvm: Clean up handling of exception intercepts.Keir Fraser2007-03-281-2/+2
| | | | | Only intercept #DB/#BP if a debugger is attached. Signed-off-by: Keir Fraser <keir@xensource.com>
* [xentrace][HVM] introduce HVM tracing to unify SVM and VMX tracingkfraser@localhost.localdomain2007-02-261-2/+0
| | | | | | | | | | | | | | * new tracing class TRC_HVM replacing TRC_VMX * 20 new trace events to differentiate the information carried by them ** added corresponding trace points in SVM and VMX code ** updated formats file: descriptive formatting of trace event data ** completely replacing previous simple tracing in VMX * possibility to toggle single events on and off at compile time in include/asm-x86/hvm/trace.h Signed-off-by: Thomas Friebel <thomas.friebel@amd.com>
* [HVM] Enable more than one platform timer (PIT/RTC/HPET)kfraser@localhost.localdomain2006-12-201-0/+1
| | | | | | | | | | | programmed as periodic timer and adds them to abstract layer, which keeps track of pending_intr_nr to avoid time interrupt lost and sync'ed timer with TSC. It also makes some cleanup to the time related code. Signed-off-by: Xiaowei Yang <xiaowei.yang@intel.com> Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
* [HVM] Remove HVM halt timer. It's no longer needed since interruptskfraser@localhost.localdomain2006-11-101-3/+0
| | | | | | can wake it up now. Signed-off-by: Xin Li <xin.b.li@intel.com>
* [HVM] VLAPIC cleanups. vlapic tsruct is statically containedkfraser@localhost.localdomain2006-11-071-1/+1
| | | | | inside the vcpu structure. Signed-off-by: Keir Fraser <keir@xensource.com>
* Enhance HVM xentrace:kfraser@localhost.localdomain2006-11-071-0/+2
| | | | | | | 1) VMX xentrace data are store in current vcpu instead physical CPU. 2) Log PIO data in xentrace. Signed-off-by: Xin Li <xin.b.li@intel.com>
* [XEN] Don't keep shadows of PAE guest l3 tables.Tim Deegan2006-10-171-5/+0
| | | | | | | | | | | Holding pages readonly that have guest PAE l3 tables in them means a performance hit and potential bug if the guest puts other datastructures on the same page as an l3 table. Instead of shadowing them, treat PAE guests as if they had four CR3 registers, and load all four top-level entries when we handle a CR3 write. This also cuts about 500 lines of special-case refcounting and re-copying code. Signed-off-by: Tim Deegan <Tim.Deegan@xensource.com>
* Replace shadow pagetable code with shadow2.tdeegan@york.uk.xensource.com2006-08-161-0/+6
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