aboutsummaryrefslogtreecommitdiffstats
path: root/xen/arch/x86/apic.c
Commit message (Collapse)AuthorAgeFilesLines
* x86: fix boot time APIC mode detectionJan Beulich2013-05-231-1/+1
| | | | | | | | | | | | | | | current_cpu_data becomes valid only relatively late in the boot process, so looking there for a particular feature early in the game would generally give the appearance of the feature being unavailable. Getting this wrong means that at kexec time the system would get returned to xAPIC mode, causing disconnect_bsp_APIC() to try to access the APIC page, which on systems with x2APIC pre-enabled will never get set up. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
* apic/iommu: Correct grammar in error message and clarify its meaningAndrew Cooper2013-05-031-2/+2
| | | | Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
* xen: Fix some over-long source lines.Keir Fraser2013-01-301-1/+1
| | | | Signed-off-by: Keir Fraser <keir@xen.org>
* x86: make cpu_2_logical_apicid private to x2apic codeJan Beulich2012-11-081-1/+0
| | | | | | | | ... as it in fact is only being used there. While moving it, also make it a per-CPU variable rather than a NR_CPUS-sized array. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* IOMMU: keep disabled until iommu_setup() is calledJan Beulich2012-11-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The iommu is enabled by default when xen is booting and later disabled in iommu_setup() when no iommu is present. But under some circumstances iommu code can be called before iommu_setup() is processed. If there is no iommu available xen crashes. This can happen for example when panic(...) is called as introduced with the patch "x86-64: detect processors subject to AMD erratum #121 and refuse to boot" since xen 4.1.3, resulting in find_iommu_for_device() to be called in the context of disable_IO_APIC() / __stop_this_cpu(). This patch fixes this by keeping the iommu disabled until iommu_setup() is entered. Originally-by: Ronny Hegewald <ronny.hegewald@online.de> In order for iommu_enable to be off initially, iommu_supports_eim() must not depend on it anymore, nor must acpi_parse_dmar(). The former in turn requires that iommu_intremap gets uncoupled from iommu_enabled (in particular, failure during IOMMU setup should no longer result in iommu_intremap getting cleared by generic code; IOMMU specific code can still do so provided in can live with the consequences). This could have the nice side effect of allowing to use "iommu=off" even when x2APIC was pre-enabled by the BIOS (in which case interrupt remapping is a requirement, but DMA translation [obviously] isn't), but that doesn't currently work (and hence x2apic_bsp_setup() forces the IOMMU on rather than just interrupt remapping). For consistency with VT-d, make the AMD IOMMU code also skip all ACPI table parsing when neither iommu_enable nor iommu_intremap are set. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Xiantao Zhang <xiantao.zhang@intel.com> Acked-by: "Huang2, Wei" <Wei.Huang2@amd.com>
* printk: prefer %#x et at over 0x%xJan Beulich2012-09-211-2/+2
| | | | | | | | | Performance is not an issue with printk(), so let the function do minimally more work and instead save a byte per affected format specifier. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* x86/hvm: don't use indirect calls without needJan Beulich2012-09-141-1/+1
| | | | | | | | Direct calls perform better, so we should prefer them and use indirect ones only when there indeed is a need for indirection. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* x86: adjust handling of interrupts coming in via legacy vectorsJan Beulich2012-05-151-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The debugging code added in c/s 24707:96987c324a4f was hit a (small) number of times (one report being http://lists.xen.org/archives/html/xen-devel/2012-05/msg00332.html), apparently always with a vector within the legacy range. Obviously, besides legacy vectors not normally expected to be in use on systems with IO-APIC(s), they should never make it to the IRQ migration logic. This wasn't being prevented so far: Since we don't have a one-to-one mapping between vectors and IRQs - legacy IRQs may have two vectors associated with them (one used in either 8259A, the other used in one of the IO-APICs) -, vector-to-IRQ translations for legacy vectors (as used in do_IRQ()) would yield a valid IRQ number despite the IRQ really being handled via an IO-APIC. This gets changed here - disable_8259A_irq() zaps the legacy vector-to- IRQ mapping, and enable_8259A_irq(), should it ever be called for a particular interrupts, restores it. The spurious interrupt logic in do_IRQ() gets adjusted too: Interrupts coming in via legacy vectors presumably didn't get reported through the IO-APIC/LAPIC pair (as we never program these vectors into any RTE or LVT). Call ack_APIC_irq() only when the LAPIC's ISR bit says an interrupt is pending at the given vector. Plus, a new function (pointer) bogus_8259A_irq() gets used to have the 8259A driver take care of the bogus interrupt (as outside of automatic EOI mode it may need an EOI to be issued for it to prevent other interrupts legitimately going through the 8259As from getting masked out). Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org> Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
* x86: Allow direct vectored interrupts to be dynamically allocated.Keir Fraser2012-03-301-8/+0
| | | | | | Use this for Intel's CMCI and thermal interrupts. Signed-off-by: Keir Fraser <keir@xen.org>
* x86: All vectored interrupts go through do_IRQ().Keir Fraser2012-03-301-56/+11
| | | | Signed-off-by: Keir Fraser <keir@xen.org>
* IO-APIC: Prevent using EOI broadcast suppression if user specified ↵Andrew Cooper2012-02-231-3/+9
| | | | | | | | | | | | | | | ioapic_ack=new on the command line. Currently, if EOI broadcast suppression is advertised on the BSP LAPIC, Xen will discard any user specified option regarding IO-APIC ack mode. This patch introduces a check which prevents EOI Broadcast suppression from forcing the IO-APIC ack mode to old if the user has explicitly asked for the new ack mode on the command line. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Committed-by: Keir Fraser <keir@xen.org>
* CONFIG: remove CONFIG_SMP #ifdefsAndrew Cooper2012-02-091-2/+1
| | | | | | | | CONFIG_SMP is always enabled and !CONFIG_SMP is not supported. So simplify the code a little by removing all #ifdefs. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Committed-by: Keir Fraser <keir@xen.org>
* x86: clean up physid_mask_t handlingJan Beulich2011-10-141-1/+2
| | | | | | | | | | | | | | | | This eliminates passing and returning by value of this type (making it unnecessary for the compiler to create temporary variables for doing so on the stack), thus dramatically reducing the stack frame sizes of a couple of functions (was in one case over 12k for a 4095-CPU build). In one case a local variable gets converted to a static one, possible because the function gets called at most once (during early boot). Some accessors get eliminated altogether as being unused or as being equally well open coded at the place of use. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* x86: add irq count for IPIsKevin Tian2011-08-311-0/+4
| | | | | | | | such count is useful to assist decision make in cpuidle governor, while w/o this patch only device interrupts through do_IRQ is currently counted. Signed-off-by: Kevin Tian <kevin.tian@intel.com>
* x86/apic: check maxlvt before accessing certain LVT fieldsJan Beulich2011-06-151-5/+9
| | | | | | | This follows Linux, including in not checking maxlvt for certain accesses to APIC_LVTERR. Signed-off-by: Jan Beulich <jbeulich@novell.com>
* KEXEC: correctly revert x2apic state when kexecingAndrew Cooper2011-06-151-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | Introduce the boolean variable 'kexecing' which indicates to functions whether we are on the kexec path or not. This is used by disable_local_APIC() to try and revert the APIC mode back to how it was found on boot. We also need some fudging of the x2apic_enabled variable. It is used in multiple places over the codebase to mean multiple things, including: What did the user specifify on the command line? Did the BIOS boot me in x2apic mode? Is the BSP Local APIC in x2apic mode? What mode is my Local APIC in? Therefore, set it up to prevent a protection fault when disabling the IOAPICs. (In this case, it is used in the "What mode is my Local APIC in?" case, so the processor doesnt suffer a protection fault because of trying to use x2apic MSRs when it should be using xapic MMIO) Finally, make sure that interrupts are disabled when jumping into the purgatory code. It would be bad to service interrupts in the Xen context when the next kernel is booting. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
* x86/apic: record local APIC state on bootAndrew Cooper2011-06-141-0/+62
| | | | | | | | | | Xen does not store the boot local APIC state which leads to problems when shutting down for a kexec jump. This patch records the boot state so we can return to the boot state when kexecing. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Signed-off-by: Keir Fraser <keir@xen.org> Acked-by: Jan Beulich <jbeulich@novell.com>
* x86/apic: fix potential Protection Fault during shutdownAndrew Cooper2011-06-141-1/+2
| | | | | | | | | | | | | | | | | | | This is a rare case, but if the BIOS is set to uniprocessor, and Xen is booted with 'lapic x2apic', Xen will switch into x2apic mode, which will cause a protection fault when disabling the local APIC. This leads to a general protection fault as this code is also in the fault handler. When x2apic mode is enabled, the only tranlsation which does not result in a protection fault is to clear both the EN and EXTD bits, which is safe to do in all cases, even if you are in xapic mode rather than x2apic mode. The linux code from which this is derrived is protected by an if ( ! x2apic_mode ...) clause which is how they get away with it. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Jan Beulich <jbeulich@novell.com>
* x86, vtd: [CVE-2011-1898] Protect against malicious MSIs from untrusted devices.Keir Fraser2011-05-121-5/+8
| | | | | | | | | | | | | | | | | | | | | In the absence of VT-d interrupt remapping support, a device can send arbitrary APIC messages to host CPUs. One class of attack that results is to confuse the hypervisor by delivering asynchronous interrupts to vectors that are expected to handle only synchronous traps/exceptions. We block this class of attack by: (1) setting APIC.TPR=0x10, to block all interrupts below vector 0x20. This blocks delivery to all architectural exception vectors. (2) checking APIC.ISR[vec] for vectors 0x80 (fast syscall) and 0x82 (hypercall). In these cases we BUG if we detect we are handling a hardware interrupt -- turning a potentially more severe infiltration into a straightforward system crash (i.e, DoS). Thanks to Invisible Things Lab <http://www.invisiblethingslab.com> for discovery and detailed investigation of this attack. Signed-off-by: Keir Fraser <keir@xen.org>
* xen/x86: explicitly mark start-of-file asm()s as .textTim Deegan2011-04-071-0/+1
| | | | | | | | LLVM and gold between them get confused when asm align commands are emitted before a section marker. Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* [VTD] check BIOS settings before enabling interrupt remapping or x2apicAllen Kay2011-04-021-3/+3
| | | | | | | | | Check flags field in ACPI DMAR structure before enabling interrupt remapping or x2apic. This allows platform vendors to disable interrupt remapping or x2apic features if on board BIOS does not support them. Signed-off-by: Allen Kay <allen.m.kay@intel.com>
* move various bits into .init.* sectionsJan Beulich2011-03-091-35/+0
| | | | | | | | | | This also includes the removal of some entirely unused functions. The patch builds upon the makefile adjustments done in the earlier sent patch titled "move more kernel decompression bits to .init.* sections". Signed-off-by: Jan Beulich <jbeulich@novell.com>
* x86: IO-APIC cleanupJan Beulich2011-03-091-1/+0
| | | | | | | | Remove unused and pointless bits from IO-APIC handling code. Move whatever possible into .init.*, and some data items into .data.read_mostly. Adjust some types. Signed-off-by: Jan Beulich <jbeulich@novell.com>
* x86: APIC cleanupJan Beulich2011-03-091-14/+5
| | | | | | | Remove unused and pointless bits from APIC handling code. Move some data items into .data.read_mostly. Adjust some types. Signed-off-by: Jan Beulich <jbeulich@novell.com>
* ix86: re-do permanent disabling of x2apicKeir Fraser2011-02-101-16/+0
| | | | | | | | Move logic into check_x2apic_preenabled() (to make sure generic_apic_probe() doesn't see genapic already set). Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Keir Fraser <keir@xen.org>
* x86:x2apic: Disable x2apic on x86-32 permanentlyKeir Fraser2011-01-211-0/+16
| | | | | | | | | x2apic initialization on x86_32 uses vcpu pointer before it is initialized. As x2apic is unlikely to be used on x86_32, this patch disables x2apic permanently on x86_32. It also asserts the sanity of vcpu pointer before dereference to prevent further misuse. Signed-off-by: Fengzhe Zhang <fengzhe.zhang@intel.com>
* x86: restore x2apic pre-enabled check logicKeir Fraser2011-01-111-9/+0
| | | | | | | | | | | | | c/s 22475 removed the early checking without replacement, neglecting the fact that x2apic_enabled must be set early for APIC register accesses done during second stage ACPI table parsing (rooted at acpi_boot_init()) to work correctly. Without this, particularly determination of the boot CPU won't work, resulting in an attempt to bring up that CPU again as a secondary one (which fails). Restore the functionality, now calling it from generic_apic_probe(). Signed-off-by: Jan Beulich <jbeulich@novell.com>
* Use bool_t for various boolean variablesKeir Fraser2010-12-241-6/+6
| | | | | | | | | | | ... decreasing cache footprint. As a prerequisite this requires making cmdline_parse() a little more flexible. Also remove a few variables altogether, and adjust sections annotations for several others. Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Keir Fraser <keir@xen.org>
* x86: adjust other interrupt related section placementKeir Fraser2010-12-151-5/+4
| | | | | | | ... and remove some variables the value of which is never used altogether. Signed-off-by: Jan Beulich <jbeulich@novell.com>
* x86: adjust x2apic section placementKeir Fraser2010-12-151-8/+7
| | | | Signed-off-by: Jan Beulich <jbeulich@novell.com>
* x86: x2apic pre-enabled but intr-remapping is not enabledKeir Fraser2010-12-151-9/+4
| | | | | | | | | | | Make it aligned with Linux kernel. Signed-off-by: Yinghai Lu <yinghai@kernel.org> Removed unnecessary bits from the original patch, and removed intremap_enabled() with its only caller gone. Signed-off-by: Jan Beulich <jbeulich@novell.com>
* x86: Define APIC_TIMER_MODE_xxx in apicdef.hKeir Fraser2010-12-151-6/+1
| | | | Signed-off-by: Wei Gang <gang.wei@intel.com>
* x86: x2apic: Large cleanupKeir Fraser2010-12-091-65/+35
| | | | Signed-off-by: Keir Fraser <keir@xen.org>
* x2apic: Remove a panic condition in enabling x2APICKeir Fraser2010-11-151-16/+5
| | | | | | | | | | | | | Currently Xen triggers a panic if user disables VT-d by command line while not disable x2APIC. This requires users to specify both "iommu=0" and "x2apic=0" to disable VT-d if the platform supports x2APIC. It's not user friendly. This patch removes the panic condition. That's to say, don't require user to specify "x2apic=0" when specify "iommu=0". As long as VT-d is not enabled (disabled in BIOS or in command line), x2APIC won't be enabled naturally (x2APIC depends on VT-d Interrupt remapping). Signed-off-by: Weidong Han <weidong.han@intel.com>
* X86: Prefer TSC-deadline timer in XenKeir Fraser2010-10-291-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new TSC Deadline Timer offers system software a low overhead per-logical-thread deadline timer in TSC units. The timer is implemented via a new architectural 64-bit register, IA32_TSC_DEADLINE_MSR. Reads and writes of this MSR occur in program order, but are non-serializing. The support for this feature is indicated by CPUID.01H:ECX.TSC_Deadline[bit 24] =3D 1 as documented in the Intel Architecture Software Developer's Manual. The LOCAL APIC on new processors has a mode where its underlying hardware timer can now be accessed via the non-serializing IA32_TSC_DEADLINE_MSR in TSC tick units. If this mode is present, prefer it over the traditional LAPIC timer mode. KERN_DEBUG dmesg will print "TSC deadline timer enabled" when TDT is used. Bootparam "tdt=off" is available to revert to LAPIC timer mode. This patch is based on original work by Len Brown for Linux kernel. cc: Len Brown <len.brown@intel.com> Signed-off-by: Wei Gang <gang.wei@intel.com> Signed-off-by: Keir Fraser <keir@xen.org>
* x2APIC: Improve x2APIC suspend/resumeKeir Fraser2010-08-131-29/+19
| | | | | | | | x2apic depends on interrupt remapping, so it should disable interrupt remapping behind x2apic disabling. And also this patch wraps __enable_x2apic to get rid of duplicated code. Signed-off-by: Weidong Han <weidong.han@intel.com>
* x2APIC: improve enabling logicKeir Fraser2010-07-051-19/+171
| | | | | | | | | | | | | | This patch masks PIC and IOAPIC RTE's before x2APIC enabling, unmask and restore them after x2APIC enabling. It also really enables interrupt remapping before x2APIC enabling instead of just checking interrupt remapping setting. This patch also handles all x2APIC configuration including BIOS settings and command line settings. Especially, it handles that BIOS hands over in x2APIC mode (when there is apic id > 255). It checks if x2APIC is already enabled by BIOS. If already enabled, it will disable interrupt remapping and queued invalidation first, then enable them again. Signed-off-by: Weidong Han <weidong.han@intel.com>
* x86: use rdmsrl/wrmsrlKeir Fraser2010-06-241-28/+28
| | | | Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
* x86: Small APIC timer initialisation cleanupKeir Fraser2010-06-071-10/+6
| | | | Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* AMD: Workaround for erratum 411Keir Fraser2010-06-071-1/+7
| | | | | | Clear APIC TMICT when we mask APIC LVTT. Signed-off-by: Wei Wang <wei.wang2@amd.com>
* Add MSR support for various feature AMD processor families.Keir Fraser2010-05-151-1/+1
| | | | Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>
* Reduce 'd' debug key's global impactKeir Fraser2010-05-061-7/+25
| | | | | | | | | | | | | | | | | | | | On large systems, dumping state may cause time management to get stalled for so long a period that it wouldn't recover. Therefore alter the state dumping logic to alternatively block each CPU as it prints rather than one CPU for a very long time (using the alternative key handling toggle introduced with an earlier patch). Further, instead of using on_selected_cpus(), which is unsafe when the dumping happens from a hardware interrupt, introduce and use a dedicated IPI sending function (which each architecture can implement to its liking) Finally, don't print useless data (e.g. the hypervisor context of the interrupt that is used for triggering the printing, but isn't part of the context that's actually interesting). Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86: enable directed EOIKeir Fraser2009-11-231-0/+25
| | | | | | | | | | | | This patch enables directed EOI on latest processor. With this, the broadcast of EOI would be suppressed upon LAPIC EOI, so VMM is required to perform a directed EOI to the IOxAPIC generating the interrupt by writting to its EOI register.(Pls. refer SDM 3A 10.5.5) This is useful for ioapic_ack_old to avoid the spurious interrupt storm, which is the reason why ioapic_ack_new is used. Signed-Off-By: Zhai Edwin <edwin.zhai@intel.com>
* x86: Clean up APIC local timer handling.Keir Fraser2009-11-031-49/+9
| | | | | | | | | | | | | | | 1. Writing TMICT=0 disables the timer. Use this fact to simplify and improve reprogram_timer(). In particular, we always write TMICT, and write zero when we do not need a timer interrupt. 2. In HPET broadcast timer handler, set TMICT=0 when we mask the APIC local timer. May as well do this early, before entering deep sleep. 3. In HVM-guest APIC emulation, disable the emulated local timer when the guest sets TMICT=0. Previously we would issue an immediate one-shot interrupt. Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* Scattered code arrangement cleanups.Keir Fraser2009-10-071-25/+49
| | | | | | | | - remove redundant declarations - add/move prototypes to headers - move things where they belong to Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
* Cleanup: Make local functions static and remove unused functions.Keir Fraser2009-09-301-8/+3
| | | | Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
* x86: Some cleanups for apic_write, apic_read, apic_wrmsr, apic_rdmsrKeir Fraser2009-09-071-5/+4
| | | | Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
* Add the support of x2apic logical cluster mode.Keir Fraser2009-09-071-10/+25
| | | | | | | | Add a xen boolean parameter 'x2apic'. Add a xen boolean parameter 'x2apic_phys'(by default, we use logical cluster mode). Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
* vt-d: enhance the support of Interrupt Remapping EIM and x2APICKeir Fraser2009-09-071-1/+12
| | | | | | | | | | | | | | 1) Clear Interrupt Remapping(IR) unit's CFI (Compatibility Format Interrupt) to enhance security; 2) Move the iommu_setup() ahead and put it before we begin to use IOAPIC so we can make sure after we enable Interrupt Remapping, the later IOAPIC (and MSI) initialization would setup IOAPIC RTEs (and MSI) with remappable format; 3) Enable x2APIC only when all VT-d engines support IR with EIM (Extended Interrupt Mode). EIM enables external devices to deliver interrupts to logical processor with >8-bit APIC ID. Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
* x86: Implement per-cpu vector for xen hypervisorKeir Fraser2009-08-191-1/+9
| | | | | | | | | | | | | | | Since Xen and Linux has big differece in code base, it is very hard to port Linux's patch and apply it to Xen directly, so this patch only adopts core logic of Linux, and make it work for Xen. Key changes: 1. vector allocation algorithm 2. all IRQ chips' set_affinity logic 3. IRQ migration when cpu hot remove. 4. Break assumptions which depend on global vector policy. Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-03 08:19:18 +0000