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-rw-r--r--tools/firmware/hvmloader/cacheattr.c25
1 files changed, 17 insertions, 8 deletions
diff --git a/tools/firmware/hvmloader/cacheattr.c b/tools/firmware/hvmloader/cacheattr.c
index 646f07f018..592b45523e 100644
--- a/tools/firmware/hvmloader/cacheattr.c
+++ b/tools/firmware/hvmloader/cacheattr.c
@@ -40,24 +40,33 @@
#define MSR_PAT 0x0277
#define MSR_MTRRdefType 0x02ff
+unsigned int cpu_phys_addr(void)
+{
+ uint32_t eax, ebx, ecx, edx;
+ unsigned int phys_bits = 36;
+ /* Find the physical address size for this CPU. */
+ cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
+ if ( eax >= 0x80000008 )
+ {
+ cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
+ phys_bits = (uint8_t)eax;
+ }
+
+ return phys_bits;
+}
+
void cacheattr_init(void)
{
uint32_t eax, ebx, ecx, edx;
uint64_t mtrr_cap, mtrr_def, content, addr_mask;
- unsigned int i, nr_var_ranges, phys_bits = 36;
+ unsigned int i, nr_var_ranges, phys_bits;
/* Does the CPU support architectural MTRRs? */
cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
if ( !(edx & (1u << 12)) )
return;
- /* Find the physical address size for this CPU. */
- cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
- if ( eax >= 0x80000008 )
- {
- cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
- phys_bits = (uint8_t)eax;
- }
+ phys_bits = cpu_phys_addr();
printf("%u-bit phys ... ", phys_bits);