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-rw-r--r--xen/arch/arm/arm32/Makefile1
-rw-r--r--xen/arch/arm/arm32/vfp.c95
-rw-r--r--xen/arch/arm/arm64/Makefile1
-rw-r--r--xen/arch/arm/arm64/vfp.c13
-rw-r--r--xen/arch/arm/domain.c7
-rw-r--r--xen/include/asm-arm/arm32/vfp.h41
-rw-r--r--xen/include/asm-arm/arm64/vfp.h16
-rw-r--r--xen/include/asm-arm/cpregs.h9
-rw-r--r--xen/include/asm-arm/domain.h4
-rw-r--r--xen/include/asm-arm/vfp.h25
10 files changed, 210 insertions, 2 deletions
diff --git a/xen/arch/arm/arm32/Makefile b/xen/arch/arm/arm32/Makefile
index aaf277a00a..b903803a58 100644
--- a/xen/arch/arm/arm32/Makefile
+++ b/xen/arch/arm/arm32/Makefile
@@ -6,5 +6,6 @@ obj-y += proc-ca15.o
obj-y += traps.o
obj-y += domain.o
+obj-y += vfp.o
obj-$(EARLY_PRINTK) += debug.o
diff --git a/xen/arch/arm/arm32/vfp.c b/xen/arch/arm/arm32/vfp.c
new file mode 100644
index 0000000000..6780131c8c
--- /dev/null
+++ b/xen/arch/arm/arm32/vfp.c
@@ -0,0 +1,95 @@
+#include <xen/sched.h>
+#include <xen/init.h>
+#include <asm/processor.h>
+#include <asm/vfp.h>
+
+void vfp_save_state(struct vcpu *v)
+{
+ v->arch.vfp.fpexc = READ_CP32(FPEXC);
+
+ WRITE_CP32(v->arch.vfp.fpexc | FPEXC_EN, FPEXC);
+
+ v->arch.vfp.fpscr = READ_CP32(FPSCR);
+
+ if ( v->arch.vfp.fpexc & FPEXC_EX ) /* Check for sub-architecture */
+ {
+ v->arch.vfp.fpinst = READ_CP32(FPINST);
+
+ if ( v->arch.vfp.fpexc & FPEXC_FP2V )
+ v->arch.vfp.fpinst2 = READ_CP32(FPINST2);
+ /* Disable FPEXC_EX */
+ WRITE_CP32((v->arch.vfp.fpexc | FPEXC_EN) & ~FPEXC_EX, FPEXC);
+ }
+
+ /* Save {d0-d15} */
+ asm volatile("stc p11, cr0, %0, #32*4"
+ : "=Q" (v->arch.vfp.fpregs1));
+
+ /* 32 x 64 bits registers? */
+ if ( (READ_CP32(MVFR0) & MVFR0_A_SIMD_MASK) == 2 )
+ {
+ /* Save {d16-d31} */
+ asm volatile("stcl p11, cr0, %0, #32*4"
+ : "=Q" (v->arch.vfp.fpregs2));
+ }
+
+ WRITE_CP32(v->arch.vfp.fpexc & ~(FPEXC_EN), FPEXC);
+}
+
+void vfp_restore_state(struct vcpu *v)
+{
+ WRITE_CP32(READ_CP32(FPEXC) | FPEXC_EN, FPEXC);
+
+ /* Restore {d0-d15} */
+ asm volatile("ldc p11, cr0, %0, #32*4"
+ : : "Q" (v->arch.vfp.fpregs1));
+
+ /* 32 x 64 bits registers? */
+ if ( (READ_CP32(MVFR0) & MVFR0_A_SIMD_MASK) == 2 ) /* 32 x 64 bits registers */
+ /* Restore {d16-d31} */
+ asm volatile("ldcl p11, cr0, %0, #32*4"
+ : : "Q" (v->arch.vfp.fpregs2));
+
+ if ( v->arch.vfp.fpexc & FPEXC_EX )
+ {
+ WRITE_CP32(v->arch.vfp.fpinst, FPINST);
+ if ( v->arch.vfp.fpexc & FPEXC_FP2V )
+ WRITE_CP32(v->arch.vfp.fpinst2, FPINST2);
+ }
+
+ WRITE_CP32(v->arch.vfp.fpscr, FPSCR);
+
+ WRITE_CP32(v->arch.vfp.fpexc, FPEXC);
+}
+
+static __init int vfp_init(void)
+{
+ unsigned int vfpsid;
+ unsigned int vfparch;
+
+ vfpsid = READ_CP32(FPSID);
+
+ printk("VFP implementer 0x%02x architecture %d part 0x%02x variant 0x%x "
+ "rev 0x%x\n",
+ (vfpsid & FPSID_IMPLEMENTER_MASK) >> FPSID_IMPLEMENTER_BIT,
+ (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT,
+ (vfpsid & FPSID_PART_MASK) >> FPSID_PART_BIT,
+ (vfpsid & FPSID_VARIANT_MASK) >> FPSID_VARIANT_BIT,
+ (vfpsid & FPSID_REV_MASK) >> FPSID_REV_BIT);
+
+ vfparch = (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT;
+ if ( vfparch < 2 )
+ panic("Xen only support VFP 3\n");
+
+ return 0;
+}
+presmp_initcall(vfp_init);
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/arch/arm/arm64/Makefile b/xen/arch/arm/arm64/Makefile
index 9484548202..e06a0a9977 100644
--- a/xen/arch/arm/arm64/Makefile
+++ b/xen/arch/arm/arm64/Makefile
@@ -5,5 +5,6 @@ obj-y += mode_switch.o
obj-y += traps.o
obj-y += domain.o
+obj-y += vfp.o
obj-$(EARLY_PRINTK) += debug.o
diff --git a/xen/arch/arm/arm64/vfp.c b/xen/arch/arm/arm64/vfp.c
new file mode 100644
index 0000000000..74e6a50579
--- /dev/null
+++ b/xen/arch/arm/arm64/vfp.c
@@ -0,0 +1,13 @@
+#include <xen/sched.h>
+#include <asm/processor.h>
+#include <asm/vfp.h>
+
+void vfp_save_state(struct vcpu *v)
+{
+ /* TODO: implement it */
+}
+
+void vfp_restore_state(struct vcpu *v)
+{
+ /* TODO: implement it */
+}
diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index 4c434a1b63..f465ab7586 100644
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -27,6 +27,7 @@
#include <asm/p2m.h>
#include <asm/irq.h>
#include <asm/cpufeature.h>
+#include <asm/vfp.h>
#include <asm/gic.h>
#include "vtimer.h"
@@ -117,7 +118,8 @@ static void ctxt_switch_from(struct vcpu *p)
/* XXX MPU */
- /* XXX VFP */
+ /* VFP */
+ vfp_save_state(p);
/* VGIC */
gic_save_state(p);
@@ -143,7 +145,8 @@ static void ctxt_switch_to(struct vcpu *n)
/* VGIC */
gic_restore_state(n);
- /* XXX VFP */
+ /* VFP */
+ vfp_restore_state(n);
/* XXX MPU */
diff --git a/xen/include/asm-arm/arm32/vfp.h b/xen/include/asm-arm/arm32/vfp.h
new file mode 100644
index 0000000000..bade3bc66e
--- /dev/null
+++ b/xen/include/asm-arm/arm32/vfp.h
@@ -0,0 +1,41 @@
+#ifndef _ARM_ARM32_VFP_H
+#define _ARM_ARM32_VFP_H
+
+#define FPEXC_EX (1u << 31)
+#define FPEXC_EN (1u << 30)
+#define FPEXC_FP2V (1u << 28)
+
+#define MVFR0_A_SIMD_MASK (0xf << 0)
+
+
+#define FPSID_IMPLEMENTER_BIT (24)
+#define FPSID_IMPLEMENTER_MASK (0xff << FPSID_IMPLEMENTER_BIT)
+#define FPSID_ARCH_BIT (16)
+#define FPSID_ARCH_MASK (0xf << FPSID_ARCH_BIT)
+#define FPSID_PART_BIT (8)
+#define FPSID_PART_MASK (0xff << FPSID_PART_BIT)
+#define FPSID_VARIANT_BIT (4)
+#define FPSID_VARIANT_MASK (0xf << FPSID_VARIANT_BIT)
+#define FPSID_REV_BIT (0)
+#define FPSID_REV_MASK (0xf << FPSID_REV_BIT)
+
+struct vfp_state
+{
+ uint64_t fpregs1[16]; /* {d0-d15} */
+ uint64_t fpregs2[16]; /* {d16-d31} */
+ uint32_t fpexc;
+ uint32_t fpscr;
+ /* VFP implementation specific state */
+ uint32_t fpinst;
+ uint32_t fpinst2;
+};
+
+#endif /* _ARM_ARM32_VFP_H */
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/asm-arm/arm64/vfp.h b/xen/include/asm-arm/arm64/vfp.h
new file mode 100644
index 0000000000..3733d2cfb7
--- /dev/null
+++ b/xen/include/asm-arm/arm64/vfp.h
@@ -0,0 +1,16 @@
+#ifndef _ARM_ARM64_VFP_H
+#define _ARM_ARM64_VFP_H
+
+struct vfp_state
+{
+};
+
+#endif /* _ARM_ARM64_VFP_H */
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/asm-arm/cpregs.h b/xen/include/asm-arm/cpregs.h
index f08d59a40c..122dd1a808 100644
--- a/xen/include/asm-arm/cpregs.h
+++ b/xen/include/asm-arm/cpregs.h
@@ -60,6 +60,15 @@
* arguments, which are cp,opc1,crn,crm,opc2.
*/
+/* Coprocessor 10 */
+
+#define FPSID p10,7,c0,c0,0 /* Floating-Point System ID Register */
+#define FPSCR p10,7,c1,c0,0 /* Floating-Point Status and Control Register */
+#define MVFR0 p10,7,c7,c0,0 /* Media and VFP Feature Register 0 */
+#define FPEXC p10,7,c8,c0,0 /* Floating-Point Exception Control Register */
+#define FPINST p10,7,c9,c0,0 /* Floating-Point Instruction Register */
+#define FPINST2 p10,7,c10,c0,0 /* Floating-point Instruction Register 2 */
+
/* Coprocessor 14 */
/* CP14 CR0: */
diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h
index cb251cc250..339b6e69ad 100644
--- a/xen/include/asm-arm/domain.h
+++ b/xen/include/asm-arm/domain.h
@@ -6,6 +6,7 @@
#include <xen/sched.h>
#include <asm/page.h>
#include <asm/p2m.h>
+#include <asm/vfp.h>
#include <public/hvm/params.h>
/* Represents state corresponding to a block of 32 interrupts */
@@ -188,6 +189,9 @@ struct arch_vcpu
uint32_t joscr, jmcr;
#endif
+ /* Float-pointer */
+ struct vfp_state vfp;
+
/* CP 15 */
uint32_t csselr;
diff --git a/xen/include/asm-arm/vfp.h b/xen/include/asm-arm/vfp.h
new file mode 100644
index 0000000000..5f10fe5962
--- /dev/null
+++ b/xen/include/asm-arm/vfp.h
@@ -0,0 +1,25 @@
+#ifndef _ASM_VFP_H
+#define _ASM_VFP_H
+
+#include <xen/sched.h>
+
+#if defined(CONFIG_ARM_32)
+# include <asm/arm32/vfp.h>
+#elif defined(CONFIG_ARM_64)
+# include <asm/arm64/vfp.h>
+#else
+# error "Unknown ARM variant"
+#endif
+
+void vfp_save_state(struct vcpu *v);
+void vfp_restore_state(struct vcpu *v);
+
+#endif /* _ASM_VFP_H */
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-11 08:00:44 +0000