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-rw-r--r--xen/arch/arm/platforms/exynos5.c7
-rw-r--r--xen/arch/arm/platforms/midway.c5
-rw-r--r--xen/arch/arm/platforms/omap5.c13
-rw-r--r--xen/arch/arm/platforms/vexpress.c5
-rw-r--r--xen/drivers/char/exynos4210-uart.c5
-rw-r--r--xen/drivers/char/omap-uart.c5
-rw-r--r--xen/drivers/char/pl011.c5
-rw-r--r--xen/include/asm-arm/arm32/io.h74
-rw-r--r--xen/include/asm-arm/arm64/io.h92
-rw-r--r--xen/include/asm-arm/io.h8
-rw-r--r--xen/include/asm-arm/mm.h8
11 files changed, 179 insertions, 48 deletions
diff --git a/xen/arch/arm/platforms/exynos5.c b/xen/arch/arm/platforms/exynos5.c
index d9eedc86ce..36d2325463 100644
--- a/xen/arch/arm/platforms/exynos5.c
+++ b/xen/arch/arm/platforms/exynos5.c
@@ -25,6 +25,7 @@
#include <xen/vmap.h>
#include <asm/platforms/exynos5.h>
#include <asm/platform.h>
+#include <asm/io.h>
static int exynos5_init_time(void)
{
@@ -41,8 +42,8 @@ static int exynos5_init_time(void)
}
/* Enable timer on Exynos 5250 should probably be done by u-boot */
- reg = ioreadl(mct + EXYNOS5_MCT_G_TCON);
- iowritel(mct + EXYNOS5_MCT_G_TCON, reg | EXYNOS5_MCT_G_TCON_START);
+ reg = readl(mct + EXYNOS5_MCT_G_TCON);
+ writel(reg | EXYNOS5_MCT_G_TCON_START, mct + EXYNOS5_MCT_G_TCON);
iounmap(mct);
@@ -77,7 +78,7 @@ static void exynos5_reset(void)
return;
}
- iowritel(pmu + EXYNOS5_SWRESET, 1);
+ writel(1, pmu + EXYNOS5_SWRESET);
iounmap(pmu);
}
diff --git a/xen/arch/arm/platforms/midway.c b/xen/arch/arm/platforms/midway.c
index 7a3dfe1899..a48fc84141 100644
--- a/xen/arch/arm/platforms/midway.c
+++ b/xen/arch/arm/platforms/midway.c
@@ -21,6 +21,7 @@
#include <xen/vmap.h>
#include <asm/platforms/midway.h>
#include <asm/platform.h>
+#include <asm/io.h>
static void midway_reset(void)
{
@@ -36,8 +37,8 @@ static void midway_reset(void)
return;
}
- iowritel(pmu + (MW_SREG_PWR_REQ & ~PAGE_MASK), MW_PWR_HARD_RESET);
- iowritel(pmu + (MW_SREG_A15_PWR_CTRL & ~PAGE_MASK), 1);
+ writel(MW_PWR_HARD_RESET, pmu + (MW_SREG_PWR_REQ & ~PAGE_MASK));
+ writel(1, pmu + (MW_SREG_A15_PWR_CTRL & ~PAGE_MASK));
iounmap(pmu);
}
diff --git a/xen/arch/arm/platforms/omap5.c b/xen/arch/arm/platforms/omap5.c
index c10cf00006..a40d0169f0 100644
--- a/xen/arch/arm/platforms/omap5.c
+++ b/xen/arch/arm/platforms/omap5.c
@@ -23,6 +23,7 @@
#include <asm/platforms/omap5.h>
#include <xen/mm.h>
#include <xen/vmap.h>
+#include <asm/io.h>
static uint16_t num_den[8][2] = {
{ 0, 0 }, /* not used */
@@ -59,7 +60,7 @@ static int omap5_init_time(void)
return -ENOMEM;
}
- sys_clksel = ioreadl(ckgen_prm_base + OMAP5_CM_CLKSEL_SYS) &
+ sys_clksel = readl(ckgen_prm_base + OMAP5_CM_CLKSEL_SYS) &
~SYS_CLKSEL_MASK;
iounmap(ckgen_prm_base);
@@ -72,7 +73,7 @@ static int omap5_init_time(void)
return -ENOMEM;
}
- frac1 = ioreadl(rt_ct_base + INCREMENTER_NUMERATOR_OFFSET);
+ frac1 = readl(rt_ct_base + INCREMENTER_NUMERATOR_OFFSET);
num = frac1 & ~NUMERATOR_DENUMERATOR_MASK;
if ( num_den[sys_clksel][0] != num )
{
@@ -80,7 +81,7 @@ static int omap5_init_time(void)
frac1 |= num_den[sys_clksel][0];
}
- frac2 = ioreadl(rt_ct_base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
+ frac2 = readl(rt_ct_base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
den = frac2 & ~NUMERATOR_DENUMERATOR_MASK;
if ( num_den[sys_clksel][1] != num )
{
@@ -88,9 +89,9 @@ static int omap5_init_time(void)
frac2 |= num_den[sys_clksel][1];
}
- iowritel(rt_ct_base + INCREMENTER_NUMERATOR_OFFSET, frac1);
- iowritel(rt_ct_base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET,
- frac2 | PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD);
+ writel(frac1, rt_ct_base + INCREMENTER_NUMERATOR_OFFSET);
+ writel(frac2 | PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD,
+ rt_ct_base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
iounmap(rt_ct_base);
diff --git a/xen/arch/arm/platforms/vexpress.c b/xen/arch/arm/platforms/vexpress.c
index 298c141844..22c0c13e98 100644
--- a/xen/arch/arm/platforms/vexpress.c
+++ b/xen/arch/arm/platforms/vexpress.c
@@ -21,6 +21,7 @@
#include <asm/platform.h>
#include <xen/mm.h>
#include <xen/vmap.h>
+#include <asm/io.h>
#define DCC_SHIFT 26
#define FUNCTION_SHIFT 20
@@ -110,10 +111,10 @@ static void vexpress_reset(void)
}
/* switch to slow mode */
- iowritel(sp810, 0x3);
+ writel(0x3, sp810);
dsb(); isb();
/* writing any value to SCSYSSTAT reg will reset the system */
- iowritel(sp810 + 4, 0x1);
+ writel(0x1, sp810 + 4);
dsb(); isb();
iounmap(sp810);
diff --git a/xen/drivers/char/exynos4210-uart.c b/xen/drivers/char/exynos4210-uart.c
index b297ed4a83..0a2ac17037 100644
--- a/xen/drivers/char/exynos4210-uart.c
+++ b/xen/drivers/char/exynos4210-uart.c
@@ -27,6 +27,7 @@
#include <asm/early_printk.h>
#include <asm/device.h>
#include <asm/exynos4210-uart.h>
+#include <asm/io.h>
static struct exynos4210_uart {
unsigned int baud, clock_hz, data_bits, parity, stop_bits;
@@ -43,8 +44,8 @@ static struct exynos4210_uart {
#define FORCED_CHECKED_AS_ONE (0x6)
#define FORCED_CHECKED_AS_ZERO (0x7)
-#define exynos4210_read(uart, off) ioreadl((uart)->regs + off)
-#define exynos4210_write(uart, off, val) iowritel((uart->regs) + off, val)
+#define exynos4210_read(uart, off) readl((uart)->regs + off)
+#define exynos4210_write(uart, off, val) writel(val, (uart->regs) + off)
static void exynos4210_uart_interrupt(int irq, void *data, struct cpu_user_regs *regs)
{
diff --git a/xen/drivers/char/omap-uart.c b/xen/drivers/char/omap-uart.c
index ffa71db921..321e636e86 100644
--- a/xen/drivers/char/omap-uart.c
+++ b/xen/drivers/char/omap-uart.c
@@ -22,11 +22,12 @@
#include <xen/mm.h>
#include <xen/vmap.h>
#include <xen/8250-uart.h>
+#include <asm/io.h>
#define REG_SHIFT 2
-#define omap_read(uart, off) ioreadl((uart)->regs + (off<<REG_SHIFT))
-#define omap_write(uart, off, val) iowritel((uart)->regs + (off<<REG_SHIFT), (val))
+#define omap_read(uart, off) readl((uart)->regs + (off<<REG_SHIFT))
+#define omap_write(uart, off, val) writel((val), (uart)->regs + (off<<REG_SHIFT))
static struct omap_uart {
u32 baud, clock_hz, data_bits, parity, stop_bits, fifo_size;
diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c
index 3386e2bc28..613b9ebfd7 100644
--- a/xen/drivers/char/pl011.c
+++ b/xen/drivers/char/pl011.c
@@ -29,6 +29,7 @@
#include <xen/mm.h>
#include <xen/vmap.h>
#include <asm/pl011-uart.h>
+#include <asm/io.h>
static struct pl011 {
unsigned int baud, clock_hz, data_bits, parity, stop_bits;
@@ -50,8 +51,8 @@ static struct pl011 {
#define PARITY_MARK (PEN|SPS)
#define PARITY_SPACE (PEN|EPS|SPS)
-#define pl011_read(uart, off) ioreadl((uart)->regs + (off))
-#define pl011_write(uart, off,val) iowritel((uart)->regs + (off), (val))
+#define pl011_read(uart, off) readl((uart)->regs + (off))
+#define pl011_write(uart, off,val) writel((val), (uart)->regs + (off))
static void pl011_interrupt(int irq, void *data, struct cpu_user_regs *regs)
{
diff --git a/xen/include/asm-arm/arm32/io.h b/xen/include/asm-arm/arm32/io.h
index ec7e0ff9a2..73a879e9fb 100644
--- a/xen/include/asm-arm/arm32/io.h
+++ b/xen/include/asm-arm/arm32/io.h
@@ -22,25 +22,75 @@
#define _ARM_ARM32_IO_H
#include <asm/system.h>
+#include <asm/byteorder.h>
-static inline uint32_t ioreadl(const volatile void __iomem *addr)
+static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
{
- uint32_t val;
+ asm volatile("strb %1, %0"
+ : "+Qo" (*(volatile u8 __force *)addr)
+ : "r" (val));
+}
+
+static inline void __raw_writew(u16 val, volatile void __iomem *addr)
+{
+ asm volatile("strh %1, %0"
+ : "+Q" (*(volatile u16 __force *)addr)
+ : "r" (val));
+}
- asm volatile("ldr %1, %0"
- : "+Qo" (*(volatile uint32_t __force *)addr),
- "=r" (val));
- dsb();
+static inline void __raw_writel(u32 val, volatile void __iomem *addr)
+{
+ asm volatile("str %1, %0"
+ : "+Qo" (*(volatile u32 __force *)addr)
+ : "r" (val));
+}
- return val;
+static inline u8 __raw_readb(const volatile void __iomem *addr)
+{
+ u8 val;
+ asm volatile("ldrb %1, %0"
+ : "+Qo" (*(volatile u8 __force *)addr),
+ "=r" (val));
+ return val;
}
-static inline void iowritel(const volatile void __iomem *addr, uint32_t val)
+static inline u16 __raw_readw(const volatile void __iomem *addr)
{
- dsb();
- asm volatile("str %1, %0"
- : "+Qo" (*(volatile uint32_t __force *)addr)
- : "r" (val));
+ u16 val;
+ asm volatile("ldrh %1, %0"
+ : "+Q" (*(volatile u16 __force *)addr),
+ "=r" (val));
+ return val;
}
+static inline u32 __raw_readl(const volatile void __iomem *addr)
+{
+ u32 val;
+ asm volatile("ldr %1, %0"
+ : "+Qo" (*(volatile u32 __force *)addr),
+ "=r" (val));
+ return val;
+}
+
+#define __iormb() rmb()
+#define __iowmb() wmb()
+
+#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
+#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
+ __raw_readw(c)); __r; })
+#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
+ __raw_readl(c)); __r; })
+
+#define writeb_relaxed(v,c) __raw_writeb(v,c)
+#define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
+#define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
+
+#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
+#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
+#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
+
+#define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
+#define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
+#define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
+
#endif /* _ARM_ARM32_IO_H */
diff --git a/xen/include/asm-arm/arm64/io.h b/xen/include/asm-arm/arm64/io.h
index ec041cdbc4..37abc4788f 100644
--- a/xen/include/asm-arm/arm64/io.h
+++ b/xen/include/asm-arm/arm64/io.h
@@ -1,5 +1,6 @@
/*
- * Based on linux arch/arm64/include/asm/io.h
+ * Based on linux arch/arm64/include/asm/io.h which is in turn
+ * Based on arch/arm/include/asm/io.h
*
* Copyright (C) 1996-2000 Russell King
* Copyright (C) 2012 ARM Ltd.
@@ -19,20 +20,93 @@
#ifndef _ARM_ARM64_IO_H
#define _ARM_ARM64_IO_H
-static inline uint32_t ioreadl(const volatile void __iomem *addr)
+#include <asm/byteorder.h>
+
+/*
+ * Generic IO read/write. These perform native-endian accesses.
+ */
+static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
{
- uint32_t val;
+ asm volatile("strb %w0, [%1]" : : "r" (val), "r" (addr));
+}
- asm volatile("ldr %w0, [%1]" : "=r" (val) : "r" (addr));
- dsb();
+static inline void __raw_writew(u16 val, volatile void __iomem *addr)
+{
+ asm volatile("strh %w0, [%1]" : : "r" (val), "r" (addr));
+}
- return val;
+static inline void __raw_writel(u32 val, volatile void __iomem *addr)
+{
+ asm volatile("str %w0, [%1]" : : "r" (val), "r" (addr));
}
-static inline void iowritel(const volatile void __iomem *addr, uint32_t val)
+static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
{
- dsb();
- asm volatile("str %w0, [%1]" : : "r" (val), "r" (addr));
+ asm volatile("str %0, [%1]" : : "r" (val), "r" (addr));
}
+static inline u8 __raw_readb(const volatile void __iomem *addr)
+{
+ u8 val;
+ asm volatile("ldrb %w0, [%1]" : "=r" (val) : "r" (addr));
+ return val;
+}
+
+static inline u16 __raw_readw(const volatile void __iomem *addr)
+{
+ u16 val;
+ asm volatile("ldrh %w0, [%1]" : "=r" (val) : "r" (addr));
+ return val;
+}
+
+static inline u32 __raw_readl(const volatile void __iomem *addr)
+{
+ u32 val;
+ asm volatile("ldr %w0, [%1]" : "=r" (val) : "r" (addr));
+ return val;
+}
+
+static inline u64 __raw_readq(const volatile void __iomem *addr)
+{
+ u64 val;
+ asm volatile("ldr %0, [%1]" : "=r" (val) : "r" (addr));
+ return val;
+}
+
+/* IO barriers */
+#define __iormb() rmb()
+#define __iowmb() wmb()
+
+#define mmiowb() do { } while (0)
+
+/*
+ * Relaxed I/O memory access primitives. These follow the Device memory
+ * ordering rules but do not guarantee any ordering relative to Normal memory
+ * accesses.
+ */
+#define readb_relaxed(c) ({ u8 __v = __raw_readb(c); __v; })
+#define readw_relaxed(c) ({ u16 __v = le16_to_cpu((__force __le16)__raw_readw(c)); __v; })
+#define readl_relaxed(c) ({ u32 __v = le32_to_cpu((__force __le32)__raw_readl(c)); __v; })
+#define readq_relaxed(c) ({ u64 __v = le64_to_cpu((__force __le64)__raw_readq(c)); __v; })
+
+#define writeb_relaxed(v,c) ((void)__raw_writeb((v),(c)))
+#define writew_relaxed(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
+#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
+#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
+
+/*
+ * I/O memory access primitives. Reads are ordered relative to any
+ * following Normal memory access. Writes are ordered relative to any prior
+ * Normal memory access.
+ */
+#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
+#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
+#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
+#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
+
+#define writeb(v,c) ({ __iowmb(); writeb_relaxed((v),(c)); })
+#define writew(v,c) ({ __iowmb(); writew_relaxed((v),(c)); })
+#define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); })
+#define writeq(v,c) ({ __iowmb(); writeq_relaxed((v),(c)); })
+
#endif /* _ARM_ARM64_IO_H */
diff --git a/xen/include/asm-arm/io.h b/xen/include/asm-arm/io.h
index aea5233d59..e426804424 100644
--- a/xen/include/asm-arm/io.h
+++ b/xen/include/asm-arm/io.h
@@ -1,6 +1,14 @@
#ifndef _ASM_IO_H
#define _ASM_IO_H
+#if defined(CONFIG_ARM_32)
+# include <asm/arm32/io.h>
+#elif defined(CONFIG_ARM_64)
+# include <asm/arm64/io.h>
+#else
+# error "unknown ARM variant"
+#endif
+
#endif
/*
* Local variables:
diff --git a/xen/include/asm-arm/mm.h b/xen/include/asm-arm/mm.h
index 97c2ee0302..173db1b9c7 100644
--- a/xen/include/asm-arm/mm.h
+++ b/xen/include/asm-arm/mm.h
@@ -6,14 +6,6 @@
#include <asm/page.h>
#include <public/xen.h>
-#if defined(CONFIG_ARM_32)
-# include <asm/arm32/io.h>
-#elif defined(CONFIG_ARM_64)
-# include <asm/arm64/io.h>
-#else
-# error "unknown ARM variant"
-#endif
-
/* Align Xen to a 2 MiB boundary. */
#define XEN_PADDR_ALIGN (1 << 21)
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-26 19:47:37 +0000