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authorStefano Stabellini <stefano.stabellini@eu.citrix.com>2013-01-24 12:47:49 +0000
committerStefano Stabellini <stefano.stabellini@eu.citrix.com>2013-01-24 12:47:49 +0000
commit34446a7e5ad47cc7902c384069a60fc3436f9f08 (patch)
tree35534c977389ba55b3c9460f5408b6df516f3594 /xen
parent9a7ac6e2e437829b0d126a99b21ad6e114ec415b (diff)
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xen/arm: introduce flush_xen_data_tlb_range_va
Add flush_xen_data_tlb_range_va, that flushes a range of virtual addresses. Replace all the calls to flush_xen_data_tlb_va with calls to flush_xen_data_tlb_range_va and remove flush_xen_data_tlb_va. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Acked-by: Ian Campbell <ian.campbell@citrix.com> Committed-by: Ian Campbell <ian.campbell@citrix.com>
Diffstat (limited to 'xen')
-rw-r--r--xen/arch/arm/mm.c8
-rw-r--r--xen/include/asm-arm/page.h18
2 files changed, 15 insertions, 11 deletions
diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
index eb5213e35b..f5712f7007 100644
--- a/xen/arch/arm/mm.c
+++ b/xen/arch/arm/mm.c
@@ -114,7 +114,7 @@ void set_fixmap(unsigned map, unsigned long mfn, unsigned attributes)
pte.pt.ai = attributes;
pte.pt.xn = 1;
write_pte(xen_fixmap + third_table_offset(FIXMAP_ADDR(map)), pte);
- flush_xen_data_tlb_va(FIXMAP_ADDR(map));
+ flush_xen_data_tlb_range_va(FIXMAP_ADDR(map), PAGE_SIZE);
}
/* Remove a mapping from a fixmap entry */
@@ -122,7 +122,7 @@ void clear_fixmap(unsigned map)
{
lpae_t pte = {0};
write_pte(xen_fixmap + third_table_offset(FIXMAP_ADDR(map)), pte);
- flush_xen_data_tlb_va(FIXMAP_ADDR(map));
+ flush_xen_data_tlb_range_va(FIXMAP_ADDR(map), PAGE_SIZE);
}
/* Map a page of domheap memory */
@@ -186,7 +186,7 @@ void *map_domain_page(unsigned long mfn)
* We may not have flushed this specific subpage at map time,
* since we only flush the 4k page not the superpage
*/
- flush_xen_data_tlb_va(va);
+ flush_xen_data_tlb_range_va(va, PAGE_SIZE);
return (void *)va;
}
@@ -246,7 +246,7 @@ void __init setup_pagetables(unsigned long boot_phys_offset, paddr_t xen_paddr)
dest_va = BOOT_MISC_VIRT_START;
pte = mfn_to_xen_entry(xen_paddr >> PAGE_SHIFT);
write_pte(xen_second + second_table_offset(dest_va), pte);
- flush_xen_data_tlb_va(dest_va);
+ flush_xen_data_tlb_range_va(dest_va, PAGE_SIZE);
/* Calculate virt-to-phys offset for the new location */
phys_offset = xen_paddr - (unsigned long) _start;
diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h
index 5779cf4efe..090d93f461 100644
--- a/xen/include/asm-arm/page.h
+++ b/xen/include/asm-arm/page.h
@@ -316,16 +316,20 @@ static inline void flush_xen_data_tlb(void)
}
/*
- * Flush one VA's hypervisor mappings from the data TLB. This is not
+ * Flush a range of VA's hypervisor mappings from the data TLB. This is not
* sufficient when changing code mappings or for self modifying code.
*/
-static inline void flush_xen_data_tlb_va(unsigned long va)
+static inline void flush_xen_data_tlb_range_va(unsigned long va, unsigned long size)
{
- asm volatile("dsb;" /* Ensure preceding are visible */
- STORE_CP32(0, TLBIMVAH)
- "dsb;" /* Ensure completion of the TLB flush */
- "isb;"
- : : "r" (va) : "memory");
+ unsigned long end = va + size;
+ dsb(); /* Ensure preceding are visible */
+ while ( va < end ) {
+ asm volatile(STORE_CP32(0, TLBIMVAH)
+ : : "r" (va) : "memory");
+ va += PAGE_SIZE;
+ }
+ dsb(); /* Ensure completion of the TLB flush */
+ isb();
}
/* Flush all non-hypervisor mappings from the TLB */