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| author | Tim Deegan <tim@xen.org> | 2012-03-13 15:10:53 +0000 |
|---|---|---|
| committer | Tim Deegan <tim@xen.org> | 2012-03-13 15:10:53 +0000 |
| commit | 139692dee47dbc35b9a646a9bafde2bca3cd4e6e (patch) | |
| tree | 7b2d0903d09d8b4d5341e2960ee18863b2b1651f /xen | |
| parent | 335ba242c55caf5c0259ade192f9e028dcfae9d8 (diff) | |
| download | xen-139692dee47dbc35b9a646a9bafde2bca3cd4e6e.tar.gz xen-139692dee47dbc35b9a646a9bafde2bca3cd4e6e.tar.bz2 xen-139692dee47dbc35b9a646a9bafde2bca3cd4e6e.zip | |
arm: Add a comment explaining the GICD writes in the GICC init function
Signed-off-by: Tim Deegan <tim@xen.org>
Committed-by: Ian Campbell <ian.campbell@citrix.com>
Diffstat (limited to 'xen')
| -rw-r--r-- | xen/arch/arm/gic.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index adc10bbe2f..1ff445810a 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -224,7 +224,9 @@ static void __cpuinit gic_cpu_init(void) { int i; - /* Disable all PPI and enable all SGI */ + /* The first 32 interrupts (PPI and SGI) are banked per-cpu, so + * even though they are controlled with GICD registers, they must + * be set up here with the other per-cpu state. */ GICD[GICD_ICENABLER] = 0xffff0000; /* Disable all PPI */ GICD[GICD_ISENABLER] = 0x0000ffff; /* Enable all SGI */ /* Set PPI and SGI priorities */ |