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| author | Ian Campbell <ian.campbell@citrix.com> | 2013-09-20 17:18:35 +0100 |
|---|---|---|
| committer | Ian Campbell <ian.campbell@citrix.com> | 2013-09-21 16:27:45 +0100 |
| commit | 50417cd978aa54930d065ac1f139f935d14af76d (patch) | |
| tree | 16c9096142fef419b39c2ad70a47110bb4483e38 /xen/include/xen | |
| parent | 7c1de0038895cbc75ebd0caffc5b0f3f03c5ad51 (diff) | |
| download | xen-50417cd978aa54930d065ac1f139f935d14af76d.tar.gz xen-50417cd978aa54930d065ac1f139f935d14af76d.tar.bz2 xen-50417cd978aa54930d065ac1f139f935d14af76d.zip | |
ns16550: support DesignWare 8250
This hardware has an additional feature which signals an error if you try to
write LCR while the UART is busy. We need to clear this error during setup,
otherwise LCR.DLAB doesn't get set and we cannot read/write the divisor.
This has been tested on the cubieboard2
Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Keir Fraser <keir@xen.org>
Cc: jbeulich@suse.com
Diffstat (limited to 'xen/include/xen')
| -rw-r--r-- | xen/include/xen/8250-uart.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/xen/include/xen/8250-uart.h b/xen/include/xen/8250-uart.h index 8693d15467..a682bae797 100644 --- a/xen/include/xen/8250-uart.h +++ b/xen/include/xen/8250-uart.h @@ -32,6 +32,7 @@ #define UART_MCR 0x04 /* Modem control */ #define UART_LSR 0x05 /* line status */ #define UART_MSR 0x06 /* Modem status */ +#define UART_USR 0x1f /* Status register (DW) */ #define UART_DLL 0x00 /* divisor latch (ls) (DLAB=1) */ #define UART_DLM 0x01 /* divisor latch (ms) (DLAB=1) */ @@ -48,6 +49,7 @@ #define UART_IIR_RDA 0x04 /* - rx data recv'd */ #define UART_IIR_THR 0x02 /* - tx reg. empty */ #define UART_IIR_MSI 0x00 /* - MODEM status */ +#define UART_IIR_BSY 0x07 /* - busy detect (DW) */ /* FIFO Control Register */ #define UART_FCR_ENABLE 0x01 /* enable FIFO */ |