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| author | Jan Beulich <jbeulich@suse.com> | 2013-05-02 16:46:02 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2013-05-02 16:46:02 +0200 |
| commit | d1222afda4d27916580c28533762e362d64ace22 (patch) | |
| tree | bb948d8c28906c1ad2fc11d80f64748631352052 /xen/include/xen/iommu.h | |
| parent | b8efae696c9a2d46e91fa0eda739427efc16c250 (diff) | |
| download | xen-d1222afda4d27916580c28533762e362d64ace22.tar.gz xen-d1222afda4d27916580c28533762e362d64ace22.tar.bz2 xen-d1222afda4d27916580c28533762e362d64ace22.zip | |
x86: allow Dom0 read-only access to IO-APICs
There are BIOSes that want to map the IO-APIC MMIO region from some
ACPI method(s), and there is at least one BIOS flavor that wants to
use this mapping to clear an RTE's mask bit. While we can't allow the
latter, we can permit reads and simply drop write attempts, leveraging
the already existing infrastructure introduced for dealing with AMD
IOMMUs' representation as PCI devices.
This fixes an interrupt setup problem on a system where _CRS evaluation
involved the above described BIOS/ACPI behavior, and is expected to
also deal with a boot time crash of pv-ops Linux upon encountering the
same kind of system.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Keir Fraser <keir@xen.org>
Diffstat (limited to 'xen/include/xen/iommu.h')
| -rw-r--r-- | xen/include/xen/iommu.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/xen/include/xen/iommu.h b/xen/include/xen/iommu.h index 8f049976af..6f0ff9d749 100644 --- a/xen/include/xen/iommu.h +++ b/xen/include/xen/iommu.h @@ -37,8 +37,6 @@ extern bool_t amd_iommu_perdev_intremap; /* Does this domain have a P2M table we can use as its IOMMU pagetable? */ #define iommu_use_hap_pt(d) (hap_enabled(d) && iommu_hap_pt_share) -extern struct rangeset *mmio_ro_ranges; - #define domain_hvm_iommu(d) (&d->arch.hvm_domain.hvm_iommu) #define MAX_IOMMUS 32 |