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| author | Len Brown <len.brown@intel.com> | 2013-08-30 10:59:09 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2013-08-30 10:59:09 +0200 |
| commit | 91413b51963127d435cfba38e382e81188527ef5 (patch) | |
| tree | 442fdbcd3fdd3df564a01957a6dded995ef1e1d1 /xen/include/asm-x86 | |
| parent | 3642ba0f692cfa9319fdeca82268238daba23794 (diff) | |
| download | xen-91413b51963127d435cfba38e382e81188527ef5.tar.gz xen-91413b51963127d435cfba38e382e81188527ef5.tar.bz2 xen-91413b51963127d435cfba38e382e81188527ef5.zip | |
x86/mwait_idle: export both C1 and C1E
Here we disable HW promotion of C1 to C1E and export both C1 and C1E
as distinct C-states.
This allows a cpuidle governor to choose a lower latency C-state than
C1E when necessary to satisfy performance and QOS constraints -- and
still save power versus polling.
This also corrects the erroneous latency previously reported for C1E
-- it is 10usec, not 1usec.
Signed-off-by: Len Brown <len.brown@intel.com>
Avoided the effect of changing the meaning of "max_cstate=".
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Keir Fraser <keir@xen.org>
Diffstat (limited to 'xen/include/asm-x86')
| -rw-r--r-- | xen/include/asm-x86/msr-index.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index 03cb00ecaf..e597a28a23 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -83,6 +83,8 @@ #define MSR_IA32_LASTINTFROMIP 0x000001dd #define MSR_IA32_LASTINTTOIP 0x000001de +#define MSR_IA32_POWER_CTL 0x000001fc + #define MSR_IA32_MTRR_PHYSBASE0 0x00000200 #define MSR_IA32_MTRR_PHYSMASK0 0x00000201 #define MSR_IA32_MTRR_PHYSBASE1 0x00000202 |