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| author | Boris Ostrovsky <boris.ostrovsky@oracle.com> | 2013-08-07 09:51:02 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2013-08-07 09:51:02 +0200 |
| commit | 330c2e4e9430855cd7e5dd45b247ccc27bf92c7a (patch) | |
| tree | f864d3856894e5e38e92b4447e3021125829a8b1 /xen/include/asm-x86 | |
| parent | 66450c1d1ab3c4480bbba949113b95d1ab6a943a (diff) | |
| download | xen-330c2e4e9430855cd7e5dd45b247ccc27bf92c7a.tar.gz xen-330c2e4e9430855cd7e5dd45b247ccc27bf92c7a.tar.bz2 xen-330c2e4e9430855cd7e5dd45b247ccc27bf92c7a.zip | |
Intel/VPMU: Add support for full-width PMC writes
A recent Linux commit (069e0c3c405814778c7475d95b9fff5318f39834) added
support for full-width PMC writes to performance counter registers,
making these registers default for perf. Since current Xen VPMU does
not support these new MSRs perf will fail to initialise in guests.
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
Acked-by: Keir Faser <keir@xen.org>
Diffstat (limited to 'xen/include/asm-x86')
| -rw-r--r-- | xen/include/asm-x86/msr-index.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index f500efdf4f..03cb00ecaf 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -33,7 +33,7 @@ /* Intel MSRs. Some also available on other CPUs */ #define MSR_IA32_PERFCTR0 0x000000c1 -#define MSR_IA32_PERFCTR1 0x000000c2 +#define MSR_IA32_A_PERFCTR0 0x000004c1 #define MSR_FSB_FREQ 0x000000cd #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 |