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| author | Tim Deegan <Tim.Deegan@xensource.com> | 2006-10-17 11:11:48 +0100 |
|---|---|---|
| committer | Tim Deegan <Tim.Deegan@xensource.com> | 2006-10-17 11:11:48 +0100 |
| commit | f26cc7890337eb60472e9888a547a608f2555916 (patch) | |
| tree | 8b9e726efaa0dbb8d8b71688a077e8b6d421b05d /xen/include/asm-x86/shadow.h | |
| parent | 3cc943dc88804bb61719d991267cc4b86f0fe198 (diff) | |
| download | xen-f26cc7890337eb60472e9888a547a608f2555916.tar.gz xen-f26cc7890337eb60472e9888a547a608f2555916.tar.bz2 xen-f26cc7890337eb60472e9888a547a608f2555916.zip | |
[XEN] Don't keep shadows of PAE guest l3 tables.
Holding pages readonly that have guest PAE l3 tables in them means
a performance hit and potential bug if the guest puts other
datastructures on the same page as an l3 table. Instead of shadowing
them, treat PAE guests as if they had four CR3 registers, and load all
four top-level entries when we handle a CR3 write. This also cuts about
500 lines of special-case refcounting and re-copying code.
Signed-off-by: Tim Deegan <Tim.Deegan@xensource.com>
Diffstat (limited to 'xen/include/asm-x86/shadow.h')
| -rw-r--r-- | xen/include/asm-x86/shadow.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/xen/include/asm-x86/shadow.h b/xen/include/asm-x86/shadow.h index 9301022abd..27cf6843eb 100644 --- a/xen/include/asm-x86/shadow.h +++ b/xen/include/asm-x86/shadow.h @@ -72,7 +72,6 @@ #define SHADOW_SET_CHANGED 0x1 #define SHADOW_SET_FLUSH 0x2 #define SHADOW_SET_ERROR 0x4 -#define SHADOW_SET_L3PAE_RECOPY 0x8 // How do we tell that we have a 32-bit PV guest in a 64-bit Xen? #ifdef __x86_64__ @@ -406,7 +405,6 @@ shadow_update_cr3(struct vcpu *v) * for HVM guests, arch.monitor_table and hvm's guest CR3. * * Update ref counts to shadow tables appropriately. - * For PAE, relocate L3 entries, if necessary, into low memory. */ static inline void update_cr3(struct vcpu *v) { @@ -587,7 +585,6 @@ shadow_guest_physmap_remove_page(struct domain *d, unsigned long gfn, #define SHF_FL1_PAE (1u << PGC_SH_type_to_index(PGC_SH_fl1_pae_shadow)) #define SHF_L2_PAE (1u << PGC_SH_type_to_index(PGC_SH_l2_pae_shadow)) #define SHF_L2H_PAE (1u << PGC_SH_type_to_index(PGC_SH_l2h_pae_shadow)) -#define SHF_L3_PAE (1u << PGC_SH_type_to_index(PGC_SH_l3_pae_shadow)) #define SHF_L1_64 (1u << PGC_SH_type_to_index(PGC_SH_l1_64_shadow)) #define SHF_FL1_64 (1u << PGC_SH_type_to_index(PGC_SH_fl1_64_shadow)) #define SHF_L2_64 (1u << PGC_SH_type_to_index(PGC_SH_l2_64_shadow)) |