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| author | kfraser@localhost.localdomain <kfraser@localhost.localdomain> | 2007-05-24 13:30:29 +0100 |
|---|---|---|
| committer | kfraser@localhost.localdomain <kfraser@localhost.localdomain> | 2007-05-24 13:30:29 +0100 |
| commit | fea68d9d919d6605c60f67de4643b85b1bc09c09 (patch) | |
| tree | 38de5575c1f1eadda449a37d60fa652ef2753bf3 /xen/include/asm-x86/msr.h | |
| parent | 55e8bb3f3f91d6ed5fbed991996428589bda47cb (diff) | |
| download | xen-fea68d9d919d6605c60f67de4643b85b1bc09c09.tar.gz xen-fea68d9d919d6605c60f67de4643b85b1bc09c09.tar.bz2 xen-fea68d9d919d6605c60f67de4643b85b1bc09c09.zip | |
svm: Handle MC4_MISC threshold register for guests
The threshold register has been introduced in AMD RevF CPUs along with
SVM (Actually this MCA/MCE msr register existed before, but had no
meaning). Therefore no need for additional cpuid checks.
On read access it reports the HVM guest the register has been locked
by the BIOS. This means, it is not available for OS use. Thus, write
accesses are simply ignored. This behaviour actually matches real HW,
so guests can deal with this.
Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
Diffstat (limited to 'xen/include/asm-x86/msr.h')
| -rw-r--r-- | xen/include/asm-x86/msr.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/xen/include/asm-x86/msr.h b/xen/include/asm-x86/msr.h index d1ea050b68..3ed5265e6e 100644 --- a/xen/include/asm-x86/msr.h +++ b/xen/include/asm-x86/msr.h @@ -217,6 +217,27 @@ static inline void write_efer(__u64 val) #define MSR_IA32_MC0_ADDR 0x402 #define MSR_IA32_MC0_MISC 0x403 +/* K8 Machine Check MSRs */ +#define MSR_K8_MC1_CTL 0x404 +#define MSR_K8_MC1_STATUS 0x405 +#define MSR_K8_MC1_ADDR 0x406 +#define MSR_K8_MC1_MISC 0x407 + +#define MSR_K8_MC2_CTL 0x408 +#define MSR_K8_MC2_STATUS 0x409 +#define MSR_K8_MC2_ADDR 0x40A +#define MSR_K8_MC2_MISC 0x40B + +#define MSR_K8_MC3_CTL 0x40C +#define MSR_K8_MC3_STATUS 0x40D +#define MSR_K8_MC3_ADDR 0x40E +#define MSR_K8_MC3_MISC 0x40F + +#define MSR_K8_MC4_CTL 0x410 +#define MSR_K8_MC4_STATUS 0x411 +#define MSR_K8_MC4_ADDR 0x412 +#define MSR_K8_MC4_MISC 0x413 + /* Pentium IV performance counter MSRs */ #define MSR_P4_BPU_PERFCTR0 0x300 #define MSR_P4_BPU_PERFCTR1 0x301 |