x86: fix EFER handling

Introduce a per-CPU shadow of what is currently in EFER, as context
switch code must re-write this MSR so that all guests run with
appropriate EFER.SCE and EFER.NX settings. Remove EFER from the set of
MSRs that VMX deals with in a generic fashion.

Signed-off-by: Jan Beulich <jbeulich@novell.com>

1 files changed, 22 insertions, 0 deletions

diff --git a/xen/include/asm-x86/msr.h b/xen/include/asm-x86/msr.h
index bd7f27b6c5..d1ea050b68 100644
--- a/xen/include/asm-x86/msr.h
+++ b/xen/include/asm-x86/msr.h
@@ -3,6 +3,9 @@
 
 #ifndef __ASSEMBLY__
 
+#include <xen/smp.h>
+#include <xen/percpu.h>
+
 #define rdmsr(msr,val1,val2) \
      __asm__ __volatile__("rdmsr" \
 			  : "=a" (val1), "=d" (val2) \
@@ -142,6 +145,25 @@ static inline void wrmsrl(unsigned int msr, __u64 val)
 #define EFER_NX (1<<_EFER_NX)
 #define EFER_SVME (1<<_EFER_SVME)
 
+#ifndef __ASSEMBLY__
+
+DECLARE_PER_CPU(__u64, efer);
+
+static inline __u64 read_efer(void)
+{
+    if (!this_cpu(efer))
+        rdmsrl(MSR_EFER, this_cpu(efer));
+    return this_cpu(efer);
+}
+
+static inline void write_efer(__u64 val)
+{
+    this_cpu(efer) = val;
+    wrmsrl(MSR_EFER, val);
+}
+
+#endif
+
 /* Intel MSRs. Some also available on other CPUs */
 #define MSR_IA32_PLATFORM_ID	0x17