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authorJan Beulich <jbeulich@suse.com>2012-09-14 14:17:26 +0200
committerJan Beulich <jbeulich@suse.com>2012-09-14 14:17:26 +0200
commit15aa6c67486cc12cd30be05b441f413013912659 (patch)
treefcde6c4c5516d8c142ae39f8095830892a4e04d0 /xen/include/asm-x86/msi.h
parent3e71234b6a0587c370c6573c5efa6fcbf13a6877 (diff)
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amd iommu: use base platform MSI implementation
Given that here, other than for VT-d, the MSI interface gets surfaced through a normal PCI device, the code should use as much as possible of the "normal" MSI support code. Further, the code can (and should) follow the "normal" MSI code in distinguishing the maskable and non-maskable cases at the IRQ controller level rather than checking the respective flag in the individual actors. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Wei Wang <wei.wang2@amd.com> Acked-by: Keir Fraser <keir@xen.org>
Diffstat (limited to 'xen/include/asm-x86/msi.h')
-rw-r--r--xen/include/asm-x86/msi.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/xen/include/asm-x86/msi.h b/xen/include/asm-x86/msi.h
index 4f224466b5..0201309e26 100644
--- a/xen/include/asm-x86/msi.h
+++ b/xen/include/asm-x86/msi.h
@@ -208,6 +208,12 @@ struct msg_address {
__u32 hi_address;
} __attribute__ ((packed));
+void early_msi_init(void);
void msi_compose_msg(struct irq_desc *, struct msi_msg *);
+void __msi_set_enable(u16 seg, u8 bus, u8 slot, u8 func, int pos, int enable);
+void mask_msi_irq(struct irq_desc *);
+void unmask_msi_irq(struct irq_desc *);
+void ack_nonmaskable_msi_irq(struct irq_desc *);
+void end_nonmaskable_msi_irq(struct irq_desc *, u8 vector);
#endif /* __ASM_MSI_H */