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| author | Keir Fraser <keir.fraser@citrix.com> | 2010-06-09 07:42:19 +0100 |
|---|---|---|
| committer | Keir Fraser <keir.fraser@citrix.com> | 2010-06-09 07:42:19 +0100 |
| commit | 741367e77d6c895e51c9cd5fc0ca202ed0416c1b (patch) | |
| tree | 808a40a3a1452778392029b626b8b604f606f645 /xen/include/asm-x86/mce.h | |
| parent | 41570d67e79bb3f5be5a8ec96bbc3f7b26e435c4 (diff) | |
| download | xen-741367e77d6c895e51c9cd5fc0ca202ed0416c1b.tar.gz xen-741367e77d6c895e51c9cd5fc0ca202ed0416c1b.tar.bz2 xen-741367e77d6c895e51c9cd5fc0ca202ed0416c1b.zip | |
mce: Clean-up mcheck_init handler
Firstly and most importantly, the maxium MCA banks are hard-coded as
MAX_NR_BANKS, which is 30. This is not architecture correct. This
patch removes this definition, replacig the cpu_banks_t with
mca_banks, and provide some basic function, like
set/clear/test/alloc/free for mcabanks_t.
Secondly, remove the broadcast_check code to intel specific, since
only Intel platform support broadcast now.
Thirdly, the X86_FEATURE_MCA check and CR4_MCE enable is done in every
vendor-specifc callback, that's redundant, move it to
mcheck_init. Also, we should enable CR4_MCE only in the end of the
mcheck_init, to close the small window between CR4_enable and the mca
setup.
And we also move vmce specific code to vmce.c as vmce_init, to make
code clean.
Signed-off-by: Jiang, Yunhong <yunhong.jiang@intel.com>
Acked-By: Christoph Egger <Christoph.Egger@amd.com>
Diffstat (limited to 'xen/include/asm-x86/mce.h')
| -rw-r--r-- | xen/include/asm-x86/mce.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/xen/include/asm-x86/mce.h b/xen/include/asm-x86/mce.h index 4baa0b8021..e533c65748 100644 --- a/xen/include/asm-x86/mce.h +++ b/xen/include/asm-x86/mce.h @@ -2,8 +2,6 @@ #include <public/arch-x86/xen-mca.h> #ifndef _XEN_X86_MCE_H #define _XEN_X86_MCE_H -/* Define for GUEST MCA handling */ -#define MAX_NR_BANKS 30 /* This entry is for recording bank nodes for the impacted domain, * put into impact_header list. */ |