[HVM] Place all APIC registers into one page in native format.

With this change we can re-use code at include/asm-x86/apicdef.h,
making the code much cleaner. Also it help for future enhancement.

This patch does not change any logic except the change to
CONTROL_REG_ACCESS_NUM, which should be 0xf for CR8 access.

Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com

1 files changed, 34 insertions, 77 deletions

diff --git a/xen/include/asm-x86/hvm/vlapic.h b/xen/include/asm-x86/hvm/vlapic.h
index d2b11f3d8e..7550bf3b05 100644
--- a/xen/include/asm-x86/hvm/vlapic.h
+++ b/xen/include/asm-x86/hvm/vlapic.h
@@ -33,58 +33,31 @@ static __inline__ int find_highest_bit(unsigned long *data, int nr_bits)
 
 #define VLAPIC(v)                       (v->arch.hvm_vcpu.vlapic)
 
-#define VAPIC_ID_MASK                   0xff
-#define VAPIC_LDR_MASK                  (VAPIC_ID_MASK << 24)
 #define VLAPIC_VERSION                  0x00050014
 
-#define VLAPIC_BASE_MSR_MASK            0x00000000fffff900ULL
-#define VLAPIC_BASE_MSR_INIT_BASE_ADDR  0xfee00000U
-#define VLAPIC_BASE_MSR_BASE_ADDR_MASK  0xfffff000U
-#define VLAPIC_BASE_MSR_INIT_VALUE      (VLAPIC_BASE_MSR_INIT_BASE_ADDR | \
-                                         MSR_IA32_APICBASE_ENABLE)
 #define VLOCAL_APIC_MEM_LENGTH          (1 << 12)
 
-#define VLAPIC_LVT_TIMER                0
-#define VLAPIC_LVT_THERMAL              1
-#define VLAPIC_LVT_PERFORM              2
-#define VLAPIC_LVT_LINT0                3
-#define VLAPIC_LVT_LINT1                4
-#define VLAPIC_LVT_ERROR                5
 #define VLAPIC_LVT_NUM                  6
 
-#define VLAPIC_LVT_BIT_MASK             (1 << 16)
-#define VLAPIC_LVT_BIT_VECTOR           0xff
-#define VLAPIC_LVT_BIT_DELIMOD          (0x7 << 8)
-#define VLAPIC_LVT_BIT_DELISTATUS       (1 << 12)
-#define VLAPIC_LVT_BIT_POLARITY         (1 << 13)
-#define VLAPIC_LVT_BIT_IRR              (1 << 14)
-#define VLAPIC_LVT_BIT_TRIG             (1 << 15)
-#define VLAPIC_LVT_TIMERMODE            (1 << 17)
+#define VLAPIC_ID(vlapic)   \
+    (GET_APIC_ID(vlapic_get_reg(vlapic, APIC_ID)))
 
-#define VLAPIC_DELIV_MODE_FIXED         0x0
-#define VLAPIC_DELIV_MODE_LPRI          0x1
-#define VLAPIC_DELIV_MODE_SMI           0x2
-#define VLAPIC_DELIV_MODE_RESERVED      0x3
-#define VLAPIC_DELIV_MODE_NMI           0x4
-#define VLAPIC_DELIV_MODE_INIT          0x5
-#define VLAPIC_DELIV_MODE_STARTUP       0x6
-#define VLAPIC_DELIV_MODE_EXT           0x7
+/* followed define is not in apicdef.h */
+#define APIC_SHORT_MASK                  0xc0000
+#define APIC_DEST_NOSHORT                0x0
+#define APIC_DEST_MASK                  0x800
 
+#define vlapic_lvt_enabled(vlapic, lvt_type)    \
+    (!(vlapic_get_reg(vlapic, lvt_type) & APIC_LVT_MASKED))
 
-#define VLAPIC_NO_SHORTHAND             0x0
-#define VLAPIC_SHORTHAND_SELF           0x1
-#define VLAPIC_SHORTHAND_INCLUDE_SELF   0x2
-#define VLAPIC_SHORTHAND_EXCLUDE_SELF   0x3
+#define vlapic_lvt_vector(vlapic, lvt_type)     \
+    (vlapic_get_reg(vlapic, lvt_type) & APIC_VECTOR_MASK)
 
-#define vlapic_lvt_timer_enabled(vlapic)    \
-    (!((vlapic)->lvt[VLAPIC_LVT_TIMER] & VLAPIC_LVT_BIT_MASK))
+#define vlapic_lvt_dm(vlapic, lvt_type)           \
+    (vlapic_get_reg(vlapic, lvt_type) & APIC_MODE_MASK)
 
-#define vlapic_lvt_vector(vlapic, type)     \
-    ((vlapic)->lvt[(type)] & VLAPIC_LVT_BIT_VECTOR)
-
-#define vlapic_lvt_dm(value)            (((value) >> 8) && 7)
-#define vlapic_lvt_timer_period(vlapic)     \
-    ((vlapic)->lvt[VLAPIC_LVT_TIMER] & VLAPIC_LVT_TIMERMODE)
+#define vlapic_lvtt_period(vlapic)     \
+    (vlapic_get_reg(vlapic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC)
 
 #define _VLAPIC_GLOB_DISABLE            0x0
 #define VLAPIC_GLOB_DISABLE_MASK        0x1
@@ -98,8 +71,12 @@ static __inline__ int find_highest_bit(unsigned long *data, int nr_bits)
 #define vlapic_global_enabled(vlapic)       \
     (!(test_bit(_VLAPIC_GLOB_DISABLE, &(vlapic)->status)))
 
-#define VLAPIC_IRR(t)   ((t)->irr[0])
-#define VLAPIC_ID(t)    ((t)->id)
+#define LVT_MASK \
+    APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK
+
+#define LINT_MASK   \
+    LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY |\
+    APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER
 
 typedef struct direct_intr_info {
     int deliver_mode;
@@ -109,73 +86,53 @@ typedef struct direct_intr_info {
 #define MAX_VECTOR      256
 
 struct vlapic {
-    uint32_t           version;
     uint32_t           status;
-    uint32_t           id;
     uint32_t           vcpu_id;
+    uint64_t           apic_base_msr;
     unsigned long      base_address;
-    unsigned long      isr[BITS_TO_LONGS(MAX_VECTOR)];
-    unsigned long      irr[BITS_TO_LONGS(MAX_VECTOR)];
-    unsigned long      tmr[BITS_TO_LONGS(MAX_VECTOR)];
-    uint32_t           task_priority;
-    uint32_t           processor_priority;
-    uint32_t           logical_dest;
-    uint32_t           dest_format;
-    uint32_t           spurious_vec;
-    uint32_t           lvt[6];
-    uint32_t           timer_initial_count;
-    uint32_t           timer_current_count;
-    uint32_t           timer_divconf;
     uint32_t           timer_divide_count;
     struct timer       vlapic_timer;
     int                intr_pending_count[MAX_VECTOR];
-    s_time_t           timer_current_update;
-    uint32_t           icr_high;
-    uint32_t           icr_low;
+    s_time_t           timer_last_update;
     direct_intr_info_t direct_intr;
     uint32_t           err_status;
-    unsigned long      init_ticks;
     uint32_t           err_write_count;
-    uint64_t           apic_base_msr;
     struct vcpu        *vcpu;
     struct domain      *domain;
+    struct page_info   *regs_page;
+    void               *regs;
 };
 
-static inline int vlapic_set_irq(struct vlapic *t, uint8_t vec, uint8_t trig)
+static inline int vlapic_set_irq(struct vlapic *vlapic,
+                                 uint8_t vec, uint8_t trig)
 {
     int ret;
 
-    ret = test_and_set_bit(vec, &t->irr[0]);
+    ret = test_and_set_bit(vec, vlapic->regs + APIC_IRR);
     if ( trig )
-       set_bit(vec, &t->tmr[0]);
+        set_bit(vec, vlapic->regs + APIC_TMR);
 
     /* We may need to wake up target vcpu, besides set pending bit here */
     return ret;
 }
 
-static inline int vlapic_timer_active(struct vlapic *vlapic)
+static inline uint32_t vlapic_get_reg(struct vlapic *vlapic, uint32_t reg)
 {
-    return active_timer(&vlapic->vlapic_timer);
+    return  *( (uint32_t *)(vlapic->regs + reg));
 }
 
-int vlapic_find_highest_irr(struct vlapic *vlapic);
-
-int vlapic_find_highest_isr(struct vlapic *vlapic);
-
-static uint32_t inline vlapic_get_base_address(struct vlapic *vlapic)
+static inline void vlapic_set_reg(struct vlapic *vlapic,
+  uint32_t reg, uint32_t val)
 {
-    return (vlapic->apic_base_msr & VLAPIC_BASE_MSR_BASE_ADDR_MASK);
+    *((uint32_t *)(vlapic->regs + reg)) = val;
 }
 
+
 void vlapic_post_injection(struct vcpu* v, int vector, int deliver_mode);
 
 int cpu_has_apic_interrupt(struct vcpu* v);
 int cpu_get_apic_interrupt(struct vcpu* v, int *mode);
 
-extern uint32_t vlapic_update_ppr(struct vlapic *vlapic);
-
-int vlapic_update(struct vcpu *v);
-
 extern int vlapic_init(struct vcpu *vc);
 
 extern void vlapic_msr_set(struct vlapic *vlapic, uint64_t value);